1 /* 2 * drivers/net/phy/marvell.c 3 * 4 * Driver for Marvell PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 */ 18 #include <linux/kernel.h> 19 #include <linux/string.h> 20 #include <linux/ctype.h> 21 #include <linux/errno.h> 22 #include <linux/unistd.h> 23 #include <linux/hwmon.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/netdevice.h> 28 #include <linux/etherdevice.h> 29 #include <linux/skbuff.h> 30 #include <linux/spinlock.h> 31 #include <linux/mm.h> 32 #include <linux/module.h> 33 #include <linux/mii.h> 34 #include <linux/ethtool.h> 35 #include <linux/phy.h> 36 #include <linux/marvell_phy.h> 37 #include <linux/of.h> 38 39 #include <linux/io.h> 40 #include <asm/irq.h> 41 #include <linux/uaccess.h> 42 43 #define MII_MARVELL_PHY_PAGE 22 44 45 #define MII_M1011_IEVENT 0x13 46 #define MII_M1011_IEVENT_CLEAR 0x0000 47 48 #define MII_M1011_IMASK 0x12 49 #define MII_M1011_IMASK_INIT 0x6400 50 #define MII_M1011_IMASK_CLEAR 0x0000 51 52 #define MII_M1011_PHY_SCR 0x10 53 #define MII_M1011_PHY_SCR_MDI 0x0000 54 #define MII_M1011_PHY_SCR_MDI_X 0x0020 55 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 56 57 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16 58 #define MII_M1145_PHY_EXT_SR 0x1b 59 #define MII_M1145_PHY_EXT_CR 0x14 60 #define MII_M1145_RGMII_RX_DELAY 0x0080 61 #define MII_M1145_RGMII_TX_DELAY 0x0002 62 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4 63 #define MII_M1145_HWCFG_MODE_MASK 0xf 64 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000 65 66 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4 67 #define MII_M1145_HWCFG_MODE_MASK 0xf 68 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000 69 70 #define MII_M1111_PHY_LED_CONTROL 0x18 71 #define MII_M1111_PHY_LED_DIRECT 0x4100 72 #define MII_M1111_PHY_LED_COMBINE 0x411c 73 #define MII_M1111_PHY_EXT_CR 0x14 74 #define MII_M1111_RX_DELAY 0x80 75 #define MII_M1111_TX_DELAY 0x2 76 #define MII_M1111_PHY_EXT_SR 0x1b 77 78 #define MII_M1111_HWCFG_MODE_MASK 0xf 79 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb 80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 82 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9 83 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 84 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 85 86 #define MII_M1111_COPPER 0 87 #define MII_M1111_FIBER 1 88 89 #define MII_88E1121_PHY_MSCR_PAGE 2 90 #define MII_88E1121_PHY_MSCR_REG 21 91 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5) 92 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) 93 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4)) 94 95 #define MII_88E1121_MISC_TEST 0x1a 96 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00 97 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8 98 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7) 99 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6) 100 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5) 101 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f 102 103 #define MII_88E1510_TEMP_SENSOR 0x1b 104 #define MII_88E1510_TEMP_SENSOR_MASK 0xff 105 106 #define MII_88E1318S_PHY_MSCR1_REG 16 107 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6) 108 109 /* Copper Specific Interrupt Enable Register */ 110 #define MII_88E1318S_PHY_CSIER 0x12 111 /* WOL Event Interrupt Enable */ 112 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) 113 114 /* LED Timer Control Register */ 115 #define MII_88E1318S_PHY_LED_PAGE 0x03 116 #define MII_88E1318S_PHY_LED_TCR 0x12 117 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) 118 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7) 119 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11) 120 121 /* Magic Packet MAC address registers */ 122 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17 123 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18 124 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19 125 126 #define MII_88E1318S_PHY_WOL_PAGE 0x11 127 #define MII_88E1318S_PHY_WOL_CTRL 0x10 128 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12) 129 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14) 130 131 #define MII_88E1121_PHY_LED_CTRL 16 132 #define MII_88E1121_PHY_LED_PAGE 3 133 #define MII_88E1121_PHY_LED_DEF 0x0030 134 135 #define MII_M1011_PHY_STATUS 0x11 136 #define MII_M1011_PHY_STATUS_1000 0x8000 137 #define MII_M1011_PHY_STATUS_100 0x4000 138 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 139 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 140 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 141 #define MII_M1011_PHY_STATUS_LINK 0x0400 142 143 #define MII_M1116R_CONTROL_REG_MAC 21 144 145 #define MII_88E3016_PHY_SPEC_CTRL 0x10 146 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200 147 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030 148 149 #define MII_88E1510_GEN_CTRL_REG_1 0x14 150 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7 151 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */ 152 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */ 153 154 #define LPA_FIBER_1000HALF 0x40 155 #define LPA_FIBER_1000FULL 0x20 156 157 #define LPA_PAUSE_FIBER 0x180 158 #define LPA_PAUSE_ASYM_FIBER 0x100 159 160 #define ADVERTISE_FIBER_1000HALF 0x40 161 #define ADVERTISE_FIBER_1000FULL 0x20 162 163 #define ADVERTISE_PAUSE_FIBER 0x180 164 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100 165 166 #define REGISTER_LINK_STATUS 0x400 167 #define NB_FIBER_STATS 1 168 169 MODULE_DESCRIPTION("Marvell PHY driver"); 170 MODULE_AUTHOR("Andy Fleming"); 171 MODULE_LICENSE("GPL"); 172 173 struct marvell_hw_stat { 174 const char *string; 175 u8 page; 176 u8 reg; 177 u8 bits; 178 }; 179 180 static struct marvell_hw_stat marvell_hw_stats[] = { 181 { "phy_receive_errors_copper", 0, 21, 16}, 182 { "phy_idle_errors", 0, 10, 8 }, 183 { "phy_receive_errors_fiber", 1, 21, 16}, 184 }; 185 186 struct marvell_priv { 187 u64 stats[ARRAY_SIZE(marvell_hw_stats)]; 188 char *hwmon_name; 189 struct device *hwmon_dev; 190 }; 191 192 static int marvell_ack_interrupt(struct phy_device *phydev) 193 { 194 int err; 195 196 /* Clear the interrupts by reading the reg */ 197 err = phy_read(phydev, MII_M1011_IEVENT); 198 199 if (err < 0) 200 return err; 201 202 return 0; 203 } 204 205 static int marvell_config_intr(struct phy_device *phydev) 206 { 207 int err; 208 209 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 210 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 211 else 212 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 213 214 return err; 215 } 216 217 static int marvell_set_polarity(struct phy_device *phydev, int polarity) 218 { 219 int reg; 220 int err; 221 int val; 222 223 /* get the current settings */ 224 reg = phy_read(phydev, MII_M1011_PHY_SCR); 225 if (reg < 0) 226 return reg; 227 228 val = reg; 229 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS; 230 switch (polarity) { 231 case ETH_TP_MDI: 232 val |= MII_M1011_PHY_SCR_MDI; 233 break; 234 case ETH_TP_MDI_X: 235 val |= MII_M1011_PHY_SCR_MDI_X; 236 break; 237 case ETH_TP_MDI_AUTO: 238 case ETH_TP_MDI_INVALID: 239 default: 240 val |= MII_M1011_PHY_SCR_AUTO_CROSS; 241 break; 242 } 243 244 if (val != reg) { 245 /* Set the new polarity value in the register */ 246 err = phy_write(phydev, MII_M1011_PHY_SCR, val); 247 if (err) 248 return err; 249 } 250 251 return 0; 252 } 253 254 static int marvell_config_aneg(struct phy_device *phydev) 255 { 256 int err; 257 258 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); 259 if (err < 0) 260 return err; 261 262 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, 263 MII_M1111_PHY_LED_DIRECT); 264 if (err < 0) 265 return err; 266 267 err = genphy_config_aneg(phydev); 268 if (err < 0) 269 return err; 270 271 if (phydev->autoneg != AUTONEG_ENABLE) { 272 int bmcr; 273 274 /* 275 * A write to speed/duplex bits (that is performed by 276 * genphy_config_aneg() call above) must be followed by 277 * a software reset. Otherwise, the write has no effect. 278 */ 279 bmcr = phy_read(phydev, MII_BMCR); 280 if (bmcr < 0) 281 return bmcr; 282 283 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); 284 if (err < 0) 285 return err; 286 } 287 288 return 0; 289 } 290 291 static int m88e1101_config_aneg(struct phy_device *phydev) 292 { 293 int err; 294 295 /* This Marvell PHY has an errata which requires 296 * that certain registers get written in order 297 * to restart autonegotiation 298 */ 299 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 300 301 if (err < 0) 302 return err; 303 304 err = phy_write(phydev, 0x1d, 0x1f); 305 if (err < 0) 306 return err; 307 308 err = phy_write(phydev, 0x1e, 0x200c); 309 if (err < 0) 310 return err; 311 312 err = phy_write(phydev, 0x1d, 0x5); 313 if (err < 0) 314 return err; 315 316 err = phy_write(phydev, 0x1e, 0); 317 if (err < 0) 318 return err; 319 320 err = phy_write(phydev, 0x1e, 0x100); 321 if (err < 0) 322 return err; 323 324 return marvell_config_aneg(phydev); 325 } 326 327 static int m88e1111_config_aneg(struct phy_device *phydev) 328 { 329 int err; 330 331 /* The Marvell PHY has an errata which requires 332 * that certain registers get written in order 333 * to restart autonegotiation 334 */ 335 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 336 337 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); 338 if (err < 0) 339 return err; 340 341 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, 342 MII_M1111_PHY_LED_DIRECT); 343 if (err < 0) 344 return err; 345 346 err = genphy_config_aneg(phydev); 347 if (err < 0) 348 return err; 349 350 if (phydev->autoneg != AUTONEG_ENABLE) { 351 int bmcr; 352 353 /* A write to speed/duplex bits (that is performed by 354 * genphy_config_aneg() call above) must be followed by 355 * a software reset. Otherwise, the write has no effect. 356 */ 357 bmcr = phy_read(phydev, MII_BMCR); 358 if (bmcr < 0) 359 return bmcr; 360 361 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); 362 if (err < 0) 363 return err; 364 } 365 366 return 0; 367 } 368 369 #ifdef CONFIG_OF_MDIO 370 /* 371 * Set and/or override some configuration registers based on the 372 * marvell,reg-init property stored in the of_node for the phydev. 373 * 374 * marvell,reg-init = <reg-page reg mask value>,...; 375 * 376 * There may be one or more sets of <reg-page reg mask value>: 377 * 378 * reg-page: which register bank to use. 379 * reg: the register. 380 * mask: if non-zero, ANDed with existing register value. 381 * value: ORed with the masked value and written to the regiser. 382 * 383 */ 384 static int marvell_of_reg_init(struct phy_device *phydev) 385 { 386 const __be32 *paddr; 387 int len, i, saved_page, current_page, ret; 388 389 if (!phydev->mdio.dev.of_node) 390 return 0; 391 392 paddr = of_get_property(phydev->mdio.dev.of_node, 393 "marvell,reg-init", &len); 394 if (!paddr || len < (4 * sizeof(*paddr))) 395 return 0; 396 397 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE); 398 if (saved_page < 0) 399 return saved_page; 400 current_page = saved_page; 401 402 ret = 0; 403 len /= sizeof(*paddr); 404 for (i = 0; i < len - 3; i += 4) { 405 u16 reg_page = be32_to_cpup(paddr + i); 406 u16 reg = be32_to_cpup(paddr + i + 1); 407 u16 mask = be32_to_cpup(paddr + i + 2); 408 u16 val_bits = be32_to_cpup(paddr + i + 3); 409 int val; 410 411 if (reg_page != current_page) { 412 current_page = reg_page; 413 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page); 414 if (ret < 0) 415 goto err; 416 } 417 418 val = 0; 419 if (mask) { 420 val = phy_read(phydev, reg); 421 if (val < 0) { 422 ret = val; 423 goto err; 424 } 425 val &= mask; 426 } 427 val |= val_bits; 428 429 ret = phy_write(phydev, reg, val); 430 if (ret < 0) 431 goto err; 432 433 } 434 err: 435 if (current_page != saved_page) { 436 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page); 437 if (ret == 0) 438 ret = i; 439 } 440 return ret; 441 } 442 #else 443 static int marvell_of_reg_init(struct phy_device *phydev) 444 { 445 return 0; 446 } 447 #endif /* CONFIG_OF_MDIO */ 448 449 static int m88e1121_config_aneg(struct phy_device *phydev) 450 { 451 int err, oldpage, mscr; 452 453 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 454 455 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 456 MII_88E1121_PHY_MSCR_PAGE); 457 if (err < 0) 458 return err; 459 460 if (phy_interface_is_rgmii(phydev)) { 461 462 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) & 463 MII_88E1121_PHY_MSCR_DELAY_MASK; 464 465 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 466 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | 467 MII_88E1121_PHY_MSCR_TX_DELAY); 468 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 469 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; 470 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 471 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; 472 473 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); 474 if (err < 0) 475 return err; 476 } 477 478 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 479 480 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 481 if (err < 0) 482 return err; 483 484 err = phy_write(phydev, MII_M1011_PHY_SCR, 485 MII_M1011_PHY_SCR_AUTO_CROSS); 486 if (err < 0) 487 return err; 488 489 return genphy_config_aneg(phydev); 490 } 491 492 static int m88e1318_config_aneg(struct phy_device *phydev) 493 { 494 int err, oldpage, mscr; 495 496 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 497 498 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 499 MII_88E1121_PHY_MSCR_PAGE); 500 if (err < 0) 501 return err; 502 503 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG); 504 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD; 505 506 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr); 507 if (err < 0) 508 return err; 509 510 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 511 if (err < 0) 512 return err; 513 514 return m88e1121_config_aneg(phydev); 515 } 516 517 /** 518 * ethtool_adv_to_fiber_adv_t 519 * @ethadv: the ethtool advertisement settings 520 * 521 * A small helper function that translates ethtool advertisement 522 * settings to phy autonegotiation advertisements for the 523 * MII_ADV register for fiber link. 524 */ 525 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv) 526 { 527 u32 result = 0; 528 529 if (ethadv & ADVERTISED_1000baseT_Half) 530 result |= ADVERTISE_FIBER_1000HALF; 531 if (ethadv & ADVERTISED_1000baseT_Full) 532 result |= ADVERTISE_FIBER_1000FULL; 533 534 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP)) 535 result |= LPA_PAUSE_ASYM_FIBER; 536 else if (ethadv & ADVERTISE_PAUSE_CAP) 537 result |= (ADVERTISE_PAUSE_FIBER 538 & (~ADVERTISE_PAUSE_ASYM_FIBER)); 539 540 return result; 541 } 542 543 /** 544 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR 545 * @phydev: target phy_device struct 546 * 547 * Description: If auto-negotiation is enabled, we configure the 548 * advertising, and then restart auto-negotiation. If it is not 549 * enabled, then we write the BMCR. Adapted for fiber link in 550 * some Marvell's devices. 551 */ 552 static int marvell_config_aneg_fiber(struct phy_device *phydev) 553 { 554 int changed = 0; 555 int err; 556 int adv, oldadv; 557 u32 advertise; 558 559 if (phydev->autoneg != AUTONEG_ENABLE) 560 return genphy_setup_forced(phydev); 561 562 /* Only allow advertising what this PHY supports */ 563 phydev->advertising &= phydev->supported; 564 advertise = phydev->advertising; 565 566 /* Setup fiber advertisement */ 567 adv = phy_read(phydev, MII_ADVERTISE); 568 if (adv < 0) 569 return adv; 570 571 oldadv = adv; 572 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL 573 | LPA_PAUSE_FIBER); 574 adv |= ethtool_adv_to_fiber_adv_t(advertise); 575 576 if (adv != oldadv) { 577 err = phy_write(phydev, MII_ADVERTISE, adv); 578 if (err < 0) 579 return err; 580 581 changed = 1; 582 } 583 584 if (changed == 0) { 585 /* Advertisement hasn't changed, but maybe aneg was never on to 586 * begin with? Or maybe phy was isolated? 587 */ 588 int ctl = phy_read(phydev, MII_BMCR); 589 590 if (ctl < 0) 591 return ctl; 592 593 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) 594 changed = 1; /* do restart aneg */ 595 } 596 597 /* Only restart aneg if we are advertising something different 598 * than we were before. 599 */ 600 if (changed > 0) 601 changed = genphy_restart_aneg(phydev); 602 603 return changed; 604 } 605 606 static int m88e1510_config_aneg(struct phy_device *phydev) 607 { 608 int err; 609 610 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 611 if (err < 0) 612 goto error; 613 614 /* Configure the copper link first */ 615 err = m88e1318_config_aneg(phydev); 616 if (err < 0) 617 goto error; 618 619 /* Then the fiber link */ 620 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); 621 if (err < 0) 622 goto error; 623 624 err = marvell_config_aneg_fiber(phydev); 625 if (err < 0) 626 goto error; 627 628 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 629 630 error: 631 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 632 return err; 633 } 634 635 static int marvell_config_init(struct phy_device *phydev) 636 { 637 /* Set registers from marvell,reg-init DT property */ 638 return marvell_of_reg_init(phydev); 639 } 640 641 static int m88e1116r_config_init(struct phy_device *phydev) 642 { 643 int temp; 644 int err; 645 646 temp = phy_read(phydev, MII_BMCR); 647 temp |= BMCR_RESET; 648 err = phy_write(phydev, MII_BMCR, temp); 649 if (err < 0) 650 return err; 651 652 mdelay(500); 653 654 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 655 if (err < 0) 656 return err; 657 658 temp = phy_read(phydev, MII_M1011_PHY_SCR); 659 temp |= (7 << 12); /* max number of gigabit attempts */ 660 temp |= (1 << 11); /* enable downshift */ 661 temp |= MII_M1011_PHY_SCR_AUTO_CROSS; 662 err = phy_write(phydev, MII_M1011_PHY_SCR, temp); 663 if (err < 0) 664 return err; 665 666 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2); 667 if (err < 0) 668 return err; 669 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC); 670 temp |= (1 << 5); 671 temp |= (1 << 4); 672 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp); 673 if (err < 0) 674 return err; 675 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 676 if (err < 0) 677 return err; 678 679 temp = phy_read(phydev, MII_BMCR); 680 temp |= BMCR_RESET; 681 err = phy_write(phydev, MII_BMCR, temp); 682 if (err < 0) 683 return err; 684 685 mdelay(500); 686 687 return marvell_config_init(phydev); 688 } 689 690 static int m88e3016_config_init(struct phy_device *phydev) 691 { 692 int reg; 693 694 /* Enable Scrambler and Auto-Crossover */ 695 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL); 696 if (reg < 0) 697 return reg; 698 699 reg &= ~MII_88E3016_DISABLE_SCRAMBLER; 700 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER; 701 702 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg); 703 if (reg < 0) 704 return reg; 705 706 return marvell_config_init(phydev); 707 } 708 709 static int m88e1111_config_init(struct phy_device *phydev) 710 { 711 int err; 712 int temp; 713 714 if (phy_interface_is_rgmii(phydev)) { 715 716 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 717 if (temp < 0) 718 return temp; 719 720 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 721 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 722 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 723 temp &= ~MII_M1111_TX_DELAY; 724 temp |= MII_M1111_RX_DELAY; 725 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 726 temp &= ~MII_M1111_RX_DELAY; 727 temp |= MII_M1111_TX_DELAY; 728 } 729 730 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 731 if (err < 0) 732 return err; 733 734 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 735 if (temp < 0) 736 return temp; 737 738 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 739 740 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) 741 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; 742 else 743 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; 744 745 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 746 if (err < 0) 747 return err; 748 } 749 750 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 751 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 752 if (temp < 0) 753 return temp; 754 755 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 756 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; 757 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; 758 759 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 760 if (err < 0) 761 return err; 762 763 /* make sure copper is selected */ 764 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE); 765 if (err < 0) 766 return err; 767 768 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 769 err & (~0xff)); 770 if (err < 0) 771 return err; 772 } 773 774 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 775 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 776 if (temp < 0) 777 return temp; 778 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 779 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 780 if (err < 0) 781 return err; 782 783 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 784 if (temp < 0) 785 return temp; 786 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); 787 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; 788 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 789 if (err < 0) 790 return err; 791 792 /* soft reset */ 793 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 794 if (err < 0) 795 return err; 796 do 797 temp = phy_read(phydev, MII_BMCR); 798 while (temp & BMCR_RESET); 799 800 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 801 if (temp < 0) 802 return temp; 803 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); 804 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; 805 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 806 if (err < 0) 807 return err; 808 } 809 810 err = marvell_of_reg_init(phydev); 811 if (err < 0) 812 return err; 813 814 return phy_write(phydev, MII_BMCR, BMCR_RESET); 815 } 816 817 static int m88e1121_config_init(struct phy_device *phydev) 818 { 819 int err, oldpage; 820 821 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 822 823 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); 824 if (err < 0) 825 return err; 826 827 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */ 828 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL, 829 MII_88E1121_PHY_LED_DEF); 830 if (err < 0) 831 return err; 832 833 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 834 835 /* Set marvell,reg-init configuration from device tree */ 836 return marvell_config_init(phydev); 837 } 838 839 static int m88e1510_config_init(struct phy_device *phydev) 840 { 841 int err; 842 int temp; 843 844 /* SGMII-to-Copper mode initialization */ 845 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 846 /* Select page 18 */ 847 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18); 848 if (err < 0) 849 return err; 850 851 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 852 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1); 853 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK; 854 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII; 855 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp); 856 if (err < 0) 857 return err; 858 859 /* PHY reset is necessary after changing MODE[2:0] */ 860 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET; 861 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp); 862 if (err < 0) 863 return err; 864 865 /* Reset page selection */ 866 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 867 if (err < 0) 868 return err; 869 } 870 871 return m88e1121_config_init(phydev); 872 } 873 874 static int m88e1118_config_aneg(struct phy_device *phydev) 875 { 876 int err; 877 878 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 879 if (err < 0) 880 return err; 881 882 err = phy_write(phydev, MII_M1011_PHY_SCR, 883 MII_M1011_PHY_SCR_AUTO_CROSS); 884 if (err < 0) 885 return err; 886 887 err = genphy_config_aneg(phydev); 888 return 0; 889 } 890 891 static int m88e1118_config_init(struct phy_device *phydev) 892 { 893 int err; 894 895 /* Change address */ 896 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); 897 if (err < 0) 898 return err; 899 900 /* Enable 1000 Mbit */ 901 err = phy_write(phydev, 0x15, 0x1070); 902 if (err < 0) 903 return err; 904 905 /* Change address */ 906 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003); 907 if (err < 0) 908 return err; 909 910 /* Adjust LED Control */ 911 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS) 912 err = phy_write(phydev, 0x10, 0x1100); 913 else 914 err = phy_write(phydev, 0x10, 0x021e); 915 if (err < 0) 916 return err; 917 918 err = marvell_of_reg_init(phydev); 919 if (err < 0) 920 return err; 921 922 /* Reset address */ 923 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); 924 if (err < 0) 925 return err; 926 927 return phy_write(phydev, MII_BMCR, BMCR_RESET); 928 } 929 930 static int m88e1149_config_init(struct phy_device *phydev) 931 { 932 int err; 933 934 /* Change address */ 935 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); 936 if (err < 0) 937 return err; 938 939 /* Enable 1000 Mbit */ 940 err = phy_write(phydev, 0x15, 0x1048); 941 if (err < 0) 942 return err; 943 944 err = marvell_of_reg_init(phydev); 945 if (err < 0) 946 return err; 947 948 /* Reset address */ 949 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); 950 if (err < 0) 951 return err; 952 953 return phy_write(phydev, MII_BMCR, BMCR_RESET); 954 } 955 956 static int m88e1145_config_init(struct phy_device *phydev) 957 { 958 int err; 959 int temp; 960 961 /* Take care of errata E0 & E1 */ 962 err = phy_write(phydev, 0x1d, 0x001b); 963 if (err < 0) 964 return err; 965 966 err = phy_write(phydev, 0x1e, 0x418f); 967 if (err < 0) 968 return err; 969 970 err = phy_write(phydev, 0x1d, 0x0016); 971 if (err < 0) 972 return err; 973 974 err = phy_write(phydev, 0x1e, 0xa2da); 975 if (err < 0) 976 return err; 977 978 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 979 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); 980 if (temp < 0) 981 return temp; 982 983 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); 984 985 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); 986 if (err < 0) 987 return err; 988 989 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { 990 err = phy_write(phydev, 0x1d, 0x0012); 991 if (err < 0) 992 return err; 993 994 temp = phy_read(phydev, 0x1e); 995 if (temp < 0) 996 return temp; 997 998 temp &= 0xf03f; 999 temp |= 2 << 9; /* 36 ohm */ 1000 temp |= 2 << 6; /* 39 ohm */ 1001 1002 err = phy_write(phydev, 0x1e, temp); 1003 if (err < 0) 1004 return err; 1005 1006 err = phy_write(phydev, 0x1d, 0x3); 1007 if (err < 0) 1008 return err; 1009 1010 err = phy_write(phydev, 0x1e, 0x8000); 1011 if (err < 0) 1012 return err; 1013 } 1014 } 1015 1016 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1017 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR); 1018 if (temp < 0) 1019 return temp; 1020 1021 temp &= ~MII_M1145_HWCFG_MODE_MASK; 1022 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK; 1023 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO; 1024 1025 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp); 1026 if (err < 0) 1027 return err; 1028 } 1029 1030 err = marvell_of_reg_init(phydev); 1031 if (err < 0) 1032 return err; 1033 1034 return 0; 1035 } 1036 1037 /** 1038 * fiber_lpa_to_ethtool_lpa_t 1039 * @lpa: value of the MII_LPA register for fiber link 1040 * 1041 * A small helper function that translates MII_LPA 1042 * bits to ethtool LP advertisement settings. 1043 */ 1044 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa) 1045 { 1046 u32 result = 0; 1047 1048 if (lpa & LPA_FIBER_1000HALF) 1049 result |= ADVERTISED_1000baseT_Half; 1050 if (lpa & LPA_FIBER_1000FULL) 1051 result |= ADVERTISED_1000baseT_Full; 1052 1053 return result; 1054 } 1055 1056 /** 1057 * marvell_update_link - update link status in real time in @phydev 1058 * @phydev: target phy_device struct 1059 * 1060 * Description: Update the value in phydev->link to reflect the 1061 * current link value. 1062 */ 1063 static int marvell_update_link(struct phy_device *phydev, int fiber) 1064 { 1065 int status; 1066 1067 /* Use the generic register for copper link, or specific 1068 * register for fiber case */ 1069 if (fiber) { 1070 status = phy_read(phydev, MII_M1011_PHY_STATUS); 1071 if (status < 0) 1072 return status; 1073 1074 if ((status & REGISTER_LINK_STATUS) == 0) 1075 phydev->link = 0; 1076 else 1077 phydev->link = 1; 1078 } else { 1079 return genphy_update_link(phydev); 1080 } 1081 1082 return 0; 1083 } 1084 1085 /* marvell_read_status_page 1086 * 1087 * Description: 1088 * Check the link, then figure out the current state 1089 * by comparing what we advertise with what the link partner 1090 * advertises. Start by checking the gigabit possibilities, 1091 * then move on to 10/100. 1092 */ 1093 static int marvell_read_status_page(struct phy_device *phydev, int page) 1094 { 1095 int adv; 1096 int err; 1097 int lpa; 1098 int lpagb; 1099 int status = 0; 1100 int fiber; 1101 1102 /* Detect and update the link, but return if there 1103 * was an error */ 1104 if (page == MII_M1111_FIBER) 1105 fiber = 1; 1106 else 1107 fiber = 0; 1108 1109 err = marvell_update_link(phydev, fiber); 1110 if (err) 1111 return err; 1112 1113 if (AUTONEG_ENABLE == phydev->autoneg) { 1114 status = phy_read(phydev, MII_M1011_PHY_STATUS); 1115 if (status < 0) 1116 return status; 1117 1118 lpa = phy_read(phydev, MII_LPA); 1119 if (lpa < 0) 1120 return lpa; 1121 1122 lpagb = phy_read(phydev, MII_STAT1000); 1123 if (lpagb < 0) 1124 return lpagb; 1125 1126 adv = phy_read(phydev, MII_ADVERTISE); 1127 if (adv < 0) 1128 return adv; 1129 1130 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) 1131 phydev->duplex = DUPLEX_FULL; 1132 else 1133 phydev->duplex = DUPLEX_HALF; 1134 1135 status = status & MII_M1011_PHY_STATUS_SPD_MASK; 1136 phydev->pause = phydev->asym_pause = 0; 1137 1138 switch (status) { 1139 case MII_M1011_PHY_STATUS_1000: 1140 phydev->speed = SPEED_1000; 1141 break; 1142 1143 case MII_M1011_PHY_STATUS_100: 1144 phydev->speed = SPEED_100; 1145 break; 1146 1147 default: 1148 phydev->speed = SPEED_10; 1149 break; 1150 } 1151 1152 if (!fiber) { 1153 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) | 1154 mii_lpa_to_ethtool_lpa_t(lpa); 1155 1156 if (phydev->duplex == DUPLEX_FULL) { 1157 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; 1158 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 1159 } 1160 } else { 1161 /* The fiber link is only 1000M capable */ 1162 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa); 1163 1164 if (phydev->duplex == DUPLEX_FULL) { 1165 if (!(lpa & LPA_PAUSE_FIBER)) { 1166 phydev->pause = 0; 1167 phydev->asym_pause = 0; 1168 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) { 1169 phydev->pause = 1; 1170 phydev->asym_pause = 1; 1171 } else { 1172 phydev->pause = 1; 1173 phydev->asym_pause = 0; 1174 } 1175 } 1176 } 1177 } else { 1178 int bmcr = phy_read(phydev, MII_BMCR); 1179 1180 if (bmcr < 0) 1181 return bmcr; 1182 1183 if (bmcr & BMCR_FULLDPLX) 1184 phydev->duplex = DUPLEX_FULL; 1185 else 1186 phydev->duplex = DUPLEX_HALF; 1187 1188 if (bmcr & BMCR_SPEED1000) 1189 phydev->speed = SPEED_1000; 1190 else if (bmcr & BMCR_SPEED100) 1191 phydev->speed = SPEED_100; 1192 else 1193 phydev->speed = SPEED_10; 1194 1195 phydev->pause = phydev->asym_pause = 0; 1196 phydev->lp_advertising = 0; 1197 } 1198 1199 return 0; 1200 } 1201 1202 /* marvell_read_status 1203 * 1204 * Some Marvell's phys have two modes: fiber and copper. 1205 * Both need status checked. 1206 * Description: 1207 * First, check the fiber link and status. 1208 * If the fiber link is down, check the copper link and status which 1209 * will be the default value if both link are down. 1210 */ 1211 static int marvell_read_status(struct phy_device *phydev) 1212 { 1213 int err; 1214 1215 /* Check the fiber mode first */ 1216 if (phydev->supported & SUPPORTED_FIBRE && 1217 phydev->interface != PHY_INTERFACE_MODE_SGMII) { 1218 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); 1219 if (err < 0) 1220 goto error; 1221 1222 err = marvell_read_status_page(phydev, MII_M1111_FIBER); 1223 if (err < 0) 1224 goto error; 1225 1226 /* If the fiber link is up, it is the selected and used link. 1227 * In this case, we need to stay in the fiber page. 1228 * Please to be careful about that, avoid to restore Copper page 1229 * in other functions which could break the behaviour 1230 * for some fiber phy like 88E1512. 1231 * */ 1232 if (phydev->link) 1233 return 0; 1234 1235 /* If fiber link is down, check and save copper mode state */ 1236 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 1237 if (err < 0) 1238 goto error; 1239 } 1240 1241 return marvell_read_status_page(phydev, MII_M1111_COPPER); 1242 1243 error: 1244 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 1245 return err; 1246 } 1247 1248 /* marvell_suspend 1249 * 1250 * Some Marvell's phys have two modes: fiber and copper. 1251 * Both need to be suspended 1252 */ 1253 static int marvell_suspend(struct phy_device *phydev) 1254 { 1255 int err; 1256 1257 /* Suspend the fiber mode first */ 1258 if (!(phydev->supported & SUPPORTED_FIBRE)) { 1259 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); 1260 if (err < 0) 1261 goto error; 1262 1263 /* With the page set, use the generic suspend */ 1264 err = genphy_suspend(phydev); 1265 if (err < 0) 1266 goto error; 1267 1268 /* Then, the copper link */ 1269 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 1270 if (err < 0) 1271 goto error; 1272 } 1273 1274 /* With the page set, use the generic suspend */ 1275 return genphy_suspend(phydev); 1276 1277 error: 1278 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 1279 return err; 1280 } 1281 1282 /* marvell_resume 1283 * 1284 * Some Marvell's phys have two modes: fiber and copper. 1285 * Both need to be resumed 1286 */ 1287 static int marvell_resume(struct phy_device *phydev) 1288 { 1289 int err; 1290 1291 /* Resume the fiber mode first */ 1292 if (!(phydev->supported & SUPPORTED_FIBRE)) { 1293 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER); 1294 if (err < 0) 1295 goto error; 1296 1297 /* With the page set, use the generic resume */ 1298 err = genphy_resume(phydev); 1299 if (err < 0) 1300 goto error; 1301 1302 /* Then, the copper link */ 1303 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 1304 if (err < 0) 1305 goto error; 1306 } 1307 1308 /* With the page set, use the generic resume */ 1309 return genphy_resume(phydev); 1310 1311 error: 1312 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER); 1313 return err; 1314 } 1315 1316 static int marvell_aneg_done(struct phy_device *phydev) 1317 { 1318 int retval = phy_read(phydev, MII_M1011_PHY_STATUS); 1319 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED); 1320 } 1321 1322 static int m88e1121_did_interrupt(struct phy_device *phydev) 1323 { 1324 int imask; 1325 1326 imask = phy_read(phydev, MII_M1011_IEVENT); 1327 1328 if (imask & MII_M1011_IMASK_INIT) 1329 return 1; 1330 1331 return 0; 1332 } 1333 1334 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 1335 { 1336 wol->supported = WAKE_MAGIC; 1337 wol->wolopts = 0; 1338 1339 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 1340 MII_88E1318S_PHY_WOL_PAGE) < 0) 1341 return; 1342 1343 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) & 1344 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE) 1345 wol->wolopts |= WAKE_MAGIC; 1346 1347 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0) 1348 return; 1349 } 1350 1351 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 1352 { 1353 int err, oldpage, temp; 1354 1355 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 1356 1357 if (wol->wolopts & WAKE_MAGIC) { 1358 /* Explicitly switch to page 0x00, just to be sure */ 1359 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00); 1360 if (err < 0) 1361 return err; 1362 1363 /* Enable the WOL interrupt */ 1364 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER); 1365 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE; 1366 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp); 1367 if (err < 0) 1368 return err; 1369 1370 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1371 MII_88E1318S_PHY_LED_PAGE); 1372 if (err < 0) 1373 return err; 1374 1375 /* Setup LED[2] as interrupt pin (active low) */ 1376 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR); 1377 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT; 1378 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE; 1379 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW; 1380 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp); 1381 if (err < 0) 1382 return err; 1383 1384 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1385 MII_88E1318S_PHY_WOL_PAGE); 1386 if (err < 0) 1387 return err; 1388 1389 /* Store the device address for the magic packet */ 1390 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2, 1391 ((phydev->attached_dev->dev_addr[5] << 8) | 1392 phydev->attached_dev->dev_addr[4])); 1393 if (err < 0) 1394 return err; 1395 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1, 1396 ((phydev->attached_dev->dev_addr[3] << 8) | 1397 phydev->attached_dev->dev_addr[2])); 1398 if (err < 0) 1399 return err; 1400 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0, 1401 ((phydev->attached_dev->dev_addr[1] << 8) | 1402 phydev->attached_dev->dev_addr[0])); 1403 if (err < 0) 1404 return err; 1405 1406 /* Clear WOL status and enable magic packet matching */ 1407 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); 1408 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; 1409 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; 1410 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); 1411 if (err < 0) 1412 return err; 1413 } else { 1414 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1415 MII_88E1318S_PHY_WOL_PAGE); 1416 if (err < 0) 1417 return err; 1418 1419 /* Clear WOL status and disable magic packet matching */ 1420 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); 1421 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; 1422 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; 1423 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); 1424 if (err < 0) 1425 return err; 1426 } 1427 1428 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 1429 if (err < 0) 1430 return err; 1431 1432 return 0; 1433 } 1434 1435 static int marvell_get_sset_count(struct phy_device *phydev) 1436 { 1437 if (phydev->supported & SUPPORTED_FIBRE) 1438 return ARRAY_SIZE(marvell_hw_stats); 1439 else 1440 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS; 1441 } 1442 1443 static void marvell_get_strings(struct phy_device *phydev, u8 *data) 1444 { 1445 int i; 1446 1447 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) { 1448 memcpy(data + i * ETH_GSTRING_LEN, 1449 marvell_hw_stats[i].string, ETH_GSTRING_LEN); 1450 } 1451 } 1452 1453 #ifndef UINT64_MAX 1454 #define UINT64_MAX (u64)(~((u64)0)) 1455 #endif 1456 static u64 marvell_get_stat(struct phy_device *phydev, int i) 1457 { 1458 struct marvell_hw_stat stat = marvell_hw_stats[i]; 1459 struct marvell_priv *priv = phydev->priv; 1460 int err, oldpage, val; 1461 u64 ret; 1462 1463 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 1464 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1465 stat.page); 1466 if (err < 0) 1467 return UINT64_MAX; 1468 1469 val = phy_read(phydev, stat.reg); 1470 if (val < 0) { 1471 ret = UINT64_MAX; 1472 } else { 1473 val = val & ((1 << stat.bits) - 1); 1474 priv->stats[i] += val; 1475 ret = priv->stats[i]; 1476 } 1477 1478 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 1479 1480 return ret; 1481 } 1482 1483 static void marvell_get_stats(struct phy_device *phydev, 1484 struct ethtool_stats *stats, u64 *data) 1485 { 1486 int i; 1487 1488 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) 1489 data[i] = marvell_get_stat(phydev, i); 1490 } 1491 1492 #ifdef CONFIG_HWMON 1493 static int m88e1121_get_temp(struct phy_device *phydev, long *temp) 1494 { 1495 int ret; 1496 int val; 1497 1498 *temp = 0; 1499 1500 mutex_lock(&phydev->lock); 1501 1502 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6); 1503 if (ret < 0) 1504 goto error; 1505 1506 /* Enable temperature sensor */ 1507 ret = phy_read(phydev, MII_88E1121_MISC_TEST); 1508 if (ret < 0) 1509 goto error; 1510 1511 ret = phy_write(phydev, MII_88E1121_MISC_TEST, 1512 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN); 1513 if (ret < 0) 1514 goto error; 1515 1516 /* Wait for temperature to stabilize */ 1517 usleep_range(10000, 12000); 1518 1519 val = phy_read(phydev, MII_88E1121_MISC_TEST); 1520 if (val < 0) { 1521 ret = val; 1522 goto error; 1523 } 1524 1525 /* Disable temperature sensor */ 1526 ret = phy_write(phydev, MII_88E1121_MISC_TEST, 1527 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN); 1528 if (ret < 0) 1529 goto error; 1530 1531 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000; 1532 1533 error: 1534 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0); 1535 mutex_unlock(&phydev->lock); 1536 1537 return ret; 1538 } 1539 1540 static int m88e1121_hwmon_read(struct device *dev, 1541 enum hwmon_sensor_types type, 1542 u32 attr, int channel, long *temp) 1543 { 1544 struct phy_device *phydev = dev_get_drvdata(dev); 1545 int err; 1546 1547 switch (attr) { 1548 case hwmon_temp_input: 1549 err = m88e1121_get_temp(phydev, temp); 1550 break; 1551 default: 1552 return -EOPNOTSUPP; 1553 } 1554 1555 return err; 1556 } 1557 1558 static umode_t m88e1121_hwmon_is_visible(const void *data, 1559 enum hwmon_sensor_types type, 1560 u32 attr, int channel) 1561 { 1562 if (type != hwmon_temp) 1563 return 0; 1564 1565 switch (attr) { 1566 case hwmon_temp_input: 1567 return 0444; 1568 default: 1569 return 0; 1570 } 1571 } 1572 1573 static u32 m88e1121_hwmon_chip_config[] = { 1574 HWMON_C_REGISTER_TZ, 1575 0 1576 }; 1577 1578 static const struct hwmon_channel_info m88e1121_hwmon_chip = { 1579 .type = hwmon_chip, 1580 .config = m88e1121_hwmon_chip_config, 1581 }; 1582 1583 static u32 m88e1121_hwmon_temp_config[] = { 1584 HWMON_T_INPUT, 1585 0 1586 }; 1587 1588 static const struct hwmon_channel_info m88e1121_hwmon_temp = { 1589 .type = hwmon_temp, 1590 .config = m88e1121_hwmon_temp_config, 1591 }; 1592 1593 static const struct hwmon_channel_info *m88e1121_hwmon_info[] = { 1594 &m88e1121_hwmon_chip, 1595 &m88e1121_hwmon_temp, 1596 NULL 1597 }; 1598 1599 static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = { 1600 .is_visible = m88e1121_hwmon_is_visible, 1601 .read = m88e1121_hwmon_read, 1602 }; 1603 1604 static const struct hwmon_chip_info m88e1121_hwmon_chip_info = { 1605 .ops = &m88e1121_hwmon_hwmon_ops, 1606 .info = m88e1121_hwmon_info, 1607 }; 1608 1609 static int m88e1510_get_temp(struct phy_device *phydev, long *temp) 1610 { 1611 int ret; 1612 1613 *temp = 0; 1614 1615 mutex_lock(&phydev->lock); 1616 1617 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6); 1618 if (ret < 0) 1619 goto error; 1620 1621 ret = phy_read(phydev, MII_88E1510_TEMP_SENSOR); 1622 if (ret < 0) 1623 goto error; 1624 1625 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000; 1626 1627 error: 1628 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0); 1629 mutex_unlock(&phydev->lock); 1630 1631 return ret; 1632 } 1633 1634 int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp) 1635 { 1636 int ret; 1637 1638 *temp = 0; 1639 1640 mutex_lock(&phydev->lock); 1641 1642 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6); 1643 if (ret < 0) 1644 goto error; 1645 1646 ret = phy_read(phydev, MII_88E1121_MISC_TEST); 1647 if (ret < 0) 1648 goto error; 1649 1650 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >> 1651 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25; 1652 /* convert to mC */ 1653 *temp *= 1000; 1654 1655 error: 1656 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0); 1657 mutex_unlock(&phydev->lock); 1658 1659 return ret; 1660 } 1661 1662 int m88e1510_set_temp_critical(struct phy_device *phydev, long temp) 1663 { 1664 int ret; 1665 1666 mutex_lock(&phydev->lock); 1667 1668 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6); 1669 if (ret < 0) 1670 goto error; 1671 1672 ret = phy_read(phydev, MII_88E1121_MISC_TEST); 1673 if (ret < 0) 1674 goto error; 1675 1676 temp = temp / 1000; 1677 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); 1678 ret = phy_write(phydev, MII_88E1121_MISC_TEST, 1679 (ret & ~MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) | 1680 (temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT)); 1681 1682 error: 1683 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0); 1684 mutex_unlock(&phydev->lock); 1685 1686 return ret; 1687 } 1688 1689 int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm) 1690 { 1691 int ret; 1692 1693 *alarm = false; 1694 1695 mutex_lock(&phydev->lock); 1696 1697 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6); 1698 if (ret < 0) 1699 goto error; 1700 1701 ret = phy_read(phydev, MII_88E1121_MISC_TEST); 1702 if (ret < 0) 1703 goto error; 1704 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ); 1705 1706 error: 1707 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0); 1708 mutex_unlock(&phydev->lock); 1709 1710 return ret; 1711 } 1712 1713 static int m88e1510_hwmon_read(struct device *dev, 1714 enum hwmon_sensor_types type, 1715 u32 attr, int channel, long *temp) 1716 { 1717 struct phy_device *phydev = dev_get_drvdata(dev); 1718 int err; 1719 1720 switch (attr) { 1721 case hwmon_temp_input: 1722 err = m88e1510_get_temp(phydev, temp); 1723 break; 1724 case hwmon_temp_crit: 1725 err = m88e1510_get_temp_critical(phydev, temp); 1726 break; 1727 case hwmon_temp_max_alarm: 1728 err = m88e1510_get_temp_alarm(phydev, temp); 1729 break; 1730 default: 1731 return -EOPNOTSUPP; 1732 } 1733 1734 return err; 1735 } 1736 1737 static int m88e1510_hwmon_write(struct device *dev, 1738 enum hwmon_sensor_types type, 1739 u32 attr, int channel, long temp) 1740 { 1741 struct phy_device *phydev = dev_get_drvdata(dev); 1742 int err; 1743 1744 switch (attr) { 1745 case hwmon_temp_crit: 1746 err = m88e1510_set_temp_critical(phydev, temp); 1747 break; 1748 default: 1749 return -EOPNOTSUPP; 1750 } 1751 return err; 1752 } 1753 1754 static umode_t m88e1510_hwmon_is_visible(const void *data, 1755 enum hwmon_sensor_types type, 1756 u32 attr, int channel) 1757 { 1758 if (type != hwmon_temp) 1759 return 0; 1760 1761 switch (attr) { 1762 case hwmon_temp_input: 1763 case hwmon_temp_max_alarm: 1764 return 0444; 1765 case hwmon_temp_crit: 1766 return 0644; 1767 default: 1768 return 0; 1769 } 1770 } 1771 1772 static u32 m88e1510_hwmon_temp_config[] = { 1773 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM, 1774 0 1775 }; 1776 1777 static const struct hwmon_channel_info m88e1510_hwmon_temp = { 1778 .type = hwmon_temp, 1779 .config = m88e1510_hwmon_temp_config, 1780 }; 1781 1782 static const struct hwmon_channel_info *m88e1510_hwmon_info[] = { 1783 &m88e1121_hwmon_chip, 1784 &m88e1510_hwmon_temp, 1785 NULL 1786 }; 1787 1788 static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = { 1789 .is_visible = m88e1510_hwmon_is_visible, 1790 .read = m88e1510_hwmon_read, 1791 .write = m88e1510_hwmon_write, 1792 }; 1793 1794 static const struct hwmon_chip_info m88e1510_hwmon_chip_info = { 1795 .ops = &m88e1510_hwmon_hwmon_ops, 1796 .info = m88e1510_hwmon_info, 1797 }; 1798 1799 static int marvell_hwmon_name(struct phy_device *phydev) 1800 { 1801 struct marvell_priv *priv = phydev->priv; 1802 struct device *dev = &phydev->mdio.dev; 1803 const char *devname = dev_name(dev); 1804 size_t len = strlen(devname); 1805 int i, j; 1806 1807 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL); 1808 if (!priv->hwmon_name) 1809 return -ENOMEM; 1810 1811 for (i = j = 0; i < len && devname[i]; i++) { 1812 if (isalnum(devname[i])) 1813 priv->hwmon_name[j++] = devname[i]; 1814 } 1815 1816 return 0; 1817 } 1818 1819 static int marvell_hwmon_probe(struct phy_device *phydev, 1820 const struct hwmon_chip_info *chip) 1821 { 1822 struct marvell_priv *priv = phydev->priv; 1823 struct device *dev = &phydev->mdio.dev; 1824 int err; 1825 1826 err = marvell_hwmon_name(phydev); 1827 if (err) 1828 return err; 1829 1830 priv->hwmon_dev = devm_hwmon_device_register_with_info( 1831 dev, priv->hwmon_name, phydev, chip, NULL); 1832 1833 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 1834 } 1835 1836 static int m88e1121_hwmon_probe(struct phy_device *phydev) 1837 { 1838 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info); 1839 } 1840 1841 static int m88e1510_hwmon_probe(struct phy_device *phydev) 1842 { 1843 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info); 1844 } 1845 #else 1846 static int m88e1121_hwmon_probe(struct phy_device *phydev) 1847 { 1848 return 0; 1849 } 1850 1851 static int m88e1510_hwmon_probe(struct phy_device *phydev) 1852 { 1853 return 0; 1854 } 1855 #endif 1856 1857 static int marvell_probe(struct phy_device *phydev) 1858 { 1859 struct marvell_priv *priv; 1860 1861 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1862 if (!priv) 1863 return -ENOMEM; 1864 1865 phydev->priv = priv; 1866 1867 return 0; 1868 } 1869 1870 static int m88e1121_probe(struct phy_device *phydev) 1871 { 1872 int err; 1873 1874 err = marvell_probe(phydev); 1875 if (err) 1876 return err; 1877 1878 return m88e1121_hwmon_probe(phydev); 1879 } 1880 1881 static int m88e1510_probe(struct phy_device *phydev) 1882 { 1883 int err; 1884 1885 err = marvell_probe(phydev); 1886 if (err) 1887 return err; 1888 1889 return m88e1510_hwmon_probe(phydev); 1890 } 1891 1892 static struct phy_driver marvell_drivers[] = { 1893 { 1894 .phy_id = MARVELL_PHY_ID_88E1101, 1895 .phy_id_mask = MARVELL_PHY_ID_MASK, 1896 .name = "Marvell 88E1101", 1897 .features = PHY_GBIT_FEATURES, 1898 .flags = PHY_HAS_INTERRUPT, 1899 .probe = marvell_probe, 1900 .config_init = &marvell_config_init, 1901 .config_aneg = &m88e1101_config_aneg, 1902 .read_status = &genphy_read_status, 1903 .ack_interrupt = &marvell_ack_interrupt, 1904 .config_intr = &marvell_config_intr, 1905 .resume = &genphy_resume, 1906 .suspend = &genphy_suspend, 1907 .get_sset_count = marvell_get_sset_count, 1908 .get_strings = marvell_get_strings, 1909 .get_stats = marvell_get_stats, 1910 }, 1911 { 1912 .phy_id = MARVELL_PHY_ID_88E1112, 1913 .phy_id_mask = MARVELL_PHY_ID_MASK, 1914 .name = "Marvell 88E1112", 1915 .features = PHY_GBIT_FEATURES, 1916 .flags = PHY_HAS_INTERRUPT, 1917 .probe = marvell_probe, 1918 .config_init = &m88e1111_config_init, 1919 .config_aneg = &marvell_config_aneg, 1920 .read_status = &genphy_read_status, 1921 .ack_interrupt = &marvell_ack_interrupt, 1922 .config_intr = &marvell_config_intr, 1923 .resume = &genphy_resume, 1924 .suspend = &genphy_suspend, 1925 .get_sset_count = marvell_get_sset_count, 1926 .get_strings = marvell_get_strings, 1927 .get_stats = marvell_get_stats, 1928 }, 1929 { 1930 .phy_id = MARVELL_PHY_ID_88E1111, 1931 .phy_id_mask = MARVELL_PHY_ID_MASK, 1932 .name = "Marvell 88E1111", 1933 .features = PHY_GBIT_FEATURES, 1934 .flags = PHY_HAS_INTERRUPT, 1935 .probe = marvell_probe, 1936 .config_init = &m88e1111_config_init, 1937 .config_aneg = &m88e1111_config_aneg, 1938 .read_status = &marvell_read_status, 1939 .ack_interrupt = &marvell_ack_interrupt, 1940 .config_intr = &marvell_config_intr, 1941 .resume = &genphy_resume, 1942 .suspend = &genphy_suspend, 1943 .get_sset_count = marvell_get_sset_count, 1944 .get_strings = marvell_get_strings, 1945 .get_stats = marvell_get_stats, 1946 }, 1947 { 1948 .phy_id = MARVELL_PHY_ID_88E1118, 1949 .phy_id_mask = MARVELL_PHY_ID_MASK, 1950 .name = "Marvell 88E1118", 1951 .features = PHY_GBIT_FEATURES, 1952 .flags = PHY_HAS_INTERRUPT, 1953 .probe = marvell_probe, 1954 .config_init = &m88e1118_config_init, 1955 .config_aneg = &m88e1118_config_aneg, 1956 .read_status = &genphy_read_status, 1957 .ack_interrupt = &marvell_ack_interrupt, 1958 .config_intr = &marvell_config_intr, 1959 .resume = &genphy_resume, 1960 .suspend = &genphy_suspend, 1961 .get_sset_count = marvell_get_sset_count, 1962 .get_strings = marvell_get_strings, 1963 .get_stats = marvell_get_stats, 1964 }, 1965 { 1966 .phy_id = MARVELL_PHY_ID_88E1121R, 1967 .phy_id_mask = MARVELL_PHY_ID_MASK, 1968 .name = "Marvell 88E1121R", 1969 .features = PHY_GBIT_FEATURES, 1970 .flags = PHY_HAS_INTERRUPT, 1971 .probe = &m88e1121_probe, 1972 .config_init = &m88e1121_config_init, 1973 .config_aneg = &m88e1121_config_aneg, 1974 .read_status = &marvell_read_status, 1975 .ack_interrupt = &marvell_ack_interrupt, 1976 .config_intr = &marvell_config_intr, 1977 .did_interrupt = &m88e1121_did_interrupt, 1978 .resume = &genphy_resume, 1979 .suspend = &genphy_suspend, 1980 .get_sset_count = marvell_get_sset_count, 1981 .get_strings = marvell_get_strings, 1982 .get_stats = marvell_get_stats, 1983 }, 1984 { 1985 .phy_id = MARVELL_PHY_ID_88E1318S, 1986 .phy_id_mask = MARVELL_PHY_ID_MASK, 1987 .name = "Marvell 88E1318S", 1988 .features = PHY_GBIT_FEATURES, 1989 .flags = PHY_HAS_INTERRUPT, 1990 .probe = marvell_probe, 1991 .config_init = &m88e1121_config_init, 1992 .config_aneg = &m88e1318_config_aneg, 1993 .read_status = &marvell_read_status, 1994 .ack_interrupt = &marvell_ack_interrupt, 1995 .config_intr = &marvell_config_intr, 1996 .did_interrupt = &m88e1121_did_interrupt, 1997 .get_wol = &m88e1318_get_wol, 1998 .set_wol = &m88e1318_set_wol, 1999 .resume = &genphy_resume, 2000 .suspend = &genphy_suspend, 2001 .get_sset_count = marvell_get_sset_count, 2002 .get_strings = marvell_get_strings, 2003 .get_stats = marvell_get_stats, 2004 }, 2005 { 2006 .phy_id = MARVELL_PHY_ID_88E1145, 2007 .phy_id_mask = MARVELL_PHY_ID_MASK, 2008 .name = "Marvell 88E1145", 2009 .features = PHY_GBIT_FEATURES, 2010 .flags = PHY_HAS_INTERRUPT, 2011 .probe = marvell_probe, 2012 .config_init = &m88e1145_config_init, 2013 .config_aneg = &marvell_config_aneg, 2014 .read_status = &genphy_read_status, 2015 .ack_interrupt = &marvell_ack_interrupt, 2016 .config_intr = &marvell_config_intr, 2017 .resume = &genphy_resume, 2018 .suspend = &genphy_suspend, 2019 .get_sset_count = marvell_get_sset_count, 2020 .get_strings = marvell_get_strings, 2021 .get_stats = marvell_get_stats, 2022 }, 2023 { 2024 .phy_id = MARVELL_PHY_ID_88E1149R, 2025 .phy_id_mask = MARVELL_PHY_ID_MASK, 2026 .name = "Marvell 88E1149R", 2027 .features = PHY_GBIT_FEATURES, 2028 .flags = PHY_HAS_INTERRUPT, 2029 .probe = marvell_probe, 2030 .config_init = &m88e1149_config_init, 2031 .config_aneg = &m88e1118_config_aneg, 2032 .read_status = &genphy_read_status, 2033 .ack_interrupt = &marvell_ack_interrupt, 2034 .config_intr = &marvell_config_intr, 2035 .resume = &genphy_resume, 2036 .suspend = &genphy_suspend, 2037 .get_sset_count = marvell_get_sset_count, 2038 .get_strings = marvell_get_strings, 2039 .get_stats = marvell_get_stats, 2040 }, 2041 { 2042 .phy_id = MARVELL_PHY_ID_88E1240, 2043 .phy_id_mask = MARVELL_PHY_ID_MASK, 2044 .name = "Marvell 88E1240", 2045 .features = PHY_GBIT_FEATURES, 2046 .flags = PHY_HAS_INTERRUPT, 2047 .probe = marvell_probe, 2048 .config_init = &m88e1111_config_init, 2049 .config_aneg = &marvell_config_aneg, 2050 .read_status = &genphy_read_status, 2051 .ack_interrupt = &marvell_ack_interrupt, 2052 .config_intr = &marvell_config_intr, 2053 .resume = &genphy_resume, 2054 .suspend = &genphy_suspend, 2055 .get_sset_count = marvell_get_sset_count, 2056 .get_strings = marvell_get_strings, 2057 .get_stats = marvell_get_stats, 2058 }, 2059 { 2060 .phy_id = MARVELL_PHY_ID_88E1116R, 2061 .phy_id_mask = MARVELL_PHY_ID_MASK, 2062 .name = "Marvell 88E1116R", 2063 .features = PHY_GBIT_FEATURES, 2064 .flags = PHY_HAS_INTERRUPT, 2065 .probe = marvell_probe, 2066 .config_init = &m88e1116r_config_init, 2067 .config_aneg = &genphy_config_aneg, 2068 .read_status = &genphy_read_status, 2069 .ack_interrupt = &marvell_ack_interrupt, 2070 .config_intr = &marvell_config_intr, 2071 .resume = &genphy_resume, 2072 .suspend = &genphy_suspend, 2073 .get_sset_count = marvell_get_sset_count, 2074 .get_strings = marvell_get_strings, 2075 .get_stats = marvell_get_stats, 2076 }, 2077 { 2078 .phy_id = MARVELL_PHY_ID_88E1510, 2079 .phy_id_mask = MARVELL_PHY_ID_MASK, 2080 .name = "Marvell 88E1510", 2081 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE, 2082 .flags = PHY_HAS_INTERRUPT, 2083 .probe = &m88e1510_probe, 2084 .config_init = &m88e1510_config_init, 2085 .config_aneg = &m88e1510_config_aneg, 2086 .read_status = &marvell_read_status, 2087 .ack_interrupt = &marvell_ack_interrupt, 2088 .config_intr = &marvell_config_intr, 2089 .did_interrupt = &m88e1121_did_interrupt, 2090 .get_wol = &m88e1318_get_wol, 2091 .set_wol = &m88e1318_set_wol, 2092 .resume = &marvell_resume, 2093 .suspend = &marvell_suspend, 2094 .get_sset_count = marvell_get_sset_count, 2095 .get_strings = marvell_get_strings, 2096 .get_stats = marvell_get_stats, 2097 }, 2098 { 2099 .phy_id = MARVELL_PHY_ID_88E1540, 2100 .phy_id_mask = MARVELL_PHY_ID_MASK, 2101 .name = "Marvell 88E1540", 2102 .features = PHY_GBIT_FEATURES, 2103 .flags = PHY_HAS_INTERRUPT, 2104 .probe = m88e1510_probe, 2105 .config_init = &marvell_config_init, 2106 .config_aneg = &m88e1510_config_aneg, 2107 .read_status = &marvell_read_status, 2108 .ack_interrupt = &marvell_ack_interrupt, 2109 .config_intr = &marvell_config_intr, 2110 .did_interrupt = &m88e1121_did_interrupt, 2111 .resume = &genphy_resume, 2112 .suspend = &genphy_suspend, 2113 .get_sset_count = marvell_get_sset_count, 2114 .get_strings = marvell_get_strings, 2115 .get_stats = marvell_get_stats, 2116 }, 2117 { 2118 .phy_id = MARVELL_PHY_ID_88E1545, 2119 .phy_id_mask = MARVELL_PHY_ID_MASK, 2120 .name = "Marvell 88E1545", 2121 .probe = m88e1510_probe, 2122 .features = PHY_GBIT_FEATURES, 2123 .flags = PHY_HAS_INTERRUPT, 2124 .config_init = &marvell_config_init, 2125 .config_aneg = &m88e1510_config_aneg, 2126 .read_status = &marvell_read_status, 2127 .ack_interrupt = &marvell_ack_interrupt, 2128 .config_intr = &marvell_config_intr, 2129 .did_interrupt = &m88e1121_did_interrupt, 2130 .resume = &genphy_resume, 2131 .suspend = &genphy_suspend, 2132 .get_sset_count = marvell_get_sset_count, 2133 .get_strings = marvell_get_strings, 2134 .get_stats = marvell_get_stats, 2135 }, 2136 { 2137 .phy_id = MARVELL_PHY_ID_88E3016, 2138 .phy_id_mask = MARVELL_PHY_ID_MASK, 2139 .name = "Marvell 88E3016", 2140 .features = PHY_BASIC_FEATURES, 2141 .flags = PHY_HAS_INTERRUPT, 2142 .probe = marvell_probe, 2143 .config_aneg = &genphy_config_aneg, 2144 .config_init = &m88e3016_config_init, 2145 .aneg_done = &marvell_aneg_done, 2146 .read_status = &marvell_read_status, 2147 .ack_interrupt = &marvell_ack_interrupt, 2148 .config_intr = &marvell_config_intr, 2149 .did_interrupt = &m88e1121_did_interrupt, 2150 .resume = &genphy_resume, 2151 .suspend = &genphy_suspend, 2152 .get_sset_count = marvell_get_sset_count, 2153 .get_strings = marvell_get_strings, 2154 .get_stats = marvell_get_stats, 2155 }, 2156 { 2157 .phy_id = MARVELL_PHY_ID_88E6390, 2158 .phy_id_mask = MARVELL_PHY_ID_MASK, 2159 .name = "Marvell 88E6390", 2160 .features = PHY_GBIT_FEATURES, 2161 .flags = PHY_HAS_INTERRUPT, 2162 .probe = m88e1510_probe, 2163 .config_init = &marvell_config_init, 2164 .config_aneg = &m88e1510_config_aneg, 2165 .read_status = &marvell_read_status, 2166 .ack_interrupt = &marvell_ack_interrupt, 2167 .config_intr = &marvell_config_intr, 2168 .did_interrupt = &m88e1121_did_interrupt, 2169 .resume = &genphy_resume, 2170 .suspend = &genphy_suspend, 2171 .get_sset_count = marvell_get_sset_count, 2172 .get_strings = marvell_get_strings, 2173 .get_stats = marvell_get_stats, 2174 }, 2175 }; 2176 2177 module_phy_driver(marvell_drivers); 2178 2179 static struct mdio_device_id __maybe_unused marvell_tbl[] = { 2180 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK }, 2181 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK }, 2182 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK }, 2183 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK }, 2184 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK }, 2185 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK }, 2186 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK }, 2187 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK }, 2188 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK }, 2189 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK }, 2190 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK }, 2191 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK }, 2192 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK }, 2193 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK }, 2194 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK }, 2195 { } 2196 }; 2197 2198 MODULE_DEVICE_TABLE(mdio, marvell_tbl); 2199