1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 3 * Copyright (C) 2019 Texas Instruments Inc. 4 */ 5 6 #include <linux/ethtool.h> 7 #include <linux/etherdevice.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/bitfield.h> 15 16 #include <dt-bindings/net/ti-dp83869.h> 17 18 #define DP83869_PHY_ID 0x2000a0f1 19 #define DP83561_PHY_ID 0x2000a1a4 20 #define DP83869_DEVADDR 0x1f 21 22 #define MII_DP83869_PHYCTRL 0x10 23 #define MII_DP83869_MICR 0x12 24 #define MII_DP83869_ISR 0x13 25 #define DP83869_CFG2 0x14 26 #define DP83869_CTRL 0x1f 27 #define DP83869_CFG4 0x1e 28 29 /* Extended Registers */ 30 #define DP83869_GEN_CFG3 0x0031 31 #define DP83869_RGMIICTL 0x0032 32 #define DP83869_STRAP_STS1 0x006e 33 #define DP83869_RGMIIDCTL 0x0086 34 #define DP83869_RXFCFG 0x0134 35 #define DP83869_RXFPMD1 0x0136 36 #define DP83869_RXFPMD2 0x0137 37 #define DP83869_RXFPMD3 0x0138 38 #define DP83869_RXFSOP1 0x0139 39 #define DP83869_RXFSOP2 0x013A 40 #define DP83869_RXFSOP3 0x013B 41 #define DP83869_IO_MUX_CFG 0x0170 42 #define DP83869_OP_MODE 0x01df 43 #define DP83869_FX_CTRL 0x0c00 44 45 #define DP83869_SW_RESET BIT(15) 46 #define DP83869_SW_RESTART BIT(14) 47 48 /* MICR Interrupt bits */ 49 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 50 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 51 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 52 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 53 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 54 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 55 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 56 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 57 #define MII_DP83869_MICR_WOL_INT_EN BIT(3) 58 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 59 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 60 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 61 62 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 63 BMCR_FULLDPLX | \ 64 BMCR_SPEED1000) 65 66 #define MII_DP83869_FIBER_ADVERTISE (ADVERTISED_FIBRE | \ 67 ADVERTISED_Pause | \ 68 ADVERTISED_Asym_Pause) 69 70 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 71 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 72 73 /* CFG1 bits */ 74 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 75 ADVERTISE_1000FULL | \ 76 CTL1000_AS_MASTER) 77 78 /* RGMIICTL bits */ 79 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 80 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 81 82 /* RGMIIDCTL */ 83 #define DP83869_RGMII_CLK_DELAY_SHIFT 4 84 #define DP83869_CLK_DELAY_DEF 7 85 86 /* STRAP_STS1 bits */ 87 #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 88 #define DP83869_STRAP_STS1_RESERVED BIT(11) 89 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 90 91 /* PHYCTRL bits */ 92 #define DP83869_RX_FIFO_SHIFT 12 93 #define DP83869_TX_FIFO_SHIFT 14 94 95 /* PHY_CTRL lower bytes 0x48 are declared as reserved */ 96 #define DP83869_PHY_CTRL_DEFAULT 0x48 97 #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) 98 #define DP83869_PHYCR_RESERVED_MASK BIT(11) 99 100 /* IO_MUX_CFG bits */ 101 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 102 103 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 104 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 105 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 106 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 107 108 /* CFG3 bits */ 109 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 110 111 /* CFG4 bits */ 112 #define DP83869_INT_OE BIT(7) 113 114 /* OP MODE */ 115 #define DP83869_OP_MODE_MII BIT(5) 116 #define DP83869_SGMII_RGMII_BRIDGE BIT(6) 117 118 /* RXFCFG bits*/ 119 #define DP83869_WOL_MAGIC_EN BIT(0) 120 #define DP83869_WOL_PATTERN_EN BIT(1) 121 #define DP83869_WOL_BCAST_EN BIT(2) 122 #define DP83869_WOL_UCAST_EN BIT(4) 123 #define DP83869_WOL_SEC_EN BIT(5) 124 #define DP83869_WOL_ENH_MAC BIT(7) 125 126 /* CFG2 bits */ 127 #define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9)) 128 #define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 129 #define DP83869_DOWNSHIFT_1_COUNT_VAL 0 130 #define DP83869_DOWNSHIFT_2_COUNT_VAL 1 131 #define DP83869_DOWNSHIFT_4_COUNT_VAL 2 132 #define DP83869_DOWNSHIFT_8_COUNT_VAL 3 133 #define DP83869_DOWNSHIFT_1_COUNT 1 134 #define DP83869_DOWNSHIFT_2_COUNT 2 135 #define DP83869_DOWNSHIFT_4_COUNT 4 136 #define DP83869_DOWNSHIFT_8_COUNT 8 137 138 enum { 139 DP83869_PORT_MIRRORING_KEEP, 140 DP83869_PORT_MIRRORING_EN, 141 DP83869_PORT_MIRRORING_DIS, 142 }; 143 144 struct dp83869_private { 145 int tx_fifo_depth; 146 int rx_fifo_depth; 147 s32 rx_int_delay; 148 s32 tx_int_delay; 149 int io_impedance; 150 int port_mirroring; 151 bool rxctrl_strap_quirk; 152 int clk_output_sel; 153 int mode; 154 }; 155 156 static int dp83869_config_aneg(struct phy_device *phydev) 157 { 158 struct dp83869_private *dp83869 = phydev->priv; 159 160 if (dp83869->mode != DP83869_RGMII_1000_BASE) 161 return genphy_config_aneg(phydev); 162 163 return genphy_c37_config_aneg(phydev); 164 } 165 166 static int dp83869_read_status(struct phy_device *phydev) 167 { 168 struct dp83869_private *dp83869 = phydev->priv; 169 bool changed; 170 int ret; 171 172 if (dp83869->mode == DP83869_RGMII_1000_BASE) 173 return genphy_c37_read_status(phydev, &changed); 174 175 ret = genphy_read_status(phydev); 176 if (ret) 177 return ret; 178 179 if (dp83869->mode == DP83869_RGMII_100_BASE) { 180 if (phydev->link) { 181 phydev->speed = SPEED_100; 182 } else { 183 phydev->speed = SPEED_UNKNOWN; 184 phydev->duplex = DUPLEX_UNKNOWN; 185 } 186 } 187 188 return 0; 189 } 190 191 static int dp83869_ack_interrupt(struct phy_device *phydev) 192 { 193 int err = phy_read(phydev, MII_DP83869_ISR); 194 195 if (err < 0) 196 return err; 197 198 return 0; 199 } 200 201 static int dp83869_config_intr(struct phy_device *phydev) 202 { 203 int micr_status = 0, err; 204 205 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 206 err = dp83869_ack_interrupt(phydev); 207 if (err) 208 return err; 209 210 micr_status = phy_read(phydev, MII_DP83869_MICR); 211 if (micr_status < 0) 212 return micr_status; 213 214 micr_status |= 215 (MII_DP83869_MICR_AN_ERR_INT_EN | 216 MII_DP83869_MICR_SPEED_CHNG_INT_EN | 217 MII_DP83869_MICR_AUTONEG_COMP_INT_EN | 218 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN | 219 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN | 220 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN); 221 222 err = phy_write(phydev, MII_DP83869_MICR, micr_status); 223 } else { 224 err = phy_write(phydev, MII_DP83869_MICR, micr_status); 225 if (err) 226 return err; 227 228 err = dp83869_ack_interrupt(phydev); 229 } 230 231 return err; 232 } 233 234 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev) 235 { 236 int irq_status, irq_enabled; 237 238 irq_status = phy_read(phydev, MII_DP83869_ISR); 239 if (irq_status < 0) { 240 phy_error(phydev); 241 return IRQ_NONE; 242 } 243 244 irq_enabled = phy_read(phydev, MII_DP83869_MICR); 245 if (irq_enabled < 0) { 246 phy_error(phydev); 247 return IRQ_NONE; 248 } 249 250 if (!(irq_status & irq_enabled)) 251 return IRQ_NONE; 252 253 phy_trigger_machine(phydev); 254 255 return IRQ_HANDLED; 256 } 257 258 static int dp83869_set_wol(struct phy_device *phydev, 259 struct ethtool_wolinfo *wol) 260 { 261 struct net_device *ndev = phydev->attached_dev; 262 int val_rxcfg, val_micr; 263 const u8 *mac; 264 int ret; 265 266 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 267 if (val_rxcfg < 0) 268 return val_rxcfg; 269 270 val_micr = phy_read(phydev, MII_DP83869_MICR); 271 if (val_micr < 0) 272 return val_micr; 273 274 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 275 WAKE_BCAST)) { 276 val_rxcfg |= DP83869_WOL_ENH_MAC; 277 val_micr |= MII_DP83869_MICR_WOL_INT_EN; 278 279 if (wol->wolopts & WAKE_MAGIC || 280 wol->wolopts & WAKE_MAGICSECURE) { 281 mac = (const u8 *)ndev->dev_addr; 282 283 if (!is_valid_ether_addr(mac)) 284 return -EINVAL; 285 286 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 287 DP83869_RXFPMD1, 288 mac[1] << 8 | mac[0]); 289 if (ret) 290 return ret; 291 292 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 293 DP83869_RXFPMD2, 294 mac[3] << 8 | mac[2]); 295 if (ret) 296 return ret; 297 298 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 299 DP83869_RXFPMD3, 300 mac[5] << 8 | mac[4]); 301 if (ret) 302 return ret; 303 304 val_rxcfg |= DP83869_WOL_MAGIC_EN; 305 } else { 306 val_rxcfg &= ~DP83869_WOL_MAGIC_EN; 307 } 308 309 if (wol->wolopts & WAKE_MAGICSECURE) { 310 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 311 DP83869_RXFSOP1, 312 (wol->sopass[1] << 8) | wol->sopass[0]); 313 if (ret) 314 return ret; 315 316 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 317 DP83869_RXFSOP2, 318 (wol->sopass[3] << 8) | wol->sopass[2]); 319 if (ret) 320 return ret; 321 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 322 DP83869_RXFSOP3, 323 (wol->sopass[5] << 8) | wol->sopass[4]); 324 if (ret) 325 return ret; 326 327 val_rxcfg |= DP83869_WOL_SEC_EN; 328 } else { 329 val_rxcfg &= ~DP83869_WOL_SEC_EN; 330 } 331 332 if (wol->wolopts & WAKE_UCAST) 333 val_rxcfg |= DP83869_WOL_UCAST_EN; 334 else 335 val_rxcfg &= ~DP83869_WOL_UCAST_EN; 336 337 if (wol->wolopts & WAKE_BCAST) 338 val_rxcfg |= DP83869_WOL_BCAST_EN; 339 else 340 val_rxcfg &= ~DP83869_WOL_BCAST_EN; 341 } else { 342 val_rxcfg &= ~DP83869_WOL_ENH_MAC; 343 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN; 344 } 345 346 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg); 347 if (ret) 348 return ret; 349 350 return phy_write(phydev, MII_DP83869_MICR, val_micr); 351 } 352 353 static void dp83869_get_wol(struct phy_device *phydev, 354 struct ethtool_wolinfo *wol) 355 { 356 int value, sopass_val; 357 358 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 359 WAKE_MAGICSECURE); 360 wol->wolopts = 0; 361 362 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 363 if (value < 0) { 364 phydev_err(phydev, "Failed to read RX CFG\n"); 365 return; 366 } 367 368 if (value & DP83869_WOL_UCAST_EN) 369 wol->wolopts |= WAKE_UCAST; 370 371 if (value & DP83869_WOL_BCAST_EN) 372 wol->wolopts |= WAKE_BCAST; 373 374 if (value & DP83869_WOL_MAGIC_EN) 375 wol->wolopts |= WAKE_MAGIC; 376 377 if (value & DP83869_WOL_SEC_EN) { 378 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 379 DP83869_RXFSOP1); 380 if (sopass_val < 0) { 381 phydev_err(phydev, "Failed to read RX SOP 1\n"); 382 return; 383 } 384 385 wol->sopass[0] = (sopass_val & 0xff); 386 wol->sopass[1] = (sopass_val >> 8); 387 388 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 389 DP83869_RXFSOP2); 390 if (sopass_val < 0) { 391 phydev_err(phydev, "Failed to read RX SOP 2\n"); 392 return; 393 } 394 395 wol->sopass[2] = (sopass_val & 0xff); 396 wol->sopass[3] = (sopass_val >> 8); 397 398 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 399 DP83869_RXFSOP3); 400 if (sopass_val < 0) { 401 phydev_err(phydev, "Failed to read RX SOP 3\n"); 402 return; 403 } 404 405 wol->sopass[4] = (sopass_val & 0xff); 406 wol->sopass[5] = (sopass_val >> 8); 407 408 wol->wolopts |= WAKE_MAGICSECURE; 409 } 410 411 if (!(value & DP83869_WOL_ENH_MAC)) 412 wol->wolopts = 0; 413 } 414 415 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data) 416 { 417 int val, cnt, enable, count; 418 419 val = phy_read(phydev, DP83869_CFG2); 420 if (val < 0) 421 return val; 422 423 enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val); 424 cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val); 425 426 switch (cnt) { 427 case DP83869_DOWNSHIFT_1_COUNT_VAL: 428 count = DP83869_DOWNSHIFT_1_COUNT; 429 break; 430 case DP83869_DOWNSHIFT_2_COUNT_VAL: 431 count = DP83869_DOWNSHIFT_2_COUNT; 432 break; 433 case DP83869_DOWNSHIFT_4_COUNT_VAL: 434 count = DP83869_DOWNSHIFT_4_COUNT; 435 break; 436 case DP83869_DOWNSHIFT_8_COUNT_VAL: 437 count = DP83869_DOWNSHIFT_8_COUNT; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 444 445 return 0; 446 } 447 448 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt) 449 { 450 int val, count; 451 452 if (cnt > DP83869_DOWNSHIFT_8_COUNT) 453 return -EINVAL; 454 455 if (!cnt) 456 return phy_clear_bits(phydev, DP83869_CFG2, 457 DP83869_DOWNSHIFT_EN); 458 459 switch (cnt) { 460 case DP83869_DOWNSHIFT_1_COUNT: 461 count = DP83869_DOWNSHIFT_1_COUNT_VAL; 462 break; 463 case DP83869_DOWNSHIFT_2_COUNT: 464 count = DP83869_DOWNSHIFT_2_COUNT_VAL; 465 break; 466 case DP83869_DOWNSHIFT_4_COUNT: 467 count = DP83869_DOWNSHIFT_4_COUNT_VAL; 468 break; 469 case DP83869_DOWNSHIFT_8_COUNT: 470 count = DP83869_DOWNSHIFT_8_COUNT_VAL; 471 break; 472 default: 473 phydev_err(phydev, 474 "Downshift count must be 1, 2, 4 or 8\n"); 475 return -EINVAL; 476 } 477 478 val = DP83869_DOWNSHIFT_EN; 479 val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count); 480 481 return phy_modify(phydev, DP83869_CFG2, 482 DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK, 483 val); 484 } 485 486 static int dp83869_get_tunable(struct phy_device *phydev, 487 struct ethtool_tunable *tuna, void *data) 488 { 489 switch (tuna->id) { 490 case ETHTOOL_PHY_DOWNSHIFT: 491 return dp83869_get_downshift(phydev, data); 492 default: 493 return -EOPNOTSUPP; 494 } 495 } 496 497 static int dp83869_set_tunable(struct phy_device *phydev, 498 struct ethtool_tunable *tuna, const void *data) 499 { 500 switch (tuna->id) { 501 case ETHTOOL_PHY_DOWNSHIFT: 502 return dp83869_set_downshift(phydev, *(const u8 *)data); 503 default: 504 return -EOPNOTSUPP; 505 } 506 } 507 508 static int dp83869_config_port_mirroring(struct phy_device *phydev) 509 { 510 struct dp83869_private *dp83869 = phydev->priv; 511 512 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 513 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, 514 DP83869_GEN_CFG3, 515 DP83869_CFG3_PORT_MIRROR_EN); 516 else 517 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, 518 DP83869_GEN_CFG3, 519 DP83869_CFG3_PORT_MIRROR_EN); 520 } 521 522 static int dp83869_set_strapped_mode(struct phy_device *phydev) 523 { 524 struct dp83869_private *dp83869 = phydev->priv; 525 int val; 526 527 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 528 if (val < 0) 529 return val; 530 531 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 532 533 return 0; 534 } 535 536 #if IS_ENABLED(CONFIG_OF_MDIO) 537 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 538 1750, 2000, 2250, 2500, 2750, 3000, 539 3250, 3500, 3750, 4000}; 540 541 static int dp83869_of_init(struct phy_device *phydev) 542 { 543 struct dp83869_private *dp83869 = phydev->priv; 544 struct device *dev = &phydev->mdio.dev; 545 struct device_node *of_node = dev->of_node; 546 int delay_size = ARRAY_SIZE(dp83869_internal_delay); 547 int ret; 548 549 if (!of_node) 550 return -ENODEV; 551 552 dp83869->io_impedance = -EINVAL; 553 554 /* Optional configuration */ 555 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 556 &dp83869->clk_output_sel); 557 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK) 558 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 559 560 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode); 561 if (ret == 0) { 562 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 563 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 564 return -EINVAL; 565 } else { 566 ret = dp83869_set_strapped_mode(phydev); 567 if (ret) 568 return ret; 569 } 570 571 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 572 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 573 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 574 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 575 576 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { 577 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 578 } else { 579 /* If the lane swap is not in the DT then check the straps */ 580 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 581 if (ret < 0) 582 return ret; 583 584 if (ret & DP83869_STRAP_MIRROR_ENABLED) 585 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 586 else 587 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 588 589 ret = 0; 590 } 591 592 if (of_property_read_u32(of_node, "rx-fifo-depth", 593 &dp83869->rx_fifo_depth)) 594 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 595 596 if (of_property_read_u32(of_node, "tx-fifo-depth", 597 &dp83869->tx_fifo_depth)) 598 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 599 600 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev, 601 &dp83869_internal_delay[0], 602 delay_size, true); 603 if (dp83869->rx_int_delay < 0) 604 dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; 605 606 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev, 607 &dp83869_internal_delay[0], 608 delay_size, false); 609 if (dp83869->tx_int_delay < 0) 610 dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; 611 612 return ret; 613 } 614 #else 615 static int dp83869_of_init(struct phy_device *phydev) 616 { 617 return dp83869_set_strapped_mode(phydev); 618 } 619 #endif /* CONFIG_OF_MDIO */ 620 621 static int dp83869_configure_rgmii(struct phy_device *phydev, 622 struct dp83869_private *dp83869) 623 { 624 int ret = 0, val; 625 626 if (phy_interface_is_rgmii(phydev)) { 627 val = phy_read(phydev, MII_DP83869_PHYCTRL); 628 if (val < 0) 629 return val; 630 631 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK; 632 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT); 633 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT); 634 635 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); 636 if (ret) 637 return ret; 638 } 639 640 if (dp83869->io_impedance >= 0) 641 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, 642 DP83869_IO_MUX_CFG, 643 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 644 dp83869->io_impedance & 645 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 646 647 return ret; 648 } 649 650 static int dp83869_configure_fiber(struct phy_device *phydev, 651 struct dp83869_private *dp83869) 652 { 653 int bmcr; 654 int ret; 655 656 /* Only allow advertising what this PHY supports */ 657 linkmode_and(phydev->advertising, phydev->advertising, 658 phydev->supported); 659 660 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 661 662 if (dp83869->mode == DP83869_RGMII_1000_BASE) { 663 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 664 phydev->supported); 665 } else { 666 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 667 phydev->supported); 668 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 669 phydev->supported); 670 671 /* Auto neg is not supported in 100base FX mode */ 672 bmcr = phy_read(phydev, MII_BMCR); 673 if (bmcr < 0) 674 return bmcr; 675 676 phydev->autoneg = AUTONEG_DISABLE; 677 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 678 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising); 679 680 if (bmcr & BMCR_ANENABLE) { 681 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 682 if (ret < 0) 683 return ret; 684 } 685 } 686 687 /* Update advertising from supported */ 688 linkmode_or(phydev->advertising, phydev->advertising, 689 phydev->supported); 690 691 return 0; 692 } 693 694 static int dp83869_configure_mode(struct phy_device *phydev, 695 struct dp83869_private *dp83869) 696 { 697 int phy_ctrl_val; 698 int ret; 699 700 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 701 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 702 return -EINVAL; 703 704 /* Below init sequence for each operational mode is defined in 705 * section 9.4.8 of the datasheet. 706 */ 707 phy_ctrl_val = dp83869->mode; 708 if (phydev->interface == PHY_INTERFACE_MODE_MII) { 709 if (dp83869->mode == DP83869_100M_MEDIA_CONVERT || 710 dp83869->mode == DP83869_RGMII_100_BASE || 711 dp83869->mode == DP83869_RGMII_COPPER_ETHERNET) { 712 phy_ctrl_val |= DP83869_OP_MODE_MII; 713 } else { 714 phydev_err(phydev, "selected op-mode is not valid with MII mode\n"); 715 return -EINVAL; 716 } 717 } 718 719 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 720 phy_ctrl_val); 721 if (ret) 722 return ret; 723 724 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 725 if (ret) 726 return ret; 727 728 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT | 729 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT | 730 DP83869_PHY_CTRL_DEFAULT); 731 732 switch (dp83869->mode) { 733 case DP83869_RGMII_COPPER_ETHERNET: 734 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 735 phy_ctrl_val); 736 if (ret) 737 return ret; 738 739 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 740 if (ret) 741 return ret; 742 743 ret = dp83869_configure_rgmii(phydev, dp83869); 744 if (ret) 745 return ret; 746 break; 747 case DP83869_RGMII_SGMII_BRIDGE: 748 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 749 DP83869_SGMII_RGMII_BRIDGE, 750 DP83869_SGMII_RGMII_BRIDGE); 751 if (ret) 752 return ret; 753 754 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 755 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 756 if (ret) 757 return ret; 758 759 break; 760 case DP83869_1000M_MEDIA_CONVERT: 761 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 762 phy_ctrl_val); 763 if (ret) 764 return ret; 765 766 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 767 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 768 if (ret) 769 return ret; 770 break; 771 case DP83869_100M_MEDIA_CONVERT: 772 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 773 phy_ctrl_val); 774 if (ret) 775 return ret; 776 break; 777 case DP83869_SGMII_COPPER_ETHERNET: 778 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 779 phy_ctrl_val); 780 if (ret) 781 return ret; 782 783 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 784 if (ret) 785 return ret; 786 787 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 788 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 789 if (ret) 790 return ret; 791 792 break; 793 case DP83869_RGMII_1000_BASE: 794 case DP83869_RGMII_100_BASE: 795 ret = dp83869_configure_fiber(phydev, dp83869); 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 return ret; 802 } 803 804 static int dp83869_config_init(struct phy_device *phydev) 805 { 806 struct dp83869_private *dp83869 = phydev->priv; 807 int ret, val; 808 809 /* Force speed optimization for the PHY even if it strapped */ 810 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, 811 DP83869_DOWNSHIFT_EN); 812 if (ret) 813 return ret; 814 815 ret = dp83869_configure_mode(phydev, dp83869); 816 if (ret) 817 return ret; 818 819 /* Enable Interrupt output INT_OE in CFG4 register */ 820 if (phy_interrupt_is_valid(phydev)) { 821 val = phy_read(phydev, DP83869_CFG4); 822 val |= DP83869_INT_OE; 823 phy_write(phydev, DP83869_CFG4, val); 824 } 825 826 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 827 dp83869_config_port_mirroring(phydev); 828 829 /* Clock output selection if muxing property is set */ 830 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) 831 ret = phy_modify_mmd(phydev, 832 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 833 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 834 dp83869->clk_output_sel << 835 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 836 837 if (phy_interface_is_rgmii(phydev)) { 838 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, 839 dp83869->rx_int_delay | 840 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT); 841 if (ret) 842 return ret; 843 844 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); 845 val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 846 DP83869_RGMII_RX_CLK_DELAY_EN); 847 848 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 849 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 850 DP83869_RGMII_RX_CLK_DELAY_EN); 851 852 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 853 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; 854 855 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 856 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; 857 858 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, 859 val); 860 } 861 862 return ret; 863 } 864 865 static int dp83869_probe(struct phy_device *phydev) 866 { 867 struct dp83869_private *dp83869; 868 int ret; 869 870 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869), 871 GFP_KERNEL); 872 if (!dp83869) 873 return -ENOMEM; 874 875 phydev->priv = dp83869; 876 877 ret = dp83869_of_init(phydev); 878 if (ret) 879 return ret; 880 881 if (dp83869->mode == DP83869_RGMII_100_BASE || 882 dp83869->mode == DP83869_RGMII_1000_BASE) 883 phydev->port = PORT_FIBRE; 884 885 return dp83869_config_init(phydev); 886 } 887 888 static int dp83869_phy_reset(struct phy_device *phydev) 889 { 890 int ret; 891 892 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET); 893 if (ret < 0) 894 return ret; 895 896 usleep_range(10, 20); 897 898 /* Global sw reset sets all registers to default. 899 * Need to set the registers in the PHY to the right config. 900 */ 901 return dp83869_config_init(phydev); 902 } 903 904 905 #define DP83869_PHY_DRIVER(_id, _name) \ 906 { \ 907 PHY_ID_MATCH_MODEL(_id), \ 908 .name = (_name), \ 909 .probe = dp83869_probe, \ 910 .config_init = dp83869_config_init, \ 911 .soft_reset = dp83869_phy_reset, \ 912 .config_intr = dp83869_config_intr, \ 913 .handle_interrupt = dp83869_handle_interrupt, \ 914 .config_aneg = dp83869_config_aneg, \ 915 .read_status = dp83869_read_status, \ 916 .get_tunable = dp83869_get_tunable, \ 917 .set_tunable = dp83869_set_tunable, \ 918 .get_wol = dp83869_get_wol, \ 919 .set_wol = dp83869_set_wol, \ 920 .suspend = genphy_suspend, \ 921 .resume = genphy_resume, \ 922 } 923 924 static struct phy_driver dp83869_driver[] = { 925 DP83869_PHY_DRIVER(DP83869_PHY_ID, "TI DP83869"), 926 DP83869_PHY_DRIVER(DP83561_PHY_ID, "TI DP83561-SP"), 927 928 }; 929 module_phy_driver(dp83869_driver); 930 931 static struct mdio_device_id __maybe_unused dp83869_tbl[] = { 932 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, 933 { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) }, 934 { } 935 }; 936 MODULE_DEVICE_TABLE(mdio, dp83869_tbl); 937 938 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver"); 939 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 940 MODULE_LICENSE("GPL v2"); 941