1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 3 * Copyright (C) 2019 Texas Instruments Inc. 4 */ 5 6 #include <linux/ethtool.h> 7 #include <linux/etherdevice.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/bitfield.h> 15 16 #include <dt-bindings/net/ti-dp83869.h> 17 18 #define DP83869_PHY_ID 0x2000a0f1 19 #define DP83561_PHY_ID 0x2000a1a4 20 #define DP83869_DEVADDR 0x1f 21 22 #define MII_DP83869_PHYCTRL 0x10 23 #define MII_DP83869_MICR 0x12 24 #define MII_DP83869_ISR 0x13 25 #define DP83869_CFG2 0x14 26 #define DP83869_CTRL 0x1f 27 #define DP83869_CFG4 0x1e 28 29 /* Extended Registers */ 30 #define DP83869_GEN_CFG3 0x0031 31 #define DP83869_RGMIICTL 0x0032 32 #define DP83869_STRAP_STS1 0x006e 33 #define DP83869_RGMIIDCTL 0x0086 34 #define DP83869_RXFCFG 0x0134 35 #define DP83869_RXFPMD1 0x0136 36 #define DP83869_RXFPMD2 0x0137 37 #define DP83869_RXFPMD3 0x0138 38 #define DP83869_RXFSOP1 0x0139 39 #define DP83869_RXFSOP2 0x013A 40 #define DP83869_RXFSOP3 0x013B 41 #define DP83869_IO_MUX_CFG 0x0170 42 #define DP83869_OP_MODE 0x01df 43 #define DP83869_FX_CTRL 0x0c00 44 45 #define DP83869_SW_RESET BIT(15) 46 #define DP83869_SW_RESTART BIT(14) 47 48 /* MICR Interrupt bits */ 49 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 50 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 51 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 52 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 53 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 54 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 55 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 56 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 57 #define MII_DP83869_MICR_WOL_INT_EN BIT(3) 58 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 59 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 60 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 61 62 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 63 BMCR_FULLDPLX | \ 64 BMCR_SPEED1000) 65 66 #define MII_DP83869_FIBER_ADVERTISE (ADVERTISED_FIBRE | \ 67 ADVERTISED_Pause | \ 68 ADVERTISED_Asym_Pause) 69 70 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 71 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 72 73 /* CFG1 bits */ 74 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 75 ADVERTISE_1000FULL | \ 76 CTL1000_AS_MASTER) 77 78 /* RGMIICTL bits */ 79 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 80 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 81 82 /* RGMIIDCTL */ 83 #define DP83869_RGMII_CLK_DELAY_SHIFT 4 84 #define DP83869_CLK_DELAY_DEF 7 85 86 /* STRAP_STS1 bits */ 87 #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 88 #define DP83869_STRAP_STS1_RESERVED BIT(11) 89 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 90 91 /* PHYCTRL bits */ 92 #define DP83869_RX_FIFO_SHIFT 12 93 #define DP83869_TX_FIFO_SHIFT 14 94 95 /* PHY_CTRL lower bytes 0x48 are declared as reserved */ 96 #define DP83869_PHY_CTRL_DEFAULT 0x48 97 #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) 98 #define DP83869_PHYCR_RESERVED_MASK BIT(11) 99 100 /* IO_MUX_CFG bits */ 101 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 102 103 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 104 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 105 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 106 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 107 108 /* CFG3 bits */ 109 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 110 111 /* CFG4 bits */ 112 #define DP83869_INT_OE BIT(7) 113 114 /* OP MODE */ 115 #define DP83869_OP_MODE_MII BIT(5) 116 #define DP83869_SGMII_RGMII_BRIDGE BIT(6) 117 118 /* RXFCFG bits*/ 119 #define DP83869_WOL_MAGIC_EN BIT(0) 120 #define DP83869_WOL_PATTERN_EN BIT(1) 121 #define DP83869_WOL_BCAST_EN BIT(2) 122 #define DP83869_WOL_UCAST_EN BIT(4) 123 #define DP83869_WOL_SEC_EN BIT(5) 124 #define DP83869_WOL_ENH_MAC BIT(7) 125 126 /* CFG2 bits */ 127 #define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9)) 128 #define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 129 #define DP83869_DOWNSHIFT_1_COUNT_VAL 0 130 #define DP83869_DOWNSHIFT_2_COUNT_VAL 1 131 #define DP83869_DOWNSHIFT_4_COUNT_VAL 2 132 #define DP83869_DOWNSHIFT_8_COUNT_VAL 3 133 #define DP83869_DOWNSHIFT_1_COUNT 1 134 #define DP83869_DOWNSHIFT_2_COUNT 2 135 #define DP83869_DOWNSHIFT_4_COUNT 4 136 #define DP83869_DOWNSHIFT_8_COUNT 8 137 138 enum { 139 DP83869_PORT_MIRRORING_KEEP, 140 DP83869_PORT_MIRRORING_EN, 141 DP83869_PORT_MIRRORING_DIS, 142 }; 143 144 struct dp83869_private { 145 int tx_fifo_depth; 146 int rx_fifo_depth; 147 s32 rx_int_delay; 148 s32 tx_int_delay; 149 int io_impedance; 150 int port_mirroring; 151 bool rxctrl_strap_quirk; 152 int clk_output_sel; 153 int mode; 154 }; 155 156 static int dp83869_config_aneg(struct phy_device *phydev) 157 { 158 struct dp83869_private *dp83869 = phydev->priv; 159 160 if (dp83869->mode != DP83869_RGMII_1000_BASE) 161 return genphy_config_aneg(phydev); 162 163 return genphy_c37_config_aneg(phydev); 164 } 165 166 static int dp83869_read_status(struct phy_device *phydev) 167 { 168 struct dp83869_private *dp83869 = phydev->priv; 169 bool changed; 170 int ret; 171 172 if (dp83869->mode == DP83869_RGMII_1000_BASE) 173 return genphy_c37_read_status(phydev, &changed); 174 175 ret = genphy_read_status(phydev); 176 if (ret) 177 return ret; 178 179 if (dp83869->mode == DP83869_RGMII_100_BASE) { 180 if (phydev->link) { 181 phydev->speed = SPEED_100; 182 } else { 183 phydev->speed = SPEED_UNKNOWN; 184 phydev->duplex = DUPLEX_UNKNOWN; 185 } 186 } 187 188 return 0; 189 } 190 191 static int dp83869_ack_interrupt(struct phy_device *phydev) 192 { 193 int err = phy_read(phydev, MII_DP83869_ISR); 194 195 if (err < 0) 196 return err; 197 198 return 0; 199 } 200 201 static int dp83869_config_intr(struct phy_device *phydev) 202 { 203 int micr_status = 0, err; 204 205 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 206 err = dp83869_ack_interrupt(phydev); 207 if (err) 208 return err; 209 210 micr_status = phy_read(phydev, MII_DP83869_MICR); 211 if (micr_status < 0) 212 return micr_status; 213 214 micr_status |= 215 (MII_DP83869_MICR_AN_ERR_INT_EN | 216 MII_DP83869_MICR_SPEED_CHNG_INT_EN | 217 MII_DP83869_MICR_AUTONEG_COMP_INT_EN | 218 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN | 219 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN | 220 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN); 221 222 err = phy_write(phydev, MII_DP83869_MICR, micr_status); 223 } else { 224 err = phy_write(phydev, MII_DP83869_MICR, micr_status); 225 if (err) 226 return err; 227 228 err = dp83869_ack_interrupt(phydev); 229 } 230 231 return err; 232 } 233 234 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev) 235 { 236 int irq_status, irq_enabled; 237 238 irq_status = phy_read(phydev, MII_DP83869_ISR); 239 if (irq_status < 0) { 240 phy_error(phydev); 241 return IRQ_NONE; 242 } 243 244 irq_enabled = phy_read(phydev, MII_DP83869_MICR); 245 if (irq_enabled < 0) { 246 phy_error(phydev); 247 return IRQ_NONE; 248 } 249 250 if (!(irq_status & irq_enabled)) 251 return IRQ_NONE; 252 253 phy_trigger_machine(phydev); 254 255 return IRQ_HANDLED; 256 } 257 258 static int dp83869_set_wol(struct phy_device *phydev, 259 struct ethtool_wolinfo *wol) 260 { 261 struct net_device *ndev = phydev->attached_dev; 262 int val_rxcfg, val_micr; 263 const u8 *mac; 264 int ret; 265 266 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 267 if (val_rxcfg < 0) 268 return val_rxcfg; 269 270 val_micr = phy_read(phydev, MII_DP83869_MICR); 271 if (val_micr < 0) 272 return val_micr; 273 274 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 275 WAKE_BCAST)) { 276 val_rxcfg |= DP83869_WOL_ENH_MAC; 277 val_micr |= MII_DP83869_MICR_WOL_INT_EN; 278 279 if (wol->wolopts & WAKE_MAGIC || 280 wol->wolopts & WAKE_MAGICSECURE) { 281 mac = (const u8 *)ndev->dev_addr; 282 283 if (!is_valid_ether_addr(mac)) 284 return -EINVAL; 285 286 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 287 DP83869_RXFPMD1, 288 mac[1] << 8 | mac[0]); 289 if (ret) 290 return ret; 291 292 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 293 DP83869_RXFPMD2, 294 mac[3] << 8 | mac[2]); 295 if (ret) 296 return ret; 297 298 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 299 DP83869_RXFPMD3, 300 mac[5] << 8 | mac[4]); 301 if (ret) 302 return ret; 303 304 val_rxcfg |= DP83869_WOL_MAGIC_EN; 305 } else { 306 val_rxcfg &= ~DP83869_WOL_MAGIC_EN; 307 } 308 309 if (wol->wolopts & WAKE_MAGICSECURE) { 310 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 311 DP83869_RXFSOP1, 312 (wol->sopass[1] << 8) | wol->sopass[0]); 313 if (ret) 314 return ret; 315 316 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 317 DP83869_RXFSOP2, 318 (wol->sopass[3] << 8) | wol->sopass[2]); 319 if (ret) 320 return ret; 321 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 322 DP83869_RXFSOP3, 323 (wol->sopass[5] << 8) | wol->sopass[4]); 324 if (ret) 325 return ret; 326 327 val_rxcfg |= DP83869_WOL_SEC_EN; 328 } else { 329 val_rxcfg &= ~DP83869_WOL_SEC_EN; 330 } 331 332 if (wol->wolopts & WAKE_UCAST) 333 val_rxcfg |= DP83869_WOL_UCAST_EN; 334 else 335 val_rxcfg &= ~DP83869_WOL_UCAST_EN; 336 337 if (wol->wolopts & WAKE_BCAST) 338 val_rxcfg |= DP83869_WOL_BCAST_EN; 339 else 340 val_rxcfg &= ~DP83869_WOL_BCAST_EN; 341 } else { 342 val_rxcfg &= ~DP83869_WOL_ENH_MAC; 343 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN; 344 } 345 346 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg); 347 if (ret) 348 return ret; 349 350 return phy_write(phydev, MII_DP83869_MICR, val_micr); 351 } 352 353 static void dp83869_get_wol(struct phy_device *phydev, 354 struct ethtool_wolinfo *wol) 355 { 356 int value, sopass_val; 357 358 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 359 WAKE_MAGICSECURE); 360 wol->wolopts = 0; 361 362 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 363 if (value < 0) { 364 phydev_err(phydev, "Failed to read RX CFG\n"); 365 return; 366 } 367 368 if (value & DP83869_WOL_UCAST_EN) 369 wol->wolopts |= WAKE_UCAST; 370 371 if (value & DP83869_WOL_BCAST_EN) 372 wol->wolopts |= WAKE_BCAST; 373 374 if (value & DP83869_WOL_MAGIC_EN) 375 wol->wolopts |= WAKE_MAGIC; 376 377 if (value & DP83869_WOL_SEC_EN) { 378 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 379 DP83869_RXFSOP1); 380 if (sopass_val < 0) { 381 phydev_err(phydev, "Failed to read RX SOP 1\n"); 382 return; 383 } 384 385 wol->sopass[0] = (sopass_val & 0xff); 386 wol->sopass[1] = (sopass_val >> 8); 387 388 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 389 DP83869_RXFSOP2); 390 if (sopass_val < 0) { 391 phydev_err(phydev, "Failed to read RX SOP 2\n"); 392 return; 393 } 394 395 wol->sopass[2] = (sopass_val & 0xff); 396 wol->sopass[3] = (sopass_val >> 8); 397 398 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 399 DP83869_RXFSOP3); 400 if (sopass_val < 0) { 401 phydev_err(phydev, "Failed to read RX SOP 3\n"); 402 return; 403 } 404 405 wol->sopass[4] = (sopass_val & 0xff); 406 wol->sopass[5] = (sopass_val >> 8); 407 408 wol->wolopts |= WAKE_MAGICSECURE; 409 } 410 411 if (!(value & DP83869_WOL_ENH_MAC)) 412 wol->wolopts = 0; 413 } 414 415 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data) 416 { 417 int val, cnt, enable, count; 418 419 val = phy_read(phydev, DP83869_CFG2); 420 if (val < 0) 421 return val; 422 423 enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val); 424 cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val); 425 426 switch (cnt) { 427 case DP83869_DOWNSHIFT_1_COUNT_VAL: 428 count = DP83869_DOWNSHIFT_1_COUNT; 429 break; 430 case DP83869_DOWNSHIFT_2_COUNT_VAL: 431 count = DP83869_DOWNSHIFT_2_COUNT; 432 break; 433 case DP83869_DOWNSHIFT_4_COUNT_VAL: 434 count = DP83869_DOWNSHIFT_4_COUNT; 435 break; 436 case DP83869_DOWNSHIFT_8_COUNT_VAL: 437 count = DP83869_DOWNSHIFT_8_COUNT; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 444 445 return 0; 446 } 447 448 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt) 449 { 450 int val, count; 451 452 if (cnt > DP83869_DOWNSHIFT_8_COUNT) 453 return -EINVAL; 454 455 if (!cnt) 456 return phy_clear_bits(phydev, DP83869_CFG2, 457 DP83869_DOWNSHIFT_EN); 458 459 switch (cnt) { 460 case DP83869_DOWNSHIFT_1_COUNT: 461 count = DP83869_DOWNSHIFT_1_COUNT_VAL; 462 break; 463 case DP83869_DOWNSHIFT_2_COUNT: 464 count = DP83869_DOWNSHIFT_2_COUNT_VAL; 465 break; 466 case DP83869_DOWNSHIFT_4_COUNT: 467 count = DP83869_DOWNSHIFT_4_COUNT_VAL; 468 break; 469 case DP83869_DOWNSHIFT_8_COUNT: 470 count = DP83869_DOWNSHIFT_8_COUNT_VAL; 471 break; 472 default: 473 phydev_err(phydev, 474 "Downshift count must be 1, 2, 4 or 8\n"); 475 return -EINVAL; 476 } 477 478 val = DP83869_DOWNSHIFT_EN; 479 val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count); 480 481 return phy_modify(phydev, DP83869_CFG2, 482 DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK, 483 val); 484 } 485 486 static int dp83869_get_tunable(struct phy_device *phydev, 487 struct ethtool_tunable *tuna, void *data) 488 { 489 switch (tuna->id) { 490 case ETHTOOL_PHY_DOWNSHIFT: 491 return dp83869_get_downshift(phydev, data); 492 default: 493 return -EOPNOTSUPP; 494 } 495 } 496 497 static int dp83869_set_tunable(struct phy_device *phydev, 498 struct ethtool_tunable *tuna, const void *data) 499 { 500 switch (tuna->id) { 501 case ETHTOOL_PHY_DOWNSHIFT: 502 return dp83869_set_downshift(phydev, *(const u8 *)data); 503 default: 504 return -EOPNOTSUPP; 505 } 506 } 507 508 static int dp83869_config_port_mirroring(struct phy_device *phydev) 509 { 510 struct dp83869_private *dp83869 = phydev->priv; 511 512 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 513 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, 514 DP83869_GEN_CFG3, 515 DP83869_CFG3_PORT_MIRROR_EN); 516 else 517 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, 518 DP83869_GEN_CFG3, 519 DP83869_CFG3_PORT_MIRROR_EN); 520 } 521 522 static int dp83869_set_strapped_mode(struct phy_device *phydev) 523 { 524 struct dp83869_private *dp83869 = phydev->priv; 525 int val; 526 527 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 528 if (val < 0) 529 return val; 530 531 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 532 533 return 0; 534 } 535 536 #if IS_ENABLED(CONFIG_OF_MDIO) 537 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 538 1750, 2000, 2250, 2500, 2750, 3000, 539 3250, 3500, 3750, 4000}; 540 541 static int dp83869_of_init(struct phy_device *phydev) 542 { 543 struct device_node *of_node = phydev->mdio.dev.of_node; 544 struct dp83869_private *dp83869 = phydev->priv; 545 int delay_size = ARRAY_SIZE(dp83869_internal_delay); 546 int ret; 547 548 if (!of_node) 549 return -ENODEV; 550 551 dp83869->io_impedance = -EINVAL; 552 553 /* Optional configuration */ 554 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 555 &dp83869->clk_output_sel); 556 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK) 557 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 558 559 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode); 560 if (ret == 0) { 561 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 562 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 563 return -EINVAL; 564 } else { 565 ret = dp83869_set_strapped_mode(phydev); 566 if (ret) 567 return ret; 568 } 569 570 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 571 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 572 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 573 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 574 575 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { 576 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 577 } else { 578 /* If the lane swap is not in the DT then check the straps */ 579 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 580 if (ret < 0) 581 return ret; 582 583 if (ret & DP83869_STRAP_MIRROR_ENABLED) 584 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 585 else 586 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 587 588 ret = 0; 589 } 590 591 if (of_property_read_u32(of_node, "rx-fifo-depth", 592 &dp83869->rx_fifo_depth)) 593 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 594 595 if (of_property_read_u32(of_node, "tx-fifo-depth", 596 &dp83869->tx_fifo_depth)) 597 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 598 599 dp83869->rx_int_delay = phy_get_internal_delay(phydev, 600 &dp83869_internal_delay[0], 601 delay_size, true); 602 if (dp83869->rx_int_delay < 0) 603 dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; 604 605 dp83869->tx_int_delay = phy_get_internal_delay(phydev, 606 &dp83869_internal_delay[0], 607 delay_size, false); 608 if (dp83869->tx_int_delay < 0) 609 dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; 610 611 return ret; 612 } 613 #else 614 static int dp83869_of_init(struct phy_device *phydev) 615 { 616 return dp83869_set_strapped_mode(phydev); 617 } 618 #endif /* CONFIG_OF_MDIO */ 619 620 static int dp83869_configure_rgmii(struct phy_device *phydev, 621 struct dp83869_private *dp83869) 622 { 623 int ret = 0, val; 624 625 if (phy_interface_is_rgmii(phydev)) { 626 val = phy_read(phydev, MII_DP83869_PHYCTRL); 627 if (val < 0) 628 return val; 629 630 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK; 631 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT); 632 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT); 633 634 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); 635 if (ret) 636 return ret; 637 } 638 639 if (dp83869->io_impedance >= 0) 640 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, 641 DP83869_IO_MUX_CFG, 642 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 643 dp83869->io_impedance & 644 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 645 646 return ret; 647 } 648 649 static int dp83869_configure_fiber(struct phy_device *phydev, 650 struct dp83869_private *dp83869) 651 { 652 int bmcr; 653 int ret; 654 655 /* Only allow advertising what this PHY supports */ 656 linkmode_and(phydev->advertising, phydev->advertising, 657 phydev->supported); 658 659 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 660 661 if (dp83869->mode == DP83869_RGMII_1000_BASE) { 662 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 663 phydev->supported); 664 } else { 665 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 666 phydev->supported); 667 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 668 phydev->supported); 669 670 /* Auto neg is not supported in 100base FX mode */ 671 bmcr = phy_read(phydev, MII_BMCR); 672 if (bmcr < 0) 673 return bmcr; 674 675 phydev->autoneg = AUTONEG_DISABLE; 676 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 677 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising); 678 679 if (bmcr & BMCR_ANENABLE) { 680 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 681 if (ret < 0) 682 return ret; 683 } 684 } 685 686 /* Update advertising from supported */ 687 linkmode_or(phydev->advertising, phydev->advertising, 688 phydev->supported); 689 690 return 0; 691 } 692 693 static int dp83869_configure_mode(struct phy_device *phydev, 694 struct dp83869_private *dp83869) 695 { 696 int phy_ctrl_val; 697 int ret; 698 699 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 700 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 701 return -EINVAL; 702 703 /* Below init sequence for each operational mode is defined in 704 * section 9.4.8 of the datasheet. 705 */ 706 phy_ctrl_val = dp83869->mode; 707 if (phydev->interface == PHY_INTERFACE_MODE_MII) { 708 if (dp83869->mode == DP83869_100M_MEDIA_CONVERT || 709 dp83869->mode == DP83869_RGMII_100_BASE || 710 dp83869->mode == DP83869_RGMII_COPPER_ETHERNET) { 711 phy_ctrl_val |= DP83869_OP_MODE_MII; 712 } else { 713 phydev_err(phydev, "selected op-mode is not valid with MII mode\n"); 714 return -EINVAL; 715 } 716 } 717 718 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 719 phy_ctrl_val); 720 if (ret) 721 return ret; 722 723 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 724 if (ret) 725 return ret; 726 727 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT | 728 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT | 729 DP83869_PHY_CTRL_DEFAULT); 730 731 switch (dp83869->mode) { 732 case DP83869_RGMII_COPPER_ETHERNET: 733 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 734 phy_ctrl_val); 735 if (ret) 736 return ret; 737 738 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 739 if (ret) 740 return ret; 741 742 ret = dp83869_configure_rgmii(phydev, dp83869); 743 if (ret) 744 return ret; 745 break; 746 case DP83869_RGMII_SGMII_BRIDGE: 747 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 748 DP83869_SGMII_RGMII_BRIDGE, 749 DP83869_SGMII_RGMII_BRIDGE); 750 if (ret) 751 return ret; 752 753 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 754 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 755 if (ret) 756 return ret; 757 758 break; 759 case DP83869_1000M_MEDIA_CONVERT: 760 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 761 phy_ctrl_val); 762 if (ret) 763 return ret; 764 765 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 766 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 767 if (ret) 768 return ret; 769 break; 770 case DP83869_100M_MEDIA_CONVERT: 771 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 772 phy_ctrl_val); 773 if (ret) 774 return ret; 775 break; 776 case DP83869_SGMII_COPPER_ETHERNET: 777 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 778 phy_ctrl_val); 779 if (ret) 780 return ret; 781 782 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 783 if (ret) 784 return ret; 785 786 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 787 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 788 if (ret) 789 return ret; 790 791 break; 792 case DP83869_RGMII_1000_BASE: 793 case DP83869_RGMII_100_BASE: 794 ret = dp83869_configure_fiber(phydev, dp83869); 795 break; 796 default: 797 return -EINVAL; 798 } 799 800 return ret; 801 } 802 803 static int dp83869_config_init(struct phy_device *phydev) 804 { 805 struct dp83869_private *dp83869 = phydev->priv; 806 int ret, val; 807 808 /* Force speed optimization for the PHY even if it strapped */ 809 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, 810 DP83869_DOWNSHIFT_EN); 811 if (ret) 812 return ret; 813 814 ret = dp83869_configure_mode(phydev, dp83869); 815 if (ret) 816 return ret; 817 818 /* Enable Interrupt output INT_OE in CFG4 register */ 819 if (phy_interrupt_is_valid(phydev)) { 820 val = phy_read(phydev, DP83869_CFG4); 821 val |= DP83869_INT_OE; 822 phy_write(phydev, DP83869_CFG4, val); 823 } 824 825 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 826 dp83869_config_port_mirroring(phydev); 827 828 /* Clock output selection if muxing property is set */ 829 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) 830 ret = phy_modify_mmd(phydev, 831 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 832 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 833 dp83869->clk_output_sel << 834 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 835 836 if (phy_interface_is_rgmii(phydev)) { 837 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, 838 dp83869->rx_int_delay | 839 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT); 840 if (ret) 841 return ret; 842 843 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); 844 val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 845 DP83869_RGMII_RX_CLK_DELAY_EN); 846 847 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 848 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 849 DP83869_RGMII_RX_CLK_DELAY_EN); 850 851 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 852 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; 853 854 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 855 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; 856 857 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, 858 val); 859 } 860 861 return ret; 862 } 863 864 static int dp83869_probe(struct phy_device *phydev) 865 { 866 struct dp83869_private *dp83869; 867 int ret; 868 869 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869), 870 GFP_KERNEL); 871 if (!dp83869) 872 return -ENOMEM; 873 874 phydev->priv = dp83869; 875 876 ret = dp83869_of_init(phydev); 877 if (ret) 878 return ret; 879 880 if (dp83869->mode == DP83869_RGMII_100_BASE || 881 dp83869->mode == DP83869_RGMII_1000_BASE) 882 phydev->port = PORT_FIBRE; 883 884 return dp83869_config_init(phydev); 885 } 886 887 static int dp83869_phy_reset(struct phy_device *phydev) 888 { 889 int ret; 890 891 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET); 892 if (ret < 0) 893 return ret; 894 895 usleep_range(10, 20); 896 897 /* Global sw reset sets all registers to default. 898 * Need to set the registers in the PHY to the right config. 899 */ 900 return dp83869_config_init(phydev); 901 } 902 903 904 #define DP83869_PHY_DRIVER(_id, _name) \ 905 { \ 906 PHY_ID_MATCH_MODEL(_id), \ 907 .name = (_name), \ 908 .probe = dp83869_probe, \ 909 .config_init = dp83869_config_init, \ 910 .soft_reset = dp83869_phy_reset, \ 911 .config_intr = dp83869_config_intr, \ 912 .handle_interrupt = dp83869_handle_interrupt, \ 913 .config_aneg = dp83869_config_aneg, \ 914 .read_status = dp83869_read_status, \ 915 .get_tunable = dp83869_get_tunable, \ 916 .set_tunable = dp83869_set_tunable, \ 917 .get_wol = dp83869_get_wol, \ 918 .set_wol = dp83869_set_wol, \ 919 .suspend = genphy_suspend, \ 920 .resume = genphy_resume, \ 921 } 922 923 static struct phy_driver dp83869_driver[] = { 924 DP83869_PHY_DRIVER(DP83869_PHY_ID, "TI DP83869"), 925 DP83869_PHY_DRIVER(DP83561_PHY_ID, "TI DP83561-SP"), 926 927 }; 928 module_phy_driver(dp83869_driver); 929 930 static const struct mdio_device_id __maybe_unused dp83869_tbl[] = { 931 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, 932 { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) }, 933 { } 934 }; 935 MODULE_DEVICE_TABLE(mdio, dp83869_tbl); 936 937 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver"); 938 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 939 MODULE_LICENSE("GPL v2"); 940