1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DP83867 PHY 4 * 5 * Copyright (C) 2015 Texas Instruments Inc. 6 */ 7 8 #include <linux/ethtool.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 15 #include <dt-bindings/net/ti-dp83867.h> 16 17 #define DP83867_PHY_ID 0x2000a231 18 #define DP83867_DEVADDR 0x1f 19 20 #define MII_DP83867_PHYCTRL 0x10 21 #define MII_DP83867_MICR 0x12 22 #define MII_DP83867_ISR 0x13 23 #define DP83867_CTRL 0x1f 24 #define DP83867_CFG3 0x1e 25 26 /* Extended Registers */ 27 #define DP83867_CFG4 0x0031 28 #define DP83867_RGMIICTL 0x0032 29 #define DP83867_STRAP_STS1 0x006E 30 #define DP83867_RGMIIDCTL 0x0086 31 #define DP83867_IO_MUX_CFG 0x0170 32 33 #define DP83867_SW_RESET BIT(15) 34 #define DP83867_SW_RESTART BIT(14) 35 36 /* MICR Interrupt bits */ 37 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 38 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 39 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 40 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 41 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 42 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 43 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 44 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 45 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 46 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 47 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 48 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 49 50 /* RGMIICTL bits */ 51 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 52 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 53 54 /* STRAP_STS1 bits */ 55 #define DP83867_STRAP_STS1_RESERVED BIT(11) 56 57 /* PHY CTRL bits */ 58 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 59 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) 60 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 61 62 /* RGMIIDCTL bits */ 63 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 64 65 /* IO_MUX_CFG bits */ 66 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 67 68 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 69 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 70 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 71 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 72 73 /* CFG4 bits */ 74 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 75 76 enum { 77 DP83867_PORT_MIRROING_KEEP, 78 DP83867_PORT_MIRROING_EN, 79 DP83867_PORT_MIRROING_DIS, 80 }; 81 82 struct dp83867_private { 83 int rx_id_delay; 84 int tx_id_delay; 85 int fifo_depth; 86 int io_impedance; 87 int port_mirroring; 88 bool rxctrl_strap_quirk; 89 int clk_output_sel; 90 }; 91 92 static int dp83867_ack_interrupt(struct phy_device *phydev) 93 { 94 int err = phy_read(phydev, MII_DP83867_ISR); 95 96 if (err < 0) 97 return err; 98 99 return 0; 100 } 101 102 static int dp83867_config_intr(struct phy_device *phydev) 103 { 104 int micr_status; 105 106 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 107 micr_status = phy_read(phydev, MII_DP83867_MICR); 108 if (micr_status < 0) 109 return micr_status; 110 111 micr_status |= 112 (MII_DP83867_MICR_AN_ERR_INT_EN | 113 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 114 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 115 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 116 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 117 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 118 119 return phy_write(phydev, MII_DP83867_MICR, micr_status); 120 } 121 122 micr_status = 0x0; 123 return phy_write(phydev, MII_DP83867_MICR, micr_status); 124 } 125 126 static int dp83867_config_port_mirroring(struct phy_device *phydev) 127 { 128 struct dp83867_private *dp83867 = 129 (struct dp83867_private *)phydev->priv; 130 131 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 132 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 133 DP83867_CFG4_PORT_MIRROR_EN); 134 else 135 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 136 DP83867_CFG4_PORT_MIRROR_EN); 137 return 0; 138 } 139 140 #ifdef CONFIG_OF_MDIO 141 static int dp83867_of_init(struct phy_device *phydev) 142 { 143 struct dp83867_private *dp83867 = phydev->priv; 144 struct device *dev = &phydev->mdio.dev; 145 struct device_node *of_node = dev->of_node; 146 int ret; 147 148 if (!of_node) 149 return -ENODEV; 150 151 dp83867->io_impedance = -EINVAL; 152 153 /* Optional configuration */ 154 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 155 &dp83867->clk_output_sel); 156 if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK) 157 /* Keep the default value if ti,clk-output-sel is not set 158 * or too high 159 */ 160 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK; 161 162 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 163 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 164 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 165 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 166 167 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 168 "ti,dp83867-rxctrl-strap-quirk"); 169 170 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 171 &dp83867->rx_id_delay); 172 if (ret && 173 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 174 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) 175 return ret; 176 177 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 178 &dp83867->tx_id_delay); 179 if (ret && 180 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 181 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) 182 return ret; 183 184 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 185 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 186 187 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 188 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 189 190 return of_property_read_u32(of_node, "ti,fifo-depth", 191 &dp83867->fifo_depth); 192 } 193 #else 194 static int dp83867_of_init(struct phy_device *phydev) 195 { 196 return 0; 197 } 198 #endif /* CONFIG_OF_MDIO */ 199 200 static int dp83867_config_init(struct phy_device *phydev) 201 { 202 struct dp83867_private *dp83867; 203 int ret, val, bs; 204 u16 delay; 205 206 if (!phydev->priv) { 207 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 208 GFP_KERNEL); 209 if (!dp83867) 210 return -ENOMEM; 211 212 phydev->priv = dp83867; 213 ret = dp83867_of_init(phydev); 214 if (ret) 215 return ret; 216 } else { 217 dp83867 = (struct dp83867_private *)phydev->priv; 218 } 219 220 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 221 if (dp83867->rxctrl_strap_quirk) 222 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 223 BIT(7)); 224 225 if (phy_interface_is_rgmii(phydev)) { 226 val = phy_read(phydev, MII_DP83867_PHYCTRL); 227 if (val < 0) 228 return val; 229 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; 230 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); 231 232 /* The code below checks if "port mirroring" N/A MODE4 has been 233 * enabled during power on bootstrap. 234 * 235 * Such N/A mode enabled by mistake can put PHY IC in some 236 * internal testing mode and disable RGMII transmission. 237 * 238 * In this particular case one needs to check STRAP_STS1 239 * register's bit 11 (marked as RESERVED). 240 */ 241 242 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 243 if (bs & DP83867_STRAP_STS1_RESERVED) 244 val &= ~DP83867_PHYCR_RESERVED_MASK; 245 246 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 247 if (ret) 248 return ret; 249 } 250 251 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 252 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 253 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 254 255 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 256 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 257 258 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 259 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 260 261 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 262 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 263 264 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 265 266 delay = (dp83867->rx_id_delay | 267 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 268 269 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 270 delay); 271 272 if (dp83867->io_impedance >= 0) 273 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 274 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 275 dp83867->io_impedance & 276 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 277 } 278 279 /* Enable Interrupt output INT_OE in CFG3 register */ 280 if (phy_interrupt_is_valid(phydev)) { 281 val = phy_read(phydev, DP83867_CFG3); 282 val |= BIT(7); 283 phy_write(phydev, DP83867_CFG3, val); 284 } 285 286 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 287 dp83867_config_port_mirroring(phydev); 288 289 /* Clock output selection if muxing property is set */ 290 if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) 291 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 292 DP83867_IO_MUX_CFG_CLK_O_SEL_MASK, 293 dp83867->clk_output_sel << 294 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT); 295 296 return 0; 297 } 298 299 static int dp83867_phy_reset(struct phy_device *phydev) 300 { 301 int err; 302 303 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 304 if (err < 0) 305 return err; 306 307 return dp83867_config_init(phydev); 308 } 309 310 static struct phy_driver dp83867_driver[] = { 311 { 312 .phy_id = DP83867_PHY_ID, 313 .phy_id_mask = 0xfffffff0, 314 .name = "TI DP83867", 315 .features = PHY_GBIT_FEATURES, 316 317 .config_init = dp83867_config_init, 318 .soft_reset = dp83867_phy_reset, 319 320 /* IRQ related */ 321 .ack_interrupt = dp83867_ack_interrupt, 322 .config_intr = dp83867_config_intr, 323 324 .suspend = genphy_suspend, 325 .resume = genphy_resume, 326 }, 327 }; 328 module_phy_driver(dp83867_driver); 329 330 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 331 { DP83867_PHY_ID, 0xfffffff0 }, 332 { } 333 }; 334 335 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 336 337 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 338 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 339 MODULE_LICENSE("GPL v2"); 340