1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DP83867 PHY 4 * 5 * Copyright (C) 2015 Texas Instruments Inc. 6 */ 7 8 #include <linux/ethtool.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/delay.h> 15 16 #include <dt-bindings/net/ti-dp83867.h> 17 18 #define DP83867_PHY_ID 0x2000a231 19 #define DP83867_DEVADDR 0x1f 20 21 #define MII_DP83867_PHYCTRL 0x10 22 #define MII_DP83867_MICR 0x12 23 #define MII_DP83867_ISR 0x13 24 #define DP83867_CTRL 0x1f 25 #define DP83867_CFG3 0x1e 26 27 /* Extended Registers */ 28 #define DP83867_CFG4 0x0031 29 #define DP83867_RGMIICTL 0x0032 30 #define DP83867_STRAP_STS1 0x006E 31 #define DP83867_STRAP_STS2 0x006f 32 #define DP83867_RGMIIDCTL 0x0086 33 #define DP83867_IO_MUX_CFG 0x0170 34 35 #define DP83867_SW_RESET BIT(15) 36 #define DP83867_SW_RESTART BIT(14) 37 38 /* MICR Interrupt bits */ 39 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 40 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 41 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 42 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 43 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 44 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 45 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 46 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 47 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 48 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 49 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 50 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 51 52 /* RGMIICTL bits */ 53 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 54 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 55 56 /* STRAP_STS1 bits */ 57 #define DP83867_STRAP_STS1_RESERVED BIT(11) 58 59 /* STRAP_STS2 bits */ 60 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 61 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 62 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 63 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 64 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 65 66 /* PHY CTRL bits */ 67 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 68 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 69 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) 70 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 71 72 /* RGMIIDCTL bits */ 73 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 74 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 75 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 76 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 77 78 /* IO_MUX_CFG bits */ 79 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 80 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 81 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 82 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 83 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 84 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 85 86 /* CFG4 bits */ 87 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 88 89 enum { 90 DP83867_PORT_MIRROING_KEEP, 91 DP83867_PORT_MIRROING_EN, 92 DP83867_PORT_MIRROING_DIS, 93 }; 94 95 struct dp83867_private { 96 u32 rx_id_delay; 97 u32 tx_id_delay; 98 u32 fifo_depth; 99 int io_impedance; 100 int port_mirroring; 101 bool rxctrl_strap_quirk; 102 bool set_clk_output; 103 u32 clk_output_sel; 104 }; 105 106 static int dp83867_ack_interrupt(struct phy_device *phydev) 107 { 108 int err = phy_read(phydev, MII_DP83867_ISR); 109 110 if (err < 0) 111 return err; 112 113 return 0; 114 } 115 116 static int dp83867_config_intr(struct phy_device *phydev) 117 { 118 int micr_status; 119 120 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 121 micr_status = phy_read(phydev, MII_DP83867_MICR); 122 if (micr_status < 0) 123 return micr_status; 124 125 micr_status |= 126 (MII_DP83867_MICR_AN_ERR_INT_EN | 127 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 128 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 129 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 130 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 131 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 132 133 return phy_write(phydev, MII_DP83867_MICR, micr_status); 134 } 135 136 micr_status = 0x0; 137 return phy_write(phydev, MII_DP83867_MICR, micr_status); 138 } 139 140 static int dp83867_config_port_mirroring(struct phy_device *phydev) 141 { 142 struct dp83867_private *dp83867 = 143 (struct dp83867_private *)phydev->priv; 144 145 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 146 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 147 DP83867_CFG4_PORT_MIRROR_EN); 148 else 149 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 150 DP83867_CFG4_PORT_MIRROR_EN); 151 return 0; 152 } 153 154 #ifdef CONFIG_OF_MDIO 155 static int dp83867_of_init(struct phy_device *phydev) 156 { 157 struct dp83867_private *dp83867 = phydev->priv; 158 struct device *dev = &phydev->mdio.dev; 159 struct device_node *of_node = dev->of_node; 160 int ret; 161 162 if (!of_node) 163 return -ENODEV; 164 165 /* Optional configuration */ 166 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 167 &dp83867->clk_output_sel); 168 /* If not set, keep default */ 169 if (!ret) { 170 dp83867->set_clk_output = true; 171 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 172 * DP83867_CLK_O_SEL_OFF. 173 */ 174 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 175 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 176 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 177 dp83867->clk_output_sel); 178 return -EINVAL; 179 } 180 } 181 182 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 183 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 184 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 185 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 186 else 187 dp83867->io_impedance = -1; /* leave at default */ 188 189 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 190 "ti,dp83867-rxctrl-strap-quirk"); 191 192 /* Existing behavior was to use default pin strapping delay in rgmii 193 * mode, but rgmii should have meant no delay. Warn existing users. 194 */ 195 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 196 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); 197 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 198 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 199 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 200 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 201 202 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 203 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 204 phydev_warn(phydev, 205 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 206 "Should be 'rgmii-id' to use internal delays\n"); 207 } 208 209 /* RX delay *must* be specified if internal delay of RX is used. */ 210 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 211 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 212 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 213 &dp83867->rx_id_delay); 214 if (ret) { 215 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 216 return ret; 217 } 218 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 219 phydev_err(phydev, 220 "ti,rx-internal-delay value of %u out of range\n", 221 dp83867->rx_id_delay); 222 return -EINVAL; 223 } 224 } 225 226 /* TX delay *must* be specified if internal delay of RX is used. */ 227 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 228 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 229 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 230 &dp83867->tx_id_delay); 231 if (ret) { 232 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 233 return ret; 234 } 235 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 236 phydev_err(phydev, 237 "ti,tx-internal-delay value of %u out of range\n", 238 dp83867->tx_id_delay); 239 return -EINVAL; 240 } 241 } 242 243 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 244 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 245 246 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 247 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 248 249 ret = of_property_read_u32(of_node, "ti,fifo-depth", 250 &dp83867->fifo_depth); 251 if (ret) { 252 phydev_err(phydev, 253 "ti,fifo-depth property is required\n"); 254 return ret; 255 } 256 if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 257 phydev_err(phydev, 258 "ti,fifo-depth value %u out of range\n", 259 dp83867->fifo_depth); 260 return -EINVAL; 261 } 262 return 0; 263 } 264 #else 265 static int dp83867_of_init(struct phy_device *phydev) 266 { 267 return 0; 268 } 269 #endif /* CONFIG_OF_MDIO */ 270 271 static int dp83867_probe(struct phy_device *phydev) 272 { 273 struct dp83867_private *dp83867; 274 275 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 276 GFP_KERNEL); 277 if (!dp83867) 278 return -ENOMEM; 279 280 phydev->priv = dp83867; 281 282 return 0; 283 } 284 285 static int dp83867_config_init(struct phy_device *phydev) 286 { 287 struct dp83867_private *dp83867 = phydev->priv; 288 int ret, val, bs; 289 u16 delay; 290 291 ret = dp83867_of_init(phydev); 292 if (ret) 293 return ret; 294 295 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 296 if (dp83867->rxctrl_strap_quirk) 297 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 298 BIT(7)); 299 300 if (phy_interface_is_rgmii(phydev)) { 301 val = phy_read(phydev, MII_DP83867_PHYCTRL); 302 if (val < 0) 303 return val; 304 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; 305 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); 306 307 /* The code below checks if "port mirroring" N/A MODE4 has been 308 * enabled during power on bootstrap. 309 * 310 * Such N/A mode enabled by mistake can put PHY IC in some 311 * internal testing mode and disable RGMII transmission. 312 * 313 * In this particular case one needs to check STRAP_STS1 314 * register's bit 11 (marked as RESERVED). 315 */ 316 317 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 318 if (bs & DP83867_STRAP_STS1_RESERVED) 319 val &= ~DP83867_PHYCR_RESERVED_MASK; 320 321 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 322 if (ret) 323 return ret; 324 } 325 326 /* If rgmii mode with no internal delay is selected, we do NOT use 327 * aligned mode as one might expect. Instead we use the PHY's default 328 * based on pin strapping. And the "mode 0" default is to *use* 329 * internal delay with a value of 7 (2.00 ns). 330 */ 331 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 332 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 333 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 334 335 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 336 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 337 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 338 339 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 340 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 341 342 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 343 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 344 345 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 346 347 delay = (dp83867->rx_id_delay | 348 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 349 350 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 351 delay); 352 } 353 354 /* If specified, set io impedance */ 355 if (dp83867->io_impedance >= 0) 356 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 357 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 358 dp83867->io_impedance); 359 360 /* Enable Interrupt output INT_OE in CFG3 register */ 361 if (phy_interrupt_is_valid(phydev)) { 362 val = phy_read(phydev, DP83867_CFG3); 363 val |= BIT(7); 364 phy_write(phydev, DP83867_CFG3, val); 365 } 366 367 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 368 dp83867_config_port_mirroring(phydev); 369 370 /* Clock output selection if muxing property is set */ 371 if (dp83867->set_clk_output) { 372 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 373 374 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 375 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 376 } else { 377 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 378 val = dp83867->clk_output_sel << 379 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 380 } 381 382 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 383 mask, val); 384 } 385 386 return 0; 387 } 388 389 static int dp83867_phy_reset(struct phy_device *phydev) 390 { 391 int err; 392 393 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 394 if (err < 0) 395 return err; 396 397 usleep_range(10, 20); 398 399 return dp83867_config_init(phydev); 400 } 401 402 static struct phy_driver dp83867_driver[] = { 403 { 404 .phy_id = DP83867_PHY_ID, 405 .phy_id_mask = 0xfffffff0, 406 .name = "TI DP83867", 407 /* PHY_GBIT_FEATURES */ 408 409 .probe = dp83867_probe, 410 .config_init = dp83867_config_init, 411 .soft_reset = dp83867_phy_reset, 412 413 /* IRQ related */ 414 .ack_interrupt = dp83867_ack_interrupt, 415 .config_intr = dp83867_config_intr, 416 417 .suspend = genphy_suspend, 418 .resume = genphy_resume, 419 }, 420 }; 421 module_phy_driver(dp83867_driver); 422 423 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 424 { DP83867_PHY_ID, 0xfffffff0 }, 425 { } 426 }; 427 428 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 429 430 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 431 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 432 MODULE_LICENSE("GPL v2"); 433