1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DP83867 PHY 4 * 5 * Copyright (C) 2015 Texas Instruments Inc. 6 */ 7 8 #include <linux/ethtool.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/delay.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 18 #include <dt-bindings/net/ti-dp83867.h> 19 20 #define DP83867_PHY_ID 0x2000a231 21 #define DP83867_DEVADDR 0x1f 22 23 #define MII_DP83867_PHYCTRL 0x10 24 #define MII_DP83867_MICR 0x12 25 #define MII_DP83867_ISR 0x13 26 #define DP83867_CFG2 0x14 27 #define DP83867_CFG3 0x1e 28 #define DP83867_CTRL 0x1f 29 30 /* Extended Registers */ 31 #define DP83867_CFG4 0x0031 32 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 33 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 34 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 35 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 36 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 37 38 #define DP83867_RGMIICTL 0x0032 39 #define DP83867_STRAP_STS1 0x006E 40 #define DP83867_STRAP_STS2 0x006f 41 #define DP83867_RGMIIDCTL 0x0086 42 #define DP83867_RXFCFG 0x0134 43 #define DP83867_RXFPMD1 0x0136 44 #define DP83867_RXFPMD2 0x0137 45 #define DP83867_RXFPMD3 0x0138 46 #define DP83867_RXFSOP1 0x0139 47 #define DP83867_RXFSOP2 0x013A 48 #define DP83867_RXFSOP3 0x013B 49 #define DP83867_IO_MUX_CFG 0x0170 50 #define DP83867_SGMIICTL 0x00D3 51 #define DP83867_10M_SGMII_CFG 0x016F 52 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 53 54 #define DP83867_SW_RESET BIT(15) 55 #define DP83867_SW_RESTART BIT(14) 56 57 /* MICR Interrupt bits */ 58 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 59 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 60 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 61 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 62 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 63 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 64 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 65 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 66 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 67 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 68 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 69 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 70 71 /* RGMIICTL bits */ 72 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 73 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 74 75 /* SGMIICTL bits */ 76 #define DP83867_SGMII_TYPE BIT(14) 77 78 /* RXFCFG bits*/ 79 #define DP83867_WOL_MAGIC_EN BIT(0) 80 #define DP83867_WOL_BCAST_EN BIT(2) 81 #define DP83867_WOL_UCAST_EN BIT(4) 82 #define DP83867_WOL_SEC_EN BIT(5) 83 #define DP83867_WOL_ENH_MAC BIT(7) 84 85 /* STRAP_STS1 bits */ 86 #define DP83867_STRAP_STS1_RESERVED BIT(11) 87 88 /* STRAP_STS2 bits */ 89 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 90 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 91 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 92 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 93 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 94 95 /* PHY CTRL bits */ 96 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 97 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 98 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) 99 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 100 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 101 102 /* RGMIIDCTL bits */ 103 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 104 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 105 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 106 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 107 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 108 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 109 110 111 /* IO_MUX_CFG bits */ 112 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 113 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 114 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 115 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 116 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 117 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 118 119 /* CFG3 bits */ 120 #define DP83867_CFG3_INT_OE BIT(7) 121 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 122 123 /* CFG4 bits */ 124 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 125 126 enum { 127 DP83867_PORT_MIRROING_KEEP, 128 DP83867_PORT_MIRROING_EN, 129 DP83867_PORT_MIRROING_DIS, 130 }; 131 132 struct dp83867_private { 133 u32 rx_id_delay; 134 u32 tx_id_delay; 135 u32 fifo_depth; 136 int io_impedance; 137 int port_mirroring; 138 bool rxctrl_strap_quirk; 139 bool set_clk_output; 140 u32 clk_output_sel; 141 bool sgmii_ref_clk_en; 142 }; 143 144 static int dp83867_ack_interrupt(struct phy_device *phydev) 145 { 146 int err = phy_read(phydev, MII_DP83867_ISR); 147 148 if (err < 0) 149 return err; 150 151 return 0; 152 } 153 154 static int dp83867_set_wol(struct phy_device *phydev, 155 struct ethtool_wolinfo *wol) 156 { 157 struct net_device *ndev = phydev->attached_dev; 158 u16 val_rxcfg, val_micr; 159 u8 *mac; 160 161 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 162 val_micr = phy_read(phydev, MII_DP83867_MICR); 163 164 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 165 WAKE_BCAST)) { 166 val_rxcfg |= DP83867_WOL_ENH_MAC; 167 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 168 169 if (wol->wolopts & WAKE_MAGIC) { 170 mac = (u8 *)ndev->dev_addr; 171 172 if (!is_valid_ether_addr(mac)) 173 return -EINVAL; 174 175 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 176 (mac[1] << 8 | mac[0])); 177 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 178 (mac[3] << 8 | mac[2])); 179 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 180 (mac[5] << 8 | mac[4])); 181 182 val_rxcfg |= DP83867_WOL_MAGIC_EN; 183 } else { 184 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 185 } 186 187 if (wol->wolopts & WAKE_MAGICSECURE) { 188 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 189 (wol->sopass[1] << 8) | wol->sopass[0]); 190 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 191 (wol->sopass[3] << 8) | wol->sopass[2]); 192 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 193 (wol->sopass[5] << 8) | wol->sopass[4]); 194 195 val_rxcfg |= DP83867_WOL_SEC_EN; 196 } else { 197 val_rxcfg &= ~DP83867_WOL_SEC_EN; 198 } 199 200 if (wol->wolopts & WAKE_UCAST) 201 val_rxcfg |= DP83867_WOL_UCAST_EN; 202 else 203 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 204 205 if (wol->wolopts & WAKE_BCAST) 206 val_rxcfg |= DP83867_WOL_BCAST_EN; 207 else 208 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 209 } else { 210 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 211 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 212 } 213 214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 215 phy_write(phydev, MII_DP83867_MICR, val_micr); 216 217 return 0; 218 } 219 220 static void dp83867_get_wol(struct phy_device *phydev, 221 struct ethtool_wolinfo *wol) 222 { 223 u16 value, sopass_val; 224 225 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 226 WAKE_MAGICSECURE); 227 wol->wolopts = 0; 228 229 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 230 231 if (value & DP83867_WOL_UCAST_EN) 232 wol->wolopts |= WAKE_UCAST; 233 234 if (value & DP83867_WOL_BCAST_EN) 235 wol->wolopts |= WAKE_BCAST; 236 237 if (value & DP83867_WOL_MAGIC_EN) 238 wol->wolopts |= WAKE_MAGIC; 239 240 if (value & DP83867_WOL_SEC_EN) { 241 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 242 DP83867_RXFSOP1); 243 wol->sopass[0] = (sopass_val & 0xff); 244 wol->sopass[1] = (sopass_val >> 8); 245 246 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 247 DP83867_RXFSOP2); 248 wol->sopass[2] = (sopass_val & 0xff); 249 wol->sopass[3] = (sopass_val >> 8); 250 251 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 252 DP83867_RXFSOP3); 253 wol->sopass[4] = (sopass_val & 0xff); 254 wol->sopass[5] = (sopass_val >> 8); 255 256 wol->wolopts |= WAKE_MAGICSECURE; 257 } 258 259 if (!(value & DP83867_WOL_ENH_MAC)) 260 wol->wolopts = 0; 261 } 262 263 static int dp83867_config_intr(struct phy_device *phydev) 264 { 265 int micr_status; 266 267 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 268 micr_status = phy_read(phydev, MII_DP83867_MICR); 269 if (micr_status < 0) 270 return micr_status; 271 272 micr_status |= 273 (MII_DP83867_MICR_AN_ERR_INT_EN | 274 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 275 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 276 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 277 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 278 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 279 280 return phy_write(phydev, MII_DP83867_MICR, micr_status); 281 } 282 283 micr_status = 0x0; 284 return phy_write(phydev, MII_DP83867_MICR, micr_status); 285 } 286 287 static int dp83867_config_port_mirroring(struct phy_device *phydev) 288 { 289 struct dp83867_private *dp83867 = 290 (struct dp83867_private *)phydev->priv; 291 292 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 293 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 294 DP83867_CFG4_PORT_MIRROR_EN); 295 else 296 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 297 DP83867_CFG4_PORT_MIRROR_EN); 298 return 0; 299 } 300 301 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 302 { 303 struct dp83867_private *dp83867 = phydev->priv; 304 305 /* Existing behavior was to use default pin strapping delay in rgmii 306 * mode, but rgmii should have meant no delay. Warn existing users. 307 */ 308 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 309 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 310 DP83867_STRAP_STS2); 311 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 312 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 313 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 314 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 315 316 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 317 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 318 phydev_warn(phydev, 319 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 320 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 321 txskew, rxskew); 322 } 323 324 /* RX delay *must* be specified if internal delay of RX is used. */ 325 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 326 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 327 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 328 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 329 return -EINVAL; 330 } 331 332 /* TX delay *must* be specified if internal delay of TX is used. */ 333 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 334 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 335 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 336 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 337 return -EINVAL; 338 } 339 340 return 0; 341 } 342 343 #ifdef CONFIG_OF_MDIO 344 static int dp83867_of_init(struct phy_device *phydev) 345 { 346 struct dp83867_private *dp83867 = phydev->priv; 347 struct device *dev = &phydev->mdio.dev; 348 struct device_node *of_node = dev->of_node; 349 int ret; 350 351 if (!of_node) 352 return -ENODEV; 353 354 /* Optional configuration */ 355 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 356 &dp83867->clk_output_sel); 357 /* If not set, keep default */ 358 if (!ret) { 359 dp83867->set_clk_output = true; 360 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 361 * DP83867_CLK_O_SEL_OFF. 362 */ 363 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 364 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 365 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 366 dp83867->clk_output_sel); 367 return -EINVAL; 368 } 369 } 370 371 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 372 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 373 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 374 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 375 else 376 dp83867->io_impedance = -1; /* leave at default */ 377 378 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 379 "ti,dp83867-rxctrl-strap-quirk"); 380 381 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 382 "ti,sgmii-ref-clock-output-enable"); 383 384 385 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 386 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 387 &dp83867->rx_id_delay); 388 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 389 phydev_err(phydev, 390 "ti,rx-internal-delay value of %u out of range\n", 391 dp83867->rx_id_delay); 392 return -EINVAL; 393 } 394 395 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 396 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 397 &dp83867->tx_id_delay); 398 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 399 phydev_err(phydev, 400 "ti,tx-internal-delay value of %u out of range\n", 401 dp83867->tx_id_delay); 402 return -EINVAL; 403 } 404 405 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 406 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 407 408 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 409 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 410 411 ret = of_property_read_u32(of_node, "ti,fifo-depth", 412 &dp83867->fifo_depth); 413 if (ret) { 414 phydev_err(phydev, 415 "ti,fifo-depth property is required\n"); 416 return ret; 417 } 418 if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 419 phydev_err(phydev, 420 "ti,fifo-depth value %u out of range\n", 421 dp83867->fifo_depth); 422 return -EINVAL; 423 } 424 return 0; 425 } 426 #else 427 static int dp83867_of_init(struct phy_device *phydev) 428 { 429 return 0; 430 } 431 #endif /* CONFIG_OF_MDIO */ 432 433 static int dp83867_probe(struct phy_device *phydev) 434 { 435 struct dp83867_private *dp83867; 436 437 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 438 GFP_KERNEL); 439 if (!dp83867) 440 return -ENOMEM; 441 442 phydev->priv = dp83867; 443 444 return dp83867_of_init(phydev); 445 } 446 447 static int dp83867_config_init(struct phy_device *phydev) 448 { 449 struct dp83867_private *dp83867 = phydev->priv; 450 int ret, val, bs; 451 u16 delay; 452 453 ret = dp83867_verify_rgmii_cfg(phydev); 454 if (ret) 455 return ret; 456 457 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 458 if (dp83867->rxctrl_strap_quirk) 459 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 460 BIT(7)); 461 462 if (phy_interface_is_rgmii(phydev)) { 463 val = phy_read(phydev, MII_DP83867_PHYCTRL); 464 if (val < 0) 465 return val; 466 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; 467 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); 468 469 /* The code below checks if "port mirroring" N/A MODE4 has been 470 * enabled during power on bootstrap. 471 * 472 * Such N/A mode enabled by mistake can put PHY IC in some 473 * internal testing mode and disable RGMII transmission. 474 * 475 * In this particular case one needs to check STRAP_STS1 476 * register's bit 11 (marked as RESERVED). 477 */ 478 479 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 480 if (bs & DP83867_STRAP_STS1_RESERVED) 481 val &= ~DP83867_PHYCR_RESERVED_MASK; 482 483 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 484 if (ret) 485 return ret; 486 487 /* If rgmii mode with no internal delay is selected, we do NOT use 488 * aligned mode as one might expect. Instead we use the PHY's default 489 * based on pin strapping. And the "mode 0" default is to *use* 490 * internal delay with a value of 7 (2.00 ns). 491 * 492 * Set up RGMII delays 493 */ 494 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 495 496 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 497 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 498 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 499 500 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 501 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 502 503 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 504 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 505 506 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 507 508 delay = 0; 509 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 510 delay |= dp83867->rx_id_delay; 511 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 512 delay |= dp83867->tx_id_delay << 513 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 514 515 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 516 delay); 517 } 518 519 /* If specified, set io impedance */ 520 if (dp83867->io_impedance >= 0) 521 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 522 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 523 dp83867->io_impedance); 524 525 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 526 /* For support SPEED_10 in SGMII mode 527 * DP83867_10M_SGMII_RATE_ADAPT bit 528 * has to be cleared by software. That 529 * does not affect SPEED_100 and 530 * SPEED_1000. 531 */ 532 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 533 DP83867_10M_SGMII_CFG, 534 DP83867_10M_SGMII_RATE_ADAPT_MASK, 535 0); 536 if (ret) 537 return ret; 538 539 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 540 * are 01). That is not enough to finalize autoneg on some 541 * devices. Increase this timer duration to maximum 16ms. 542 */ 543 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 544 DP83867_CFG4, 545 DP83867_CFG4_SGMII_ANEG_MASK, 546 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 547 548 if (ret) 549 return ret; 550 551 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 552 /* SGMII type is set to 4-wire mode by default. 553 * If we place appropriate property in dts (see above) 554 * switch on 6-wire mode. 555 */ 556 if (dp83867->sgmii_ref_clk_en) 557 val |= DP83867_SGMII_TYPE; 558 else 559 val &= ~DP83867_SGMII_TYPE; 560 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 561 } 562 563 val = phy_read(phydev, DP83867_CFG3); 564 /* Enable Interrupt output INT_OE in CFG3 register */ 565 if (phy_interrupt_is_valid(phydev)) 566 val |= DP83867_CFG3_INT_OE; 567 568 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 569 phy_write(phydev, DP83867_CFG3, val); 570 571 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 572 dp83867_config_port_mirroring(phydev); 573 574 /* Clock output selection if muxing property is set */ 575 if (dp83867->set_clk_output) { 576 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 577 578 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 579 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 580 } else { 581 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 582 val = dp83867->clk_output_sel << 583 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 584 } 585 586 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 587 mask, val); 588 } 589 590 return 0; 591 } 592 593 static int dp83867_phy_reset(struct phy_device *phydev) 594 { 595 int err; 596 597 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 598 if (err < 0) 599 return err; 600 601 usleep_range(10, 20); 602 603 /* After reset FORCE_LINK_GOOD bit is set. Although the 604 * default value should be unset. Disable FORCE_LINK_GOOD 605 * for the phy to work properly. 606 */ 607 return phy_modify(phydev, MII_DP83867_PHYCTRL, 608 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 609 } 610 611 static struct phy_driver dp83867_driver[] = { 612 { 613 .phy_id = DP83867_PHY_ID, 614 .phy_id_mask = 0xfffffff0, 615 .name = "TI DP83867", 616 /* PHY_GBIT_FEATURES */ 617 618 .probe = dp83867_probe, 619 .config_init = dp83867_config_init, 620 .soft_reset = dp83867_phy_reset, 621 622 .get_wol = dp83867_get_wol, 623 .set_wol = dp83867_set_wol, 624 625 /* IRQ related */ 626 .ack_interrupt = dp83867_ack_interrupt, 627 .config_intr = dp83867_config_intr, 628 629 .suspend = genphy_suspend, 630 .resume = genphy_resume, 631 }, 632 }; 633 module_phy_driver(dp83867_driver); 634 635 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 636 { DP83867_PHY_ID, 0xfffffff0 }, 637 { } 638 }; 639 640 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 641 642 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 643 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 644 MODULE_LICENSE("GPL v2"); 645