1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/bitfield.h> 17 18 #include <dt-bindings/net/ti-dp83867.h> 19 20 #define DP83867_PHY_ID 0x2000a231 21 #define DP83867_DEVADDR 0x1f 22 23 #define MII_DP83867_PHYCTRL 0x10 24 #define MII_DP83867_PHYSTS 0x11 25 #define MII_DP83867_MICR 0x12 26 #define MII_DP83867_ISR 0x13 27 #define DP83867_CFG2 0x14 28 #define DP83867_CFG3 0x1e 29 #define DP83867_CTRL 0x1f 30 31 /* Extended Registers */ 32 #define DP83867_FLD_THR_CFG 0x002e 33 #define DP83867_CFG4 0x0031 34 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 35 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 36 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 37 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 38 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 39 40 #define DP83867_RGMIICTL 0x0032 41 #define DP83867_STRAP_STS1 0x006E 42 #define DP83867_STRAP_STS2 0x006f 43 #define DP83867_RGMIIDCTL 0x0086 44 #define DP83867_RXFCFG 0x0134 45 #define DP83867_RXFPMD1 0x0136 46 #define DP83867_RXFPMD2 0x0137 47 #define DP83867_RXFPMD3 0x0138 48 #define DP83867_RXFSOP1 0x0139 49 #define DP83867_RXFSOP2 0x013A 50 #define DP83867_RXFSOP3 0x013B 51 #define DP83867_IO_MUX_CFG 0x0170 52 #define DP83867_SGMIICTL 0x00D3 53 #define DP83867_10M_SGMII_CFG 0x016F 54 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 55 56 #define DP83867_SW_RESET BIT(15) 57 #define DP83867_SW_RESTART BIT(14) 58 59 /* MICR Interrupt bits */ 60 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 61 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 62 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 63 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 64 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 65 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 66 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 67 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 68 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 69 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 70 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 71 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 72 73 /* RGMIICTL bits */ 74 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 75 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 76 77 /* SGMIICTL bits */ 78 #define DP83867_SGMII_TYPE BIT(14) 79 80 /* RXFCFG bits*/ 81 #define DP83867_WOL_MAGIC_EN BIT(0) 82 #define DP83867_WOL_BCAST_EN BIT(2) 83 #define DP83867_WOL_UCAST_EN BIT(4) 84 #define DP83867_WOL_SEC_EN BIT(5) 85 #define DP83867_WOL_ENH_MAC BIT(7) 86 87 /* STRAP_STS1 bits */ 88 #define DP83867_STRAP_STS1_RESERVED BIT(11) 89 90 /* STRAP_STS2 bits */ 91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 92 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 94 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 95 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 96 #define DP83867_STRAP_STS2_STRAP_FLD BIT(10) 97 98 /* PHY CTRL bits */ 99 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 101 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 102 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 103 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 104 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 105 #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) 106 107 /* RGMIIDCTL bits */ 108 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 109 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 110 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 111 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 112 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 113 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 114 115 /* IO_MUX_CFG bits */ 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 122 123 /* PHY STS bits */ 124 #define DP83867_PHYSTS_1000 BIT(15) 125 #define DP83867_PHYSTS_100 BIT(14) 126 #define DP83867_PHYSTS_DUPLEX BIT(13) 127 #define DP83867_PHYSTS_LINK BIT(10) 128 129 /* CFG2 bits */ 130 #define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9)) 131 #define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 132 #define DP83867_DOWNSHIFT_1_COUNT_VAL 0 133 #define DP83867_DOWNSHIFT_2_COUNT_VAL 1 134 #define DP83867_DOWNSHIFT_4_COUNT_VAL 2 135 #define DP83867_DOWNSHIFT_8_COUNT_VAL 3 136 #define DP83867_DOWNSHIFT_1_COUNT 1 137 #define DP83867_DOWNSHIFT_2_COUNT 2 138 #define DP83867_DOWNSHIFT_4_COUNT 4 139 #define DP83867_DOWNSHIFT_8_COUNT 8 140 141 /* CFG3 bits */ 142 #define DP83867_CFG3_INT_OE BIT(7) 143 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 144 145 /* CFG4 bits */ 146 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 147 148 /* FLD_THR_CFG */ 149 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7 150 151 enum { 152 DP83867_PORT_MIRROING_KEEP, 153 DP83867_PORT_MIRROING_EN, 154 DP83867_PORT_MIRROING_DIS, 155 }; 156 157 struct dp83867_private { 158 u32 rx_id_delay; 159 u32 tx_id_delay; 160 u32 tx_fifo_depth; 161 u32 rx_fifo_depth; 162 int io_impedance; 163 int port_mirroring; 164 bool rxctrl_strap_quirk; 165 bool set_clk_output; 166 u32 clk_output_sel; 167 bool sgmii_ref_clk_en; 168 }; 169 170 static int dp83867_ack_interrupt(struct phy_device *phydev) 171 { 172 int err = phy_read(phydev, MII_DP83867_ISR); 173 174 if (err < 0) 175 return err; 176 177 return 0; 178 } 179 180 static int dp83867_set_wol(struct phy_device *phydev, 181 struct ethtool_wolinfo *wol) 182 { 183 struct net_device *ndev = phydev->attached_dev; 184 u16 val_rxcfg, val_micr; 185 u8 *mac; 186 187 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 188 val_micr = phy_read(phydev, MII_DP83867_MICR); 189 190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 191 WAKE_BCAST)) { 192 val_rxcfg |= DP83867_WOL_ENH_MAC; 193 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 194 195 if (wol->wolopts & WAKE_MAGIC) { 196 mac = (u8 *)ndev->dev_addr; 197 198 if (!is_valid_ether_addr(mac)) 199 return -EINVAL; 200 201 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 202 (mac[1] << 8 | mac[0])); 203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 204 (mac[3] << 8 | mac[2])); 205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 206 (mac[5] << 8 | mac[4])); 207 208 val_rxcfg |= DP83867_WOL_MAGIC_EN; 209 } else { 210 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 211 } 212 213 if (wol->wolopts & WAKE_MAGICSECURE) { 214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 215 (wol->sopass[1] << 8) | wol->sopass[0]); 216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, 217 (wol->sopass[3] << 8) | wol->sopass[2]); 218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, 219 (wol->sopass[5] << 8) | wol->sopass[4]); 220 221 val_rxcfg |= DP83867_WOL_SEC_EN; 222 } else { 223 val_rxcfg &= ~DP83867_WOL_SEC_EN; 224 } 225 226 if (wol->wolopts & WAKE_UCAST) 227 val_rxcfg |= DP83867_WOL_UCAST_EN; 228 else 229 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 230 231 if (wol->wolopts & WAKE_BCAST) 232 val_rxcfg |= DP83867_WOL_BCAST_EN; 233 else 234 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 235 } else { 236 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 237 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 238 } 239 240 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 241 phy_write(phydev, MII_DP83867_MICR, val_micr); 242 243 return 0; 244 } 245 246 static void dp83867_get_wol(struct phy_device *phydev, 247 struct ethtool_wolinfo *wol) 248 { 249 u16 value, sopass_val; 250 251 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 252 WAKE_MAGICSECURE); 253 wol->wolopts = 0; 254 255 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 256 257 if (value & DP83867_WOL_UCAST_EN) 258 wol->wolopts |= WAKE_UCAST; 259 260 if (value & DP83867_WOL_BCAST_EN) 261 wol->wolopts |= WAKE_BCAST; 262 263 if (value & DP83867_WOL_MAGIC_EN) 264 wol->wolopts |= WAKE_MAGIC; 265 266 if (value & DP83867_WOL_SEC_EN) { 267 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 268 DP83867_RXFSOP1); 269 wol->sopass[0] = (sopass_val & 0xff); 270 wol->sopass[1] = (sopass_val >> 8); 271 272 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 273 DP83867_RXFSOP2); 274 wol->sopass[2] = (sopass_val & 0xff); 275 wol->sopass[3] = (sopass_val >> 8); 276 277 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 278 DP83867_RXFSOP3); 279 wol->sopass[4] = (sopass_val & 0xff); 280 wol->sopass[5] = (sopass_val >> 8); 281 282 wol->wolopts |= WAKE_MAGICSECURE; 283 } 284 285 if (!(value & DP83867_WOL_ENH_MAC)) 286 wol->wolopts = 0; 287 } 288 289 static int dp83867_config_intr(struct phy_device *phydev) 290 { 291 int micr_status; 292 293 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 294 micr_status = phy_read(phydev, MII_DP83867_MICR); 295 if (micr_status < 0) 296 return micr_status; 297 298 micr_status |= 299 (MII_DP83867_MICR_AN_ERR_INT_EN | 300 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 301 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 302 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 303 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 304 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 305 306 return phy_write(phydev, MII_DP83867_MICR, micr_status); 307 } 308 309 micr_status = 0x0; 310 return phy_write(phydev, MII_DP83867_MICR, micr_status); 311 } 312 313 static int dp83867_read_status(struct phy_device *phydev) 314 { 315 int status = phy_read(phydev, MII_DP83867_PHYSTS); 316 int ret; 317 318 ret = genphy_read_status(phydev); 319 if (ret) 320 return ret; 321 322 if (status < 0) 323 return status; 324 325 if (status & DP83867_PHYSTS_DUPLEX) 326 phydev->duplex = DUPLEX_FULL; 327 else 328 phydev->duplex = DUPLEX_HALF; 329 330 if (status & DP83867_PHYSTS_1000) 331 phydev->speed = SPEED_1000; 332 else if (status & DP83867_PHYSTS_100) 333 phydev->speed = SPEED_100; 334 else 335 phydev->speed = SPEED_10; 336 337 return 0; 338 } 339 340 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data) 341 { 342 int val, cnt, enable, count; 343 344 val = phy_read(phydev, DP83867_CFG2); 345 if (val < 0) 346 return val; 347 348 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val); 349 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val); 350 351 switch (cnt) { 352 case DP83867_DOWNSHIFT_1_COUNT_VAL: 353 count = DP83867_DOWNSHIFT_1_COUNT; 354 break; 355 case DP83867_DOWNSHIFT_2_COUNT_VAL: 356 count = DP83867_DOWNSHIFT_2_COUNT; 357 break; 358 case DP83867_DOWNSHIFT_4_COUNT_VAL: 359 count = DP83867_DOWNSHIFT_4_COUNT; 360 break; 361 case DP83867_DOWNSHIFT_8_COUNT_VAL: 362 count = DP83867_DOWNSHIFT_8_COUNT; 363 break; 364 default: 365 return -EINVAL; 366 } 367 368 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 369 370 return 0; 371 } 372 373 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt) 374 { 375 int val, count; 376 377 if (cnt > DP83867_DOWNSHIFT_8_COUNT) 378 return -E2BIG; 379 380 if (!cnt) 381 return phy_clear_bits(phydev, DP83867_CFG2, 382 DP83867_DOWNSHIFT_EN); 383 384 switch (cnt) { 385 case DP83867_DOWNSHIFT_1_COUNT: 386 count = DP83867_DOWNSHIFT_1_COUNT_VAL; 387 break; 388 case DP83867_DOWNSHIFT_2_COUNT: 389 count = DP83867_DOWNSHIFT_2_COUNT_VAL; 390 break; 391 case DP83867_DOWNSHIFT_4_COUNT: 392 count = DP83867_DOWNSHIFT_4_COUNT_VAL; 393 break; 394 case DP83867_DOWNSHIFT_8_COUNT: 395 count = DP83867_DOWNSHIFT_8_COUNT_VAL; 396 break; 397 default: 398 phydev_err(phydev, 399 "Downshift count must be 1, 2, 4 or 8\n"); 400 return -EINVAL; 401 } 402 403 val = DP83867_DOWNSHIFT_EN; 404 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count); 405 406 return phy_modify(phydev, DP83867_CFG2, 407 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK, 408 val); 409 } 410 411 static int dp83867_get_tunable(struct phy_device *phydev, 412 struct ethtool_tunable *tuna, void *data) 413 { 414 switch (tuna->id) { 415 case ETHTOOL_PHY_DOWNSHIFT: 416 return dp83867_get_downshift(phydev, data); 417 default: 418 return -EOPNOTSUPP; 419 } 420 } 421 422 static int dp83867_set_tunable(struct phy_device *phydev, 423 struct ethtool_tunable *tuna, const void *data) 424 { 425 switch (tuna->id) { 426 case ETHTOOL_PHY_DOWNSHIFT: 427 return dp83867_set_downshift(phydev, *(const u8 *)data); 428 default: 429 return -EOPNOTSUPP; 430 } 431 } 432 433 static int dp83867_config_port_mirroring(struct phy_device *phydev) 434 { 435 struct dp83867_private *dp83867 = 436 (struct dp83867_private *)phydev->priv; 437 438 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 439 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 440 DP83867_CFG4_PORT_MIRROR_EN); 441 else 442 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 443 DP83867_CFG4_PORT_MIRROR_EN); 444 return 0; 445 } 446 447 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 448 { 449 struct dp83867_private *dp83867 = phydev->priv; 450 451 /* Existing behavior was to use default pin strapping delay in rgmii 452 * mode, but rgmii should have meant no delay. Warn existing users. 453 */ 454 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 455 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 456 DP83867_STRAP_STS2); 457 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 458 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 459 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 460 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 461 462 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 463 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 464 phydev_warn(phydev, 465 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 466 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 467 txskew, rxskew); 468 } 469 470 /* RX delay *must* be specified if internal delay of RX is used. */ 471 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 472 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 473 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 474 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 475 return -EINVAL; 476 } 477 478 /* TX delay *must* be specified if internal delay of TX is used. */ 479 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 480 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 481 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 482 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488 489 #if IS_ENABLED(CONFIG_OF_MDIO) 490 static int dp83867_of_init(struct phy_device *phydev) 491 { 492 struct dp83867_private *dp83867 = phydev->priv; 493 struct device *dev = &phydev->mdio.dev; 494 struct device_node *of_node = dev->of_node; 495 int ret; 496 497 if (!of_node) 498 return -ENODEV; 499 500 /* Optional configuration */ 501 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 502 &dp83867->clk_output_sel); 503 /* If not set, keep default */ 504 if (!ret) { 505 dp83867->set_clk_output = true; 506 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 507 * DP83867_CLK_O_SEL_OFF. 508 */ 509 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 510 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 511 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 512 dp83867->clk_output_sel); 513 return -EINVAL; 514 } 515 } 516 517 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 518 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 519 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 520 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 521 else 522 dp83867->io_impedance = -1; /* leave at default */ 523 524 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 525 "ti,dp83867-rxctrl-strap-quirk"); 526 527 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 528 "ti,sgmii-ref-clock-output-enable"); 529 530 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 531 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 532 &dp83867->rx_id_delay); 533 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 534 phydev_err(phydev, 535 "ti,rx-internal-delay value of %u out of range\n", 536 dp83867->rx_id_delay); 537 return -EINVAL; 538 } 539 540 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 541 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 542 &dp83867->tx_id_delay); 543 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 544 phydev_err(phydev, 545 "ti,tx-internal-delay value of %u out of range\n", 546 dp83867->tx_id_delay); 547 return -EINVAL; 548 } 549 550 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 551 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 552 553 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 554 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 555 556 ret = of_property_read_u32(of_node, "ti,fifo-depth", 557 &dp83867->tx_fifo_depth); 558 if (ret) { 559 ret = of_property_read_u32(of_node, "tx-fifo-depth", 560 &dp83867->tx_fifo_depth); 561 if (ret) 562 dp83867->tx_fifo_depth = 563 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 564 } 565 566 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 567 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 568 dp83867->tx_fifo_depth); 569 return -EINVAL; 570 } 571 572 ret = of_property_read_u32(of_node, "rx-fifo-depth", 573 &dp83867->rx_fifo_depth); 574 if (ret) 575 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 576 577 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 578 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 579 dp83867->rx_fifo_depth); 580 return -EINVAL; 581 } 582 583 return 0; 584 } 585 #else 586 static int dp83867_of_init(struct phy_device *phydev) 587 { 588 return 0; 589 } 590 #endif /* CONFIG_OF_MDIO */ 591 592 static int dp83867_probe(struct phy_device *phydev) 593 { 594 struct dp83867_private *dp83867; 595 596 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 597 GFP_KERNEL); 598 if (!dp83867) 599 return -ENOMEM; 600 601 phydev->priv = dp83867; 602 603 return dp83867_of_init(phydev); 604 } 605 606 static int dp83867_config_init(struct phy_device *phydev) 607 { 608 struct dp83867_private *dp83867 = phydev->priv; 609 int ret, val, bs; 610 u16 delay; 611 612 /* Force speed optimization for the PHY even if it strapped */ 613 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, 614 DP83867_DOWNSHIFT_EN); 615 if (ret) 616 return ret; 617 618 ret = dp83867_verify_rgmii_cfg(phydev); 619 if (ret) 620 return ret; 621 622 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 623 if (dp83867->rxctrl_strap_quirk) 624 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 625 BIT(7)); 626 627 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); 628 if (bs & DP83867_STRAP_STS2_STRAP_FLD) { 629 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will 630 * be set to 0x2. This may causes the PHY link to be unstable - 631 * the default value 0x1 need to be restored. 632 */ 633 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 634 DP83867_FLD_THR_CFG, 635 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK, 636 0x1); 637 if (ret) 638 return ret; 639 } 640 641 if (phy_interface_is_rgmii(phydev) || 642 phydev->interface == PHY_INTERFACE_MODE_SGMII) { 643 val = phy_read(phydev, MII_DP83867_PHYCTRL); 644 if (val < 0) 645 return val; 646 647 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 648 val |= (dp83867->tx_fifo_depth << 649 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 650 651 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 652 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 653 val |= (dp83867->rx_fifo_depth << 654 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); 655 } 656 657 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 658 if (ret) 659 return ret; 660 } 661 662 if (phy_interface_is_rgmii(phydev)) { 663 val = phy_read(phydev, MII_DP83867_PHYCTRL); 664 if (val < 0) 665 return val; 666 667 /* The code below checks if "port mirroring" N/A MODE4 has been 668 * enabled during power on bootstrap. 669 * 670 * Such N/A mode enabled by mistake can put PHY IC in some 671 * internal testing mode and disable RGMII transmission. 672 * 673 * In this particular case one needs to check STRAP_STS1 674 * register's bit 11 (marked as RESERVED). 675 */ 676 677 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 678 if (bs & DP83867_STRAP_STS1_RESERVED) 679 val &= ~DP83867_PHYCR_RESERVED_MASK; 680 681 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 682 if (ret) 683 return ret; 684 685 /* If rgmii mode with no internal delay is selected, we do NOT use 686 * aligned mode as one might expect. Instead we use the PHY's default 687 * based on pin strapping. And the "mode 0" default is to *use* 688 * internal delay with a value of 7 (2.00 ns). 689 * 690 * Set up RGMII delays 691 */ 692 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 693 694 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 695 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 696 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 697 698 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 699 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 700 701 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 702 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 703 704 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 705 706 delay = 0; 707 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 708 delay |= dp83867->rx_id_delay; 709 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 710 delay |= dp83867->tx_id_delay << 711 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 712 713 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 714 delay); 715 } 716 717 /* If specified, set io impedance */ 718 if (dp83867->io_impedance >= 0) 719 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 720 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 721 dp83867->io_impedance); 722 723 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 724 /* For support SPEED_10 in SGMII mode 725 * DP83867_10M_SGMII_RATE_ADAPT bit 726 * has to be cleared by software. That 727 * does not affect SPEED_100 and 728 * SPEED_1000. 729 */ 730 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 731 DP83867_10M_SGMII_CFG, 732 DP83867_10M_SGMII_RATE_ADAPT_MASK, 733 0); 734 if (ret) 735 return ret; 736 737 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 738 * are 01). That is not enough to finalize autoneg on some 739 * devices. Increase this timer duration to maximum 16ms. 740 */ 741 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 742 DP83867_CFG4, 743 DP83867_CFG4_SGMII_ANEG_MASK, 744 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 745 746 if (ret) 747 return ret; 748 749 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 750 /* SGMII type is set to 4-wire mode by default. 751 * If we place appropriate property in dts (see above) 752 * switch on 6-wire mode. 753 */ 754 if (dp83867->sgmii_ref_clk_en) 755 val |= DP83867_SGMII_TYPE; 756 else 757 val &= ~DP83867_SGMII_TYPE; 758 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 759 } 760 761 val = phy_read(phydev, DP83867_CFG3); 762 /* Enable Interrupt output INT_OE in CFG3 register */ 763 if (phy_interrupt_is_valid(phydev)) 764 val |= DP83867_CFG3_INT_OE; 765 766 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 767 phy_write(phydev, DP83867_CFG3, val); 768 769 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 770 dp83867_config_port_mirroring(phydev); 771 772 /* Clock output selection if muxing property is set */ 773 if (dp83867->set_clk_output) { 774 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 775 776 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 777 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 778 } else { 779 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 780 val = dp83867->clk_output_sel << 781 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 782 } 783 784 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 785 mask, val); 786 } 787 788 return 0; 789 } 790 791 static int dp83867_phy_reset(struct phy_device *phydev) 792 { 793 int err; 794 795 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 796 if (err < 0) 797 return err; 798 799 usleep_range(10, 20); 800 801 /* After reset FORCE_LINK_GOOD bit is set. Although the 802 * default value should be unset. Disable FORCE_LINK_GOOD 803 * for the phy to work properly. 804 */ 805 return phy_modify(phydev, MII_DP83867_PHYCTRL, 806 DP83867_PHYCR_FORCE_LINK_GOOD, 0); 807 } 808 809 static struct phy_driver dp83867_driver[] = { 810 { 811 .phy_id = DP83867_PHY_ID, 812 .phy_id_mask = 0xfffffff0, 813 .name = "TI DP83867", 814 /* PHY_GBIT_FEATURES */ 815 816 .probe = dp83867_probe, 817 .config_init = dp83867_config_init, 818 .soft_reset = dp83867_phy_reset, 819 820 .read_status = dp83867_read_status, 821 .get_tunable = dp83867_get_tunable, 822 .set_tunable = dp83867_set_tunable, 823 824 .get_wol = dp83867_get_wol, 825 .set_wol = dp83867_set_wol, 826 827 /* IRQ related */ 828 .ack_interrupt = dp83867_ack_interrupt, 829 .config_intr = dp83867_config_intr, 830 831 .suspend = genphy_suspend, 832 .resume = genphy_resume, 833 }, 834 }; 835 module_phy_driver(dp83867_driver); 836 837 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 838 { DP83867_PHY_ID, 0xfffffff0 }, 839 { } 840 }; 841 842 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 843 844 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 845 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 846 MODULE_LICENSE("GPL v2"); 847