1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DP83867 PHY 4 * 5 * Copyright (C) 2015 Texas Instruments Inc. 6 */ 7 8 #include <linux/ethtool.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/delay.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 18 #include <dt-bindings/net/ti-dp83867.h> 19 20 #define DP83867_PHY_ID 0x2000a231 21 #define DP83867_DEVADDR 0x1f 22 23 #define MII_DP83867_PHYCTRL 0x10 24 #define MII_DP83867_MICR 0x12 25 #define MII_DP83867_ISR 0x13 26 #define DP83867_CFG2 0x14 27 #define DP83867_CFG3 0x1e 28 #define DP83867_CTRL 0x1f 29 30 /* Extended Registers */ 31 #define DP83867_CFG4 0x0031 32 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6)) 33 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5) 34 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5) 35 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5) 36 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5) 37 38 #define DP83867_RGMIICTL 0x0032 39 #define DP83867_STRAP_STS1 0x006E 40 #define DP83867_STRAP_STS2 0x006f 41 #define DP83867_RGMIIDCTL 0x0086 42 #define DP83867_RXFCFG 0x0134 43 #define DP83867_RXFPMD1 0x0136 44 #define DP83867_RXFPMD2 0x0137 45 #define DP83867_RXFPMD3 0x0138 46 #define DP83867_RXFSOP1 0x0139 47 #define DP83867_RXFSOP2 0x013A 48 #define DP83867_RXFSOP3 0x013B 49 #define DP83867_IO_MUX_CFG 0x0170 50 #define DP83867_SGMIICTL 0x00D3 51 #define DP83867_10M_SGMII_CFG 0x016F 52 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7) 53 54 #define DP83867_SW_RESET BIT(15) 55 #define DP83867_SW_RESTART BIT(14) 56 57 /* MICR Interrupt bits */ 58 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 59 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 60 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 61 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 62 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 63 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 64 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 65 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 66 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 67 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 68 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 69 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 70 71 /* RGMIICTL bits */ 72 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 73 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 74 75 /* SGMIICTL bits */ 76 #define DP83867_SGMII_TYPE BIT(14) 77 78 /* RXFCFG bits*/ 79 #define DP83867_WOL_MAGIC_EN BIT(0) 80 #define DP83867_WOL_BCAST_EN BIT(2) 81 #define DP83867_WOL_UCAST_EN BIT(4) 82 #define DP83867_WOL_SEC_EN BIT(5) 83 #define DP83867_WOL_ENH_MAC BIT(7) 84 85 /* STRAP_STS1 bits */ 86 #define DP83867_STRAP_STS1_RESERVED BIT(11) 87 88 /* STRAP_STS2 bits */ 89 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4) 90 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4 91 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0) 92 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0 93 #define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2) 94 95 /* PHY CTRL bits */ 96 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14 97 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12 98 #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 99 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 101 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 102 103 /* RGMIIDCTL bits */ 104 #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf 105 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 106 #define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1) 107 #define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf 108 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0 109 #define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1) 110 111 112 /* IO_MUX_CFG bits */ 113 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f 114 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 115 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 116 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 117 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 118 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 119 120 /* CFG3 bits */ 121 #define DP83867_CFG3_INT_OE BIT(7) 122 #define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9) 123 124 /* CFG4 bits */ 125 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 126 127 enum { 128 DP83867_PORT_MIRROING_KEEP, 129 DP83867_PORT_MIRROING_EN, 130 DP83867_PORT_MIRROING_DIS, 131 }; 132 133 struct dp83867_private { 134 u32 rx_id_delay; 135 u32 tx_id_delay; 136 u32 tx_fifo_depth; 137 u32 rx_fifo_depth; 138 int io_impedance; 139 int port_mirroring; 140 bool rxctrl_strap_quirk; 141 bool set_clk_output; 142 u32 clk_output_sel; 143 bool sgmii_ref_clk_en; 144 }; 145 146 static int dp83867_ack_interrupt(struct phy_device *phydev) 147 { 148 int err = phy_read(phydev, MII_DP83867_ISR); 149 150 if (err < 0) 151 return err; 152 153 return 0; 154 } 155 156 static int dp83867_set_wol(struct phy_device *phydev, 157 struct ethtool_wolinfo *wol) 158 { 159 struct net_device *ndev = phydev->attached_dev; 160 u16 val_rxcfg, val_micr; 161 u8 *mac; 162 163 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 164 val_micr = phy_read(phydev, MII_DP83867_MICR); 165 166 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 167 WAKE_BCAST)) { 168 val_rxcfg |= DP83867_WOL_ENH_MAC; 169 val_micr |= MII_DP83867_MICR_WOL_INT_EN; 170 171 if (wol->wolopts & WAKE_MAGIC) { 172 mac = (u8 *)ndev->dev_addr; 173 174 if (!is_valid_ether_addr(mac)) 175 return -EINVAL; 176 177 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, 178 (mac[1] << 8 | mac[0])); 179 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, 180 (mac[3] << 8 | mac[2])); 181 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, 182 (mac[5] << 8 | mac[4])); 183 184 val_rxcfg |= DP83867_WOL_MAGIC_EN; 185 } else { 186 val_rxcfg &= ~DP83867_WOL_MAGIC_EN; 187 } 188 189 if (wol->wolopts & WAKE_MAGICSECURE) { 190 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 191 (wol->sopass[1] << 8) | wol->sopass[0]); 192 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 193 (wol->sopass[3] << 8) | wol->sopass[2]); 194 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, 195 (wol->sopass[5] << 8) | wol->sopass[4]); 196 197 val_rxcfg |= DP83867_WOL_SEC_EN; 198 } else { 199 val_rxcfg &= ~DP83867_WOL_SEC_EN; 200 } 201 202 if (wol->wolopts & WAKE_UCAST) 203 val_rxcfg |= DP83867_WOL_UCAST_EN; 204 else 205 val_rxcfg &= ~DP83867_WOL_UCAST_EN; 206 207 if (wol->wolopts & WAKE_BCAST) 208 val_rxcfg |= DP83867_WOL_BCAST_EN; 209 else 210 val_rxcfg &= ~DP83867_WOL_BCAST_EN; 211 } else { 212 val_rxcfg &= ~DP83867_WOL_ENH_MAC; 213 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN; 214 } 215 216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); 217 phy_write(phydev, MII_DP83867_MICR, val_micr); 218 219 return 0; 220 } 221 222 static void dp83867_get_wol(struct phy_device *phydev, 223 struct ethtool_wolinfo *wol) 224 { 225 u16 value, sopass_val; 226 227 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 228 WAKE_MAGICSECURE); 229 wol->wolopts = 0; 230 231 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG); 232 233 if (value & DP83867_WOL_UCAST_EN) 234 wol->wolopts |= WAKE_UCAST; 235 236 if (value & DP83867_WOL_BCAST_EN) 237 wol->wolopts |= WAKE_BCAST; 238 239 if (value & DP83867_WOL_MAGIC_EN) 240 wol->wolopts |= WAKE_MAGIC; 241 242 if (value & DP83867_WOL_SEC_EN) { 243 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 244 DP83867_RXFSOP1); 245 wol->sopass[0] = (sopass_val & 0xff); 246 wol->sopass[1] = (sopass_val >> 8); 247 248 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 249 DP83867_RXFSOP2); 250 wol->sopass[2] = (sopass_val & 0xff); 251 wol->sopass[3] = (sopass_val >> 8); 252 253 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR, 254 DP83867_RXFSOP3); 255 wol->sopass[4] = (sopass_val & 0xff); 256 wol->sopass[5] = (sopass_val >> 8); 257 258 wol->wolopts |= WAKE_MAGICSECURE; 259 } 260 261 if (!(value & DP83867_WOL_ENH_MAC)) 262 wol->wolopts = 0; 263 } 264 265 static int dp83867_config_intr(struct phy_device *phydev) 266 { 267 int micr_status; 268 269 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 270 micr_status = phy_read(phydev, MII_DP83867_MICR); 271 if (micr_status < 0) 272 return micr_status; 273 274 micr_status |= 275 (MII_DP83867_MICR_AN_ERR_INT_EN | 276 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 277 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 278 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 279 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 280 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 281 282 return phy_write(phydev, MII_DP83867_MICR, micr_status); 283 } 284 285 micr_status = 0x0; 286 return phy_write(phydev, MII_DP83867_MICR, micr_status); 287 } 288 289 static int dp83867_config_port_mirroring(struct phy_device *phydev) 290 { 291 struct dp83867_private *dp83867 = 292 (struct dp83867_private *)phydev->priv; 293 294 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 295 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 296 DP83867_CFG4_PORT_MIRROR_EN); 297 else 298 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 299 DP83867_CFG4_PORT_MIRROR_EN); 300 return 0; 301 } 302 303 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev) 304 { 305 struct dp83867_private *dp83867 = phydev->priv; 306 307 /* Existing behavior was to use default pin strapping delay in rgmii 308 * mode, but rgmii should have meant no delay. Warn existing users. 309 */ 310 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { 311 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, 312 DP83867_STRAP_STS2); 313 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >> 314 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT; 315 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >> 316 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT; 317 318 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE || 319 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE) 320 phydev_warn(phydev, 321 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" 322 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", 323 txskew, rxskew); 324 } 325 326 /* RX delay *must* be specified if internal delay of RX is used. */ 327 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 328 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && 329 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { 330 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); 331 return -EINVAL; 332 } 333 334 /* TX delay *must* be specified if internal delay of TX is used. */ 335 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 336 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && 337 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { 338 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); 339 return -EINVAL; 340 } 341 342 return 0; 343 } 344 345 #ifdef CONFIG_OF_MDIO 346 static int dp83867_of_init(struct phy_device *phydev) 347 { 348 struct dp83867_private *dp83867 = phydev->priv; 349 struct device *dev = &phydev->mdio.dev; 350 struct device_node *of_node = dev->of_node; 351 int ret; 352 353 if (!of_node) 354 return -ENODEV; 355 356 /* Optional configuration */ 357 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 358 &dp83867->clk_output_sel); 359 /* If not set, keep default */ 360 if (!ret) { 361 dp83867->set_clk_output = true; 362 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 363 * DP83867_CLK_O_SEL_OFF. 364 */ 365 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 366 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 367 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 368 dp83867->clk_output_sel); 369 return -EINVAL; 370 } 371 } 372 373 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 374 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 375 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 376 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 377 else 378 dp83867->io_impedance = -1; /* leave at default */ 379 380 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 381 "ti,dp83867-rxctrl-strap-quirk"); 382 383 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, 384 "ti,sgmii-ref-clock-output-enable"); 385 386 387 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; 388 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 389 &dp83867->rx_id_delay); 390 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { 391 phydev_err(phydev, 392 "ti,rx-internal-delay value of %u out of range\n", 393 dp83867->rx_id_delay); 394 return -EINVAL; 395 } 396 397 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; 398 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 399 &dp83867->tx_id_delay); 400 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { 401 phydev_err(phydev, 402 "ti,tx-internal-delay value of %u out of range\n", 403 dp83867->tx_id_delay); 404 return -EINVAL; 405 } 406 407 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 408 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 409 410 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 411 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 412 413 ret = of_property_read_u32(of_node, "ti,fifo-depth", 414 &dp83867->tx_fifo_depth); 415 if (ret) { 416 ret = of_property_read_u32(of_node, "tx-fifo-depth", 417 &dp83867->tx_fifo_depth); 418 if (ret) 419 dp83867->tx_fifo_depth = 420 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 421 } 422 423 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 424 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", 425 dp83867->tx_fifo_depth); 426 return -EINVAL; 427 } 428 429 ret = of_property_read_u32(of_node, "rx-fifo-depth", 430 &dp83867->rx_fifo_depth); 431 if (ret) 432 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; 433 434 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { 435 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", 436 dp83867->rx_fifo_depth); 437 return -EINVAL; 438 } 439 440 return 0; 441 } 442 #else 443 static int dp83867_of_init(struct phy_device *phydev) 444 { 445 return 0; 446 } 447 #endif /* CONFIG_OF_MDIO */ 448 449 static int dp83867_probe(struct phy_device *phydev) 450 { 451 struct dp83867_private *dp83867; 452 453 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 454 GFP_KERNEL); 455 if (!dp83867) 456 return -ENOMEM; 457 458 phydev->priv = dp83867; 459 460 return dp83867_of_init(phydev); 461 } 462 463 static int dp83867_config_init(struct phy_device *phydev) 464 { 465 struct dp83867_private *dp83867 = phydev->priv; 466 int ret, val, bs; 467 u16 delay; 468 469 ret = dp83867_verify_rgmii_cfg(phydev); 470 if (ret) 471 return ret; 472 473 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 474 if (dp83867->rxctrl_strap_quirk) 475 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 476 BIT(7)); 477 478 if (phy_interface_is_rgmii(phydev) || 479 phydev->interface == PHY_INTERFACE_MODE_SGMII) { 480 val = phy_read(phydev, MII_DP83867_PHYCTRL); 481 if (val < 0) 482 return val; 483 484 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; 485 val |= (dp83867->tx_fifo_depth << 486 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); 487 488 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 489 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; 490 val |= (dp83867->rx_fifo_depth << 491 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); 492 } 493 494 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 495 if (ret) 496 return ret; 497 } 498 499 if (phy_interface_is_rgmii(phydev)) { 500 val = phy_read(phydev, MII_DP83867_PHYCTRL); 501 if (val < 0) 502 return val; 503 504 /* The code below checks if "port mirroring" N/A MODE4 has been 505 * enabled during power on bootstrap. 506 * 507 * Such N/A mode enabled by mistake can put PHY IC in some 508 * internal testing mode and disable RGMII transmission. 509 * 510 * In this particular case one needs to check STRAP_STS1 511 * register's bit 11 (marked as RESERVED). 512 */ 513 514 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 515 if (bs & DP83867_STRAP_STS1_RESERVED) 516 val &= ~DP83867_PHYCR_RESERVED_MASK; 517 518 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 519 if (ret) 520 return ret; 521 522 /* If rgmii mode with no internal delay is selected, we do NOT use 523 * aligned mode as one might expect. Instead we use the PHY's default 524 * based on pin strapping. And the "mode 0" default is to *use* 525 * internal delay with a value of 7 (2.00 ns). 526 * 527 * Set up RGMII delays 528 */ 529 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 530 531 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 532 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 533 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 534 535 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 536 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 537 538 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 539 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 540 541 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 542 543 delay = 0; 544 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) 545 delay |= dp83867->rx_id_delay; 546 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) 547 delay |= dp83867->tx_id_delay << 548 DP83867_RGMII_TX_CLK_DELAY_SHIFT; 549 550 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 551 delay); 552 } 553 554 /* If specified, set io impedance */ 555 if (dp83867->io_impedance >= 0) 556 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 557 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK, 558 dp83867->io_impedance); 559 560 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 561 /* For support SPEED_10 in SGMII mode 562 * DP83867_10M_SGMII_RATE_ADAPT bit 563 * has to be cleared by software. That 564 * does not affect SPEED_100 and 565 * SPEED_1000. 566 */ 567 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 568 DP83867_10M_SGMII_CFG, 569 DP83867_10M_SGMII_RATE_ADAPT_MASK, 570 0); 571 if (ret) 572 return ret; 573 574 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 575 * are 01). That is not enough to finalize autoneg on some 576 * devices. Increase this timer duration to maximum 16ms. 577 */ 578 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, 579 DP83867_CFG4, 580 DP83867_CFG4_SGMII_ANEG_MASK, 581 DP83867_CFG4_SGMII_ANEG_TIMER_16MS); 582 583 if (ret) 584 return ret; 585 586 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); 587 /* SGMII type is set to 4-wire mode by default. 588 * If we place appropriate property in dts (see above) 589 * switch on 6-wire mode. 590 */ 591 if (dp83867->sgmii_ref_clk_en) 592 val |= DP83867_SGMII_TYPE; 593 else 594 val &= ~DP83867_SGMII_TYPE; 595 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); 596 } 597 598 val = phy_read(phydev, DP83867_CFG3); 599 /* Enable Interrupt output INT_OE in CFG3 register */ 600 if (phy_interrupt_is_valid(phydev)) 601 val |= DP83867_CFG3_INT_OE; 602 603 val |= DP83867_CFG3_ROBUST_AUTO_MDIX; 604 phy_write(phydev, DP83867_CFG3, val); 605 606 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 607 dp83867_config_port_mirroring(phydev); 608 609 /* Clock output selection if muxing property is set */ 610 if (dp83867->set_clk_output) { 611 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 612 613 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 614 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 615 } else { 616 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 617 val = dp83867->clk_output_sel << 618 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 619 } 620 621 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 622 mask, val); 623 } 624 625 return 0; 626 } 627 628 static int dp83867_phy_reset(struct phy_device *phydev) 629 { 630 int err; 631 632 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 633 if (err < 0) 634 return err; 635 636 usleep_range(10, 20); 637 638 return 0; 639 } 640 641 static struct phy_driver dp83867_driver[] = { 642 { 643 .phy_id = DP83867_PHY_ID, 644 .phy_id_mask = 0xfffffff0, 645 .name = "TI DP83867", 646 /* PHY_GBIT_FEATURES */ 647 648 .probe = dp83867_probe, 649 .config_init = dp83867_config_init, 650 .soft_reset = dp83867_phy_reset, 651 652 .get_wol = dp83867_get_wol, 653 .set_wol = dp83867_set_wol, 654 655 /* IRQ related */ 656 .ack_interrupt = dp83867_ack_interrupt, 657 .config_intr = dp83867_config_intr, 658 659 .suspend = genphy_suspend, 660 .resume = genphy_resume, 661 }, 662 }; 663 module_phy_driver(dp83867_driver); 664 665 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 666 { DP83867_PHY_ID, 0xfffffff0 }, 667 { } 668 }; 669 670 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 671 672 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 673 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 674 MODULE_LICENSE("GPL v2"); 675