1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 #include <linux/bitfield.h> 16 17 #define DP83822_PHY_ID 0x2000a240 18 #define DP83825S_PHY_ID 0x2000a140 19 #define DP83825I_PHY_ID 0x2000a150 20 #define DP83825CM_PHY_ID 0x2000a160 21 #define DP83825CS_PHY_ID 0x2000a170 22 #define DP83826C_PHY_ID 0x2000a130 23 #define DP83826NC_PHY_ID 0x2000a110 24 25 #define MII_DP83822_CTRL_2 0x0a 26 #define MII_DP83822_PHYSTS 0x10 27 #define MII_DP83822_PHYSCR 0x11 28 #define MII_DP83822_MISR1 0x12 29 #define MII_DP83822_MISR2 0x13 30 #define MII_DP83822_FCSCR 0x14 31 #define MII_DP83822_RCSR 0x17 32 #define MII_DP83822_RESET_CTRL 0x1f 33 #define MII_DP83822_IOCTRL2 0x463 34 #define MII_DP83822_GENCFG 0x465 35 #define MII_DP83822_SOR1 0x467 36 37 /* DP83826 specific registers */ 38 #define MII_DP83826_VOD_CFG1 0x30b 39 #define MII_DP83826_VOD_CFG2 0x30c 40 41 /* GENCFG */ 42 #define DP83822_SIG_DET_LOW BIT(0) 43 44 /* Control Register 2 bits */ 45 #define DP83822_FX_ENABLE BIT(14) 46 47 #define DP83822_SW_RESET BIT(15) 48 #define DP83822_DIG_RESTART BIT(14) 49 50 /* PHY STS bits */ 51 #define DP83822_PHYSTS_DUPLEX BIT(2) 52 #define DP83822_PHYSTS_10 BIT(1) 53 #define DP83822_PHYSTS_LINK BIT(0) 54 55 /* PHYSCR Register Fields */ 56 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 57 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 58 59 /* MISR1 bits */ 60 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 61 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 62 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 63 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 64 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 65 #define DP83822_LINK_STAT_INT_EN BIT(5) 66 #define DP83822_ENERGY_DET_INT_EN BIT(6) 67 #define DP83822_LINK_QUAL_INT_EN BIT(7) 68 69 /* MISR2 bits */ 70 #define DP83822_JABBER_DET_INT_EN BIT(0) 71 #define DP83822_WOL_PKT_INT_EN BIT(1) 72 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 73 #define DP83822_MDI_XOVER_INT_EN BIT(3) 74 #define DP83822_LB_FIFO_INT_EN BIT(4) 75 #define DP83822_PAGE_RX_INT_EN BIT(5) 76 #define DP83822_ANEG_ERR_INT_EN BIT(6) 77 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 78 79 /* INT_STAT1 bits */ 80 #define DP83822_WOL_INT_EN BIT(4) 81 #define DP83822_WOL_INT_STAT BIT(12) 82 83 #define MII_DP83822_RXSOP1 0x04a5 84 #define MII_DP83822_RXSOP2 0x04a6 85 #define MII_DP83822_RXSOP3 0x04a7 86 87 /* WoL Registers */ 88 #define MII_DP83822_WOL_CFG 0x04a0 89 #define MII_DP83822_WOL_STAT 0x04a1 90 #define MII_DP83822_WOL_DA1 0x04a2 91 #define MII_DP83822_WOL_DA2 0x04a3 92 #define MII_DP83822_WOL_DA3 0x04a4 93 94 /* WoL bits */ 95 #define DP83822_WOL_MAGIC_EN BIT(0) 96 #define DP83822_WOL_SECURE_ON BIT(5) 97 #define DP83822_WOL_EN BIT(7) 98 #define DP83822_WOL_INDICATION_SEL BIT(8) 99 #define DP83822_WOL_CLR_INDICATION BIT(11) 100 101 /* RCSR bits */ 102 #define DP83822_RMII_MODE_EN BIT(5) 103 #define DP83822_RMII_MODE_SEL BIT(7) 104 #define DP83822_RGMII_MODE_EN BIT(9) 105 #define DP83822_RX_CLK_SHIFT BIT(12) 106 #define DP83822_TX_CLK_SHIFT BIT(11) 107 108 /* IOCTRL2 bits */ 109 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4) 110 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0) 111 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0) 112 113 #define DP83822_CLK_SRC_MAC_IF 0x0 114 #define DP83822_CLK_SRC_XI 0x1 115 #define DP83822_CLK_SRC_INT_REF 0x2 116 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4 117 #define DP83822_CLK_SRC_FREE_RUNNING 0x6 118 #define DP83822_CLK_SRC_RECOVERED 0x7 119 120 /* SOR1 mode */ 121 #define DP83822_STRAP_MODE1 0 122 #define DP83822_STRAP_MODE2 BIT(0) 123 #define DP83822_STRAP_MODE3 BIT(1) 124 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 125 126 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 127 #define DP83822_COL_SHIFT 10 128 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 129 #define DP83822_RX_ER_SHIFT 8 130 131 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 132 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 133 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 134 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 135 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 136 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 137 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 138 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 139 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 140 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 141 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 142 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 143 144 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 145 ADVERTISED_FIBRE | \ 146 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 147 148 struct dp83822_private { 149 bool fx_signal_det_low; 150 int fx_enabled; 151 u16 fx_sd_enable; 152 u8 cfg_dac_minus; 153 u8 cfg_dac_plus; 154 struct ethtool_wolinfo wol; 155 bool set_gpio2_clk_out; 156 u32 gpio2_clk_out; 157 }; 158 159 static int dp83822_config_wol(struct phy_device *phydev, 160 struct ethtool_wolinfo *wol) 161 { 162 struct net_device *ndev = phydev->attached_dev; 163 u16 value; 164 const u8 *mac; 165 166 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 167 mac = (const u8 *)ndev->dev_addr; 168 169 if (!is_valid_ether_addr(mac)) 170 return -EINVAL; 171 172 /* MAC addresses start with byte 5, but stored in mac[0]. 173 * 822 PHYs store bytes 4|5, 2|3, 0|1 174 */ 175 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, 176 (mac[1] << 8) | mac[0]); 177 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, 178 (mac[3] << 8) | mac[2]); 179 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, 180 (mac[5] << 8) | mac[4]); 181 182 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, 183 MII_DP83822_WOL_CFG); 184 if (wol->wolopts & WAKE_MAGIC) 185 value |= DP83822_WOL_MAGIC_EN; 186 else 187 value &= ~DP83822_WOL_MAGIC_EN; 188 189 if (wol->wolopts & WAKE_MAGICSECURE) { 190 phy_write_mmd(phydev, MDIO_MMD_VEND2, 191 MII_DP83822_RXSOP1, 192 (wol->sopass[1] << 8) | wol->sopass[0]); 193 phy_write_mmd(phydev, MDIO_MMD_VEND2, 194 MII_DP83822_RXSOP2, 195 (wol->sopass[3] << 8) | wol->sopass[2]); 196 phy_write_mmd(phydev, MDIO_MMD_VEND2, 197 MII_DP83822_RXSOP3, 198 (wol->sopass[5] << 8) | wol->sopass[4]); 199 value |= DP83822_WOL_SECURE_ON; 200 } else { 201 value &= ~DP83822_WOL_SECURE_ON; 202 } 203 204 /* Clear any pending WoL interrupt */ 205 phy_read(phydev, MII_DP83822_MISR2); 206 207 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 208 DP83822_WOL_CLR_INDICATION; 209 210 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 211 MII_DP83822_WOL_CFG, value); 212 } else { 213 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 214 MII_DP83822_WOL_CFG, 215 DP83822_WOL_EN | 216 DP83822_WOL_MAGIC_EN | 217 DP83822_WOL_SECURE_ON); 218 } 219 } 220 221 static int dp83822_set_wol(struct phy_device *phydev, 222 struct ethtool_wolinfo *wol) 223 { 224 struct dp83822_private *dp83822 = phydev->priv; 225 int ret; 226 227 ret = dp83822_config_wol(phydev, wol); 228 if (!ret) 229 memcpy(&dp83822->wol, wol, sizeof(*wol)); 230 return ret; 231 } 232 233 static void dp83822_get_wol(struct phy_device *phydev, 234 struct ethtool_wolinfo *wol) 235 { 236 int value; 237 u16 sopass_val; 238 239 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 240 wol->wolopts = 0; 241 242 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 243 244 if (value & DP83822_WOL_MAGIC_EN) 245 wol->wolopts |= WAKE_MAGIC; 246 247 if (value & DP83822_WOL_SECURE_ON) { 248 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 249 MII_DP83822_RXSOP1); 250 wol->sopass[0] = (sopass_val & 0xff); 251 wol->sopass[1] = (sopass_val >> 8); 252 253 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 254 MII_DP83822_RXSOP2); 255 wol->sopass[2] = (sopass_val & 0xff); 256 wol->sopass[3] = (sopass_val >> 8); 257 258 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 259 MII_DP83822_RXSOP3); 260 wol->sopass[4] = (sopass_val & 0xff); 261 wol->sopass[5] = (sopass_val >> 8); 262 263 wol->wolopts |= WAKE_MAGICSECURE; 264 } 265 266 /* WoL is not enabled so set wolopts to 0 */ 267 if (!(value & DP83822_WOL_EN)) 268 wol->wolopts = 0; 269 } 270 271 static int dp83822_config_intr(struct phy_device *phydev) 272 { 273 struct dp83822_private *dp83822 = phydev->priv; 274 int misr_status; 275 int physcr_status; 276 int err; 277 278 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 279 misr_status = phy_read(phydev, MII_DP83822_MISR1); 280 if (misr_status < 0) 281 return misr_status; 282 283 misr_status |= (DP83822_LINK_STAT_INT_EN | 284 DP83822_ENERGY_DET_INT_EN | 285 DP83822_LINK_QUAL_INT_EN); 286 287 if (!dp83822->fx_enabled) 288 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 289 DP83822_DUP_MODE_CHANGE_INT_EN | 290 DP83822_SPEED_CHANGED_INT_EN; 291 292 293 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 294 if (err < 0) 295 return err; 296 297 misr_status = phy_read(phydev, MII_DP83822_MISR2); 298 if (misr_status < 0) 299 return misr_status; 300 301 misr_status |= (DP83822_JABBER_DET_INT_EN | 302 DP83822_SLEEP_MODE_INT_EN | 303 DP83822_LB_FIFO_INT_EN | 304 DP83822_PAGE_RX_INT_EN | 305 DP83822_EEE_ERROR_CHANGE_INT_EN); 306 307 if (!dp83822->fx_enabled) 308 misr_status |= DP83822_ANEG_ERR_INT_EN | 309 DP83822_WOL_PKT_INT_EN; 310 311 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 312 if (err < 0) 313 return err; 314 315 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 316 if (physcr_status < 0) 317 return physcr_status; 318 319 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 320 321 } else { 322 err = phy_write(phydev, MII_DP83822_MISR1, 0); 323 if (err < 0) 324 return err; 325 326 err = phy_write(phydev, MII_DP83822_MISR2, 0); 327 if (err < 0) 328 return err; 329 330 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 331 if (physcr_status < 0) 332 return physcr_status; 333 334 physcr_status &= ~DP83822_PHYSCR_INTEN; 335 } 336 337 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 338 } 339 340 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 341 { 342 bool trigger_machine = false; 343 int irq_status; 344 345 /* The MISR1 and MISR2 registers are holding the interrupt status in 346 * the upper half (15:8), while the lower half (7:0) is used for 347 * controlling the interrupt enable state of those individual interrupt 348 * sources. To determine the possible interrupt sources, just read the 349 * MISR* register and use it directly to know which interrupts have 350 * been enabled previously or not. 351 */ 352 irq_status = phy_read(phydev, MII_DP83822_MISR1); 353 if (irq_status < 0) { 354 phy_error(phydev); 355 return IRQ_NONE; 356 } 357 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 358 trigger_machine = true; 359 360 irq_status = phy_read(phydev, MII_DP83822_MISR2); 361 if (irq_status < 0) { 362 phy_error(phydev); 363 return IRQ_NONE; 364 } 365 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 366 trigger_machine = true; 367 368 if (!trigger_machine) 369 return IRQ_NONE; 370 371 phy_trigger_machine(phydev); 372 373 return IRQ_HANDLED; 374 } 375 376 static int dp83822_read_status(struct phy_device *phydev) 377 { 378 struct dp83822_private *dp83822 = phydev->priv; 379 int status = phy_read(phydev, MII_DP83822_PHYSTS); 380 int ctrl2; 381 int ret; 382 383 if (dp83822->fx_enabled) { 384 if (status & DP83822_PHYSTS_LINK) { 385 phydev->speed = SPEED_UNKNOWN; 386 phydev->duplex = DUPLEX_UNKNOWN; 387 } else { 388 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 389 if (ctrl2 < 0) 390 return ctrl2; 391 392 if (!(ctrl2 & DP83822_FX_ENABLE)) { 393 ret = phy_write(phydev, MII_DP83822_CTRL_2, 394 DP83822_FX_ENABLE | ctrl2); 395 if (ret < 0) 396 return ret; 397 } 398 } 399 } 400 401 ret = genphy_read_status(phydev); 402 if (ret) 403 return ret; 404 405 if (status < 0) 406 return status; 407 408 if (status & DP83822_PHYSTS_DUPLEX) 409 phydev->duplex = DUPLEX_FULL; 410 else 411 phydev->duplex = DUPLEX_HALF; 412 413 if (status & DP83822_PHYSTS_10) 414 phydev->speed = SPEED_10; 415 else 416 phydev->speed = SPEED_100; 417 418 return 0; 419 } 420 421 static int dp83822_config_init(struct phy_device *phydev) 422 { 423 struct dp83822_private *dp83822 = phydev->priv; 424 struct device *dev = &phydev->mdio.dev; 425 int rgmii_delay = 0; 426 s32 rx_int_delay; 427 s32 tx_int_delay; 428 int err = 0; 429 int bmcr; 430 431 if (dp83822->set_gpio2_clk_out) 432 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 433 DP83822_IOCTRL2_GPIO2_CTRL | 434 DP83822_IOCTRL2_GPIO2_CLK_SRC, 435 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 436 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) | 437 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC, 438 dp83822->gpio2_clk_out)); 439 440 if (phy_interface_is_rgmii(phydev)) { 441 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 442 true); 443 444 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ 445 if (rx_int_delay > 0) 446 rgmii_delay |= DP83822_RX_CLK_SHIFT; 447 448 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 449 false); 450 451 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ 452 if (tx_int_delay <= 0) 453 rgmii_delay |= DP83822_TX_CLK_SHIFT; 454 455 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 456 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); 457 if (err) 458 return err; 459 460 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 461 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 462 463 if (err) 464 return err; 465 } else { 466 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 467 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 468 469 if (err) 470 return err; 471 } 472 473 if (dp83822->fx_enabled) { 474 err = phy_modify(phydev, MII_DP83822_CTRL_2, 475 DP83822_FX_ENABLE, 1); 476 if (err < 0) 477 return err; 478 479 /* Only allow advertising what this PHY supports */ 480 linkmode_and(phydev->advertising, phydev->advertising, 481 phydev->supported); 482 483 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 484 phydev->supported); 485 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 486 phydev->advertising); 487 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 488 phydev->supported); 489 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 490 phydev->supported); 491 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 492 phydev->advertising); 493 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 494 phydev->advertising); 495 496 /* Auto neg is not supported in fiber mode */ 497 bmcr = phy_read(phydev, MII_BMCR); 498 if (bmcr < 0) 499 return bmcr; 500 501 if (bmcr & BMCR_ANENABLE) { 502 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 503 if (err < 0) 504 return err; 505 } 506 phydev->autoneg = AUTONEG_DISABLE; 507 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 508 phydev->supported); 509 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 510 phydev->advertising); 511 512 /* Setup fiber advertisement */ 513 err = phy_modify_changed(phydev, MII_ADVERTISE, 514 MII_DP83822_FIBER_ADVERTISE, 515 MII_DP83822_FIBER_ADVERTISE); 516 517 if (err < 0) 518 return err; 519 520 if (dp83822->fx_signal_det_low) { 521 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 522 MII_DP83822_GENCFG, 523 DP83822_SIG_DET_LOW); 524 if (err) 525 return err; 526 } 527 } 528 return dp83822_config_wol(phydev, &dp83822->wol); 529 } 530 531 static int dp8382x_config_rmii_mode(struct phy_device *phydev) 532 { 533 struct device *dev = &phydev->mdio.dev; 534 const char *of_val; 535 int ret; 536 537 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { 538 if (strcmp(of_val, "master") == 0) { 539 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 540 DP83822_RMII_MODE_SEL); 541 } else if (strcmp(of_val, "slave") == 0) { 542 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 543 DP83822_RMII_MODE_SEL); 544 } else { 545 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", 546 of_val); 547 ret = -EINVAL; 548 } 549 550 if (ret) 551 return ret; 552 } 553 554 return 0; 555 } 556 557 static int dp83826_config_init(struct phy_device *phydev) 558 { 559 struct dp83822_private *dp83822 = phydev->priv; 560 u16 val, mask; 561 int ret; 562 563 if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 564 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 565 DP83822_RMII_MODE_EN); 566 if (ret) 567 return ret; 568 569 ret = dp8382x_config_rmii_mode(phydev); 570 if (ret) 571 return ret; 572 } else { 573 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 574 DP83822_RMII_MODE_EN); 575 if (ret) 576 return ret; 577 } 578 579 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 580 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 581 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 582 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 583 dp83822->cfg_dac_minus)); 584 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 585 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val); 586 if (ret) 587 return ret; 588 589 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 590 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 591 dp83822->cfg_dac_minus)); 592 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 593 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 594 if (ret) 595 return ret; 596 } 597 598 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 599 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 600 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 601 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 602 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 603 if (ret) 604 return ret; 605 } 606 607 return dp83822_config_wol(phydev, &dp83822->wol); 608 } 609 610 static int dp83825_config_init(struct phy_device *phydev) 611 { 612 struct dp83822_private *dp83822 = phydev->priv; 613 int ret; 614 615 ret = dp8382x_config_rmii_mode(phydev); 616 if (ret) 617 return ret; 618 619 return dp83822_config_wol(phydev, &dp83822->wol); 620 } 621 622 static int dp83822_phy_reset(struct phy_device *phydev) 623 { 624 int err; 625 626 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 627 if (err < 0) 628 return err; 629 630 return phydev->drv->config_init(phydev); 631 } 632 633 #ifdef CONFIG_OF_MDIO 634 static int dp83822_of_init(struct phy_device *phydev) 635 { 636 struct dp83822_private *dp83822 = phydev->priv; 637 struct device *dev = &phydev->mdio.dev; 638 const char *of_val; 639 640 /* Signal detection for the PHY is only enabled if the FX_EN and the 641 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 642 * is strapped otherwise signal detection is disabled for the PHY. 643 */ 644 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 645 dp83822->fx_signal_det_low = device_property_present(dev, 646 "ti,link-loss-low"); 647 if (!dp83822->fx_enabled) 648 dp83822->fx_enabled = device_property_present(dev, 649 "ti,fiber-mode"); 650 651 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) { 652 if (strcmp(of_val, "mac-if") == 0) { 653 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF; 654 } else if (strcmp(of_val, "xi") == 0) { 655 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI; 656 } else if (strcmp(of_val, "int-ref") == 0) { 657 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF; 658 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) { 659 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF; 660 } else if (strcmp(of_val, "free-running") == 0) { 661 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING; 662 } else if (strcmp(of_val, "recovered") == 0) { 663 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED; 664 } else { 665 phydev_err(phydev, 666 "Invalid value for ti,gpio2-clk-out property (%s)\n", 667 of_val); 668 return -EINVAL; 669 } 670 671 dp83822->set_gpio2_clk_out = true; 672 } 673 674 return 0; 675 } 676 677 static int dp83826_to_dac_minus_one_regval(int percent) 678 { 679 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 680 681 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 682 } 683 684 static int dp83826_to_dac_plus_one_regval(int percent) 685 { 686 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 687 688 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 689 } 690 691 static void dp83826_of_init(struct phy_device *phydev) 692 { 693 struct dp83822_private *dp83822 = phydev->priv; 694 struct device *dev = &phydev->mdio.dev; 695 u32 val; 696 697 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 698 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 699 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 700 701 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 702 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 703 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 704 } 705 #else 706 static int dp83822_of_init(struct phy_device *phydev) 707 { 708 return 0; 709 } 710 711 static void dp83826_of_init(struct phy_device *phydev) 712 { 713 } 714 #endif /* CONFIG_OF_MDIO */ 715 716 static int dp83822_read_straps(struct phy_device *phydev) 717 { 718 struct dp83822_private *dp83822 = phydev->priv; 719 int fx_enabled, fx_sd_enable; 720 int val; 721 722 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1); 723 if (val < 0) 724 return val; 725 726 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 727 728 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 729 if (fx_enabled == DP83822_STRAP_MODE2 || 730 fx_enabled == DP83822_STRAP_MODE3) 731 dp83822->fx_enabled = 1; 732 733 if (dp83822->fx_enabled) { 734 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 735 if (fx_sd_enable == DP83822_STRAP_MODE3 || 736 fx_sd_enable == DP83822_STRAP_MODE4) 737 dp83822->fx_sd_enable = 1; 738 } 739 740 return 0; 741 } 742 743 static int dp8382x_probe(struct phy_device *phydev) 744 { 745 struct dp83822_private *dp83822; 746 747 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 748 GFP_KERNEL); 749 if (!dp83822) 750 return -ENOMEM; 751 752 phydev->priv = dp83822; 753 754 return 0; 755 } 756 757 static int dp83822_probe(struct phy_device *phydev) 758 { 759 struct dp83822_private *dp83822; 760 int ret; 761 762 ret = dp8382x_probe(phydev); 763 if (ret) 764 return ret; 765 766 dp83822 = phydev->priv; 767 768 ret = dp83822_read_straps(phydev); 769 if (ret) 770 return ret; 771 772 dp83822_of_init(phydev); 773 774 if (dp83822->fx_enabled) 775 phydev->port = PORT_FIBRE; 776 777 return 0; 778 } 779 780 static int dp83826_probe(struct phy_device *phydev) 781 { 782 int ret; 783 784 ret = dp8382x_probe(phydev); 785 if (ret) 786 return ret; 787 788 dp83826_of_init(phydev); 789 790 return 0; 791 } 792 793 static int dp83822_suspend(struct phy_device *phydev) 794 { 795 int value; 796 797 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 798 799 if (!(value & DP83822_WOL_EN)) 800 genphy_suspend(phydev); 801 802 return 0; 803 } 804 805 static int dp83822_resume(struct phy_device *phydev) 806 { 807 int value; 808 809 genphy_resume(phydev); 810 811 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 812 813 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | 814 DP83822_WOL_CLR_INDICATION); 815 816 return 0; 817 } 818 819 #define DP83822_PHY_DRIVER(_id, _name) \ 820 { \ 821 PHY_ID_MATCH_MODEL(_id), \ 822 .name = (_name), \ 823 /* PHY_BASIC_FEATURES */ \ 824 .probe = dp83822_probe, \ 825 .soft_reset = dp83822_phy_reset, \ 826 .config_init = dp83822_config_init, \ 827 .read_status = dp83822_read_status, \ 828 .get_wol = dp83822_get_wol, \ 829 .set_wol = dp83822_set_wol, \ 830 .config_intr = dp83822_config_intr, \ 831 .handle_interrupt = dp83822_handle_interrupt, \ 832 .suspend = dp83822_suspend, \ 833 .resume = dp83822_resume, \ 834 } 835 836 #define DP83825_PHY_DRIVER(_id, _name) \ 837 { \ 838 PHY_ID_MATCH_MODEL(_id), \ 839 .name = (_name), \ 840 /* PHY_BASIC_FEATURES */ \ 841 .probe = dp8382x_probe, \ 842 .soft_reset = dp83822_phy_reset, \ 843 .config_init = dp83825_config_init, \ 844 .get_wol = dp83822_get_wol, \ 845 .set_wol = dp83822_set_wol, \ 846 .config_intr = dp83822_config_intr, \ 847 .handle_interrupt = dp83822_handle_interrupt, \ 848 .suspend = dp83822_suspend, \ 849 .resume = dp83822_resume, \ 850 } 851 852 #define DP83826_PHY_DRIVER(_id, _name) \ 853 { \ 854 PHY_ID_MATCH_MODEL(_id), \ 855 .name = (_name), \ 856 /* PHY_BASIC_FEATURES */ \ 857 .probe = dp83826_probe, \ 858 .soft_reset = dp83822_phy_reset, \ 859 .config_init = dp83826_config_init, \ 860 .get_wol = dp83822_get_wol, \ 861 .set_wol = dp83822_set_wol, \ 862 .config_intr = dp83822_config_intr, \ 863 .handle_interrupt = dp83822_handle_interrupt, \ 864 .suspend = dp83822_suspend, \ 865 .resume = dp83822_resume, \ 866 } 867 868 static struct phy_driver dp83822_driver[] = { 869 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 870 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 871 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 872 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 873 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 874 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 875 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 876 }; 877 module_phy_driver(dp83822_driver); 878 879 static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 880 { DP83822_PHY_ID, 0xfffffff0 }, 881 { DP83825I_PHY_ID, 0xfffffff0 }, 882 { DP83826C_PHY_ID, 0xfffffff0 }, 883 { DP83826NC_PHY_ID, 0xfffffff0 }, 884 { DP83825S_PHY_ID, 0xfffffff0 }, 885 { DP83825CM_PHY_ID, 0xfffffff0 }, 886 { DP83825CS_PHY_ID, 0xfffffff0 }, 887 { }, 888 }; 889 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 890 891 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 892 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 893 MODULE_LICENSE("GPL v2"); 894