1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 #include <linux/bitfield.h> 16 17 #define DP83822_PHY_ID 0x2000a240 18 #define DP83825S_PHY_ID 0x2000a140 19 #define DP83825I_PHY_ID 0x2000a150 20 #define DP83825CM_PHY_ID 0x2000a160 21 #define DP83825CS_PHY_ID 0x2000a170 22 #define DP83826C_PHY_ID 0x2000a130 23 #define DP83826NC_PHY_ID 0x2000a110 24 25 #define DP83822_DEVADDR 0x1f 26 27 #define MII_DP83822_CTRL_2 0x0a 28 #define MII_DP83822_PHYSTS 0x10 29 #define MII_DP83822_PHYSCR 0x11 30 #define MII_DP83822_MISR1 0x12 31 #define MII_DP83822_MISR2 0x13 32 #define MII_DP83822_FCSCR 0x14 33 #define MII_DP83822_RCSR 0x17 34 #define MII_DP83822_RESET_CTRL 0x1f 35 #define MII_DP83822_GENCFG 0x465 36 #define MII_DP83822_SOR1 0x467 37 38 /* DP83826 specific registers */ 39 #define MII_DP83826_VOD_CFG1 0x30b 40 #define MII_DP83826_VOD_CFG2 0x30c 41 42 /* GENCFG */ 43 #define DP83822_SIG_DET_LOW BIT(0) 44 45 /* Control Register 2 bits */ 46 #define DP83822_FX_ENABLE BIT(14) 47 48 #define DP83822_HW_RESET BIT(15) 49 #define DP83822_SW_RESET BIT(14) 50 51 /* PHY STS bits */ 52 #define DP83822_PHYSTS_DUPLEX BIT(2) 53 #define DP83822_PHYSTS_10 BIT(1) 54 #define DP83822_PHYSTS_LINK BIT(0) 55 56 /* PHYSCR Register Fields */ 57 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 58 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 59 60 /* MISR1 bits */ 61 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 62 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 63 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 64 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 65 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 66 #define DP83822_LINK_STAT_INT_EN BIT(5) 67 #define DP83822_ENERGY_DET_INT_EN BIT(6) 68 #define DP83822_LINK_QUAL_INT_EN BIT(7) 69 70 /* MISR2 bits */ 71 #define DP83822_JABBER_DET_INT_EN BIT(0) 72 #define DP83822_WOL_PKT_INT_EN BIT(1) 73 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 74 #define DP83822_MDI_XOVER_INT_EN BIT(3) 75 #define DP83822_LB_FIFO_INT_EN BIT(4) 76 #define DP83822_PAGE_RX_INT_EN BIT(5) 77 #define DP83822_ANEG_ERR_INT_EN BIT(6) 78 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 79 80 /* INT_STAT1 bits */ 81 #define DP83822_WOL_INT_EN BIT(4) 82 #define DP83822_WOL_INT_STAT BIT(12) 83 84 #define MII_DP83822_RXSOP1 0x04a5 85 #define MII_DP83822_RXSOP2 0x04a6 86 #define MII_DP83822_RXSOP3 0x04a7 87 88 /* WoL Registers */ 89 #define MII_DP83822_WOL_CFG 0x04a0 90 #define MII_DP83822_WOL_STAT 0x04a1 91 #define MII_DP83822_WOL_DA1 0x04a2 92 #define MII_DP83822_WOL_DA2 0x04a3 93 #define MII_DP83822_WOL_DA3 0x04a4 94 95 /* WoL bits */ 96 #define DP83822_WOL_MAGIC_EN BIT(0) 97 #define DP83822_WOL_SECURE_ON BIT(5) 98 #define DP83822_WOL_EN BIT(7) 99 #define DP83822_WOL_INDICATION_SEL BIT(8) 100 #define DP83822_WOL_CLR_INDICATION BIT(11) 101 102 /* RCSR bits */ 103 #define DP83822_RMII_MODE_EN BIT(5) 104 #define DP83822_RMII_MODE_SEL BIT(7) 105 #define DP83822_RGMII_MODE_EN BIT(9) 106 #define DP83822_RX_CLK_SHIFT BIT(12) 107 #define DP83822_TX_CLK_SHIFT BIT(11) 108 109 /* SOR1 mode */ 110 #define DP83822_STRAP_MODE1 0 111 #define DP83822_STRAP_MODE2 BIT(0) 112 #define DP83822_STRAP_MODE3 BIT(1) 113 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 114 115 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 116 #define DP83822_COL_SHIFT 10 117 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 118 #define DP83822_RX_ER_SHIFT 8 119 120 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 121 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 122 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 123 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 124 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 125 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 126 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 127 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 128 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 129 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 130 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 131 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 132 133 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 134 ADVERTISED_FIBRE | \ 135 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 136 137 struct dp83822_private { 138 bool fx_signal_det_low; 139 int fx_enabled; 140 u16 fx_sd_enable; 141 u8 cfg_dac_minus; 142 u8 cfg_dac_plus; 143 }; 144 145 static int dp83822_set_wol(struct phy_device *phydev, 146 struct ethtool_wolinfo *wol) 147 { 148 struct net_device *ndev = phydev->attached_dev; 149 u16 value; 150 const u8 *mac; 151 152 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 153 mac = (const u8 *)ndev->dev_addr; 154 155 if (!is_valid_ether_addr(mac)) 156 return -EINVAL; 157 158 /* MAC addresses start with byte 5, but stored in mac[0]. 159 * 822 PHYs store bytes 4|5, 2|3, 0|1 160 */ 161 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, 162 (mac[1] << 8) | mac[0]); 163 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, 164 (mac[3] << 8) | mac[2]); 165 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, 166 (mac[5] << 8) | mac[4]); 167 168 value = phy_read_mmd(phydev, DP83822_DEVADDR, 169 MII_DP83822_WOL_CFG); 170 if (wol->wolopts & WAKE_MAGIC) 171 value |= DP83822_WOL_MAGIC_EN; 172 else 173 value &= ~DP83822_WOL_MAGIC_EN; 174 175 if (wol->wolopts & WAKE_MAGICSECURE) { 176 phy_write_mmd(phydev, DP83822_DEVADDR, 177 MII_DP83822_RXSOP1, 178 (wol->sopass[1] << 8) | wol->sopass[0]); 179 phy_write_mmd(phydev, DP83822_DEVADDR, 180 MII_DP83822_RXSOP2, 181 (wol->sopass[3] << 8) | wol->sopass[2]); 182 phy_write_mmd(phydev, DP83822_DEVADDR, 183 MII_DP83822_RXSOP3, 184 (wol->sopass[5] << 8) | wol->sopass[4]); 185 value |= DP83822_WOL_SECURE_ON; 186 } else { 187 value &= ~DP83822_WOL_SECURE_ON; 188 } 189 190 /* Clear any pending WoL interrupt */ 191 phy_read(phydev, MII_DP83822_MISR2); 192 193 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 194 DP83822_WOL_CLR_INDICATION; 195 196 return phy_write_mmd(phydev, DP83822_DEVADDR, 197 MII_DP83822_WOL_CFG, value); 198 } else { 199 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 200 MII_DP83822_WOL_CFG, DP83822_WOL_EN); 201 } 202 } 203 204 static void dp83822_get_wol(struct phy_device *phydev, 205 struct ethtool_wolinfo *wol) 206 { 207 int value; 208 u16 sopass_val; 209 210 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 211 wol->wolopts = 0; 212 213 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 214 215 if (value & DP83822_WOL_MAGIC_EN) 216 wol->wolopts |= WAKE_MAGIC; 217 218 if (value & DP83822_WOL_SECURE_ON) { 219 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 220 MII_DP83822_RXSOP1); 221 wol->sopass[0] = (sopass_val & 0xff); 222 wol->sopass[1] = (sopass_val >> 8); 223 224 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 225 MII_DP83822_RXSOP2); 226 wol->sopass[2] = (sopass_val & 0xff); 227 wol->sopass[3] = (sopass_val >> 8); 228 229 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 230 MII_DP83822_RXSOP3); 231 wol->sopass[4] = (sopass_val & 0xff); 232 wol->sopass[5] = (sopass_val >> 8); 233 234 wol->wolopts |= WAKE_MAGICSECURE; 235 } 236 237 /* WoL is not enabled so set wolopts to 0 */ 238 if (!(value & DP83822_WOL_EN)) 239 wol->wolopts = 0; 240 } 241 242 static int dp83822_config_intr(struct phy_device *phydev) 243 { 244 struct dp83822_private *dp83822 = phydev->priv; 245 int misr_status; 246 int physcr_status; 247 int err; 248 249 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 250 misr_status = phy_read(phydev, MII_DP83822_MISR1); 251 if (misr_status < 0) 252 return misr_status; 253 254 misr_status |= (DP83822_LINK_STAT_INT_EN | 255 DP83822_ENERGY_DET_INT_EN | 256 DP83822_LINK_QUAL_INT_EN); 257 258 /* Private data pointer is NULL on DP83825 */ 259 if (!dp83822 || !dp83822->fx_enabled) 260 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 261 DP83822_DUP_MODE_CHANGE_INT_EN | 262 DP83822_SPEED_CHANGED_INT_EN; 263 264 265 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 266 if (err < 0) 267 return err; 268 269 misr_status = phy_read(phydev, MII_DP83822_MISR2); 270 if (misr_status < 0) 271 return misr_status; 272 273 misr_status |= (DP83822_JABBER_DET_INT_EN | 274 DP83822_SLEEP_MODE_INT_EN | 275 DP83822_LB_FIFO_INT_EN | 276 DP83822_PAGE_RX_INT_EN | 277 DP83822_EEE_ERROR_CHANGE_INT_EN); 278 279 /* Private data pointer is NULL on DP83825 */ 280 if (!dp83822 || !dp83822->fx_enabled) 281 misr_status |= DP83822_ANEG_ERR_INT_EN | 282 DP83822_WOL_PKT_INT_EN; 283 284 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 285 if (err < 0) 286 return err; 287 288 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 289 if (physcr_status < 0) 290 return physcr_status; 291 292 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 293 294 } else { 295 err = phy_write(phydev, MII_DP83822_MISR1, 0); 296 if (err < 0) 297 return err; 298 299 err = phy_write(phydev, MII_DP83822_MISR2, 0); 300 if (err < 0) 301 return err; 302 303 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 304 if (physcr_status < 0) 305 return physcr_status; 306 307 physcr_status &= ~DP83822_PHYSCR_INTEN; 308 } 309 310 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 311 } 312 313 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 314 { 315 bool trigger_machine = false; 316 int irq_status; 317 318 /* The MISR1 and MISR2 registers are holding the interrupt status in 319 * the upper half (15:8), while the lower half (7:0) is used for 320 * controlling the interrupt enable state of those individual interrupt 321 * sources. To determine the possible interrupt sources, just read the 322 * MISR* register and use it directly to know which interrupts have 323 * been enabled previously or not. 324 */ 325 irq_status = phy_read(phydev, MII_DP83822_MISR1); 326 if (irq_status < 0) { 327 phy_error(phydev); 328 return IRQ_NONE; 329 } 330 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 331 trigger_machine = true; 332 333 irq_status = phy_read(phydev, MII_DP83822_MISR2); 334 if (irq_status < 0) { 335 phy_error(phydev); 336 return IRQ_NONE; 337 } 338 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 339 trigger_machine = true; 340 341 if (!trigger_machine) 342 return IRQ_NONE; 343 344 phy_trigger_machine(phydev); 345 346 return IRQ_HANDLED; 347 } 348 349 static int dp8382x_disable_wol(struct phy_device *phydev) 350 { 351 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, 352 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | 353 DP83822_WOL_SECURE_ON); 354 } 355 356 static int dp83822_read_status(struct phy_device *phydev) 357 { 358 struct dp83822_private *dp83822 = phydev->priv; 359 int status = phy_read(phydev, MII_DP83822_PHYSTS); 360 int ctrl2; 361 int ret; 362 363 if (dp83822->fx_enabled) { 364 if (status & DP83822_PHYSTS_LINK) { 365 phydev->speed = SPEED_UNKNOWN; 366 phydev->duplex = DUPLEX_UNKNOWN; 367 } else { 368 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 369 if (ctrl2 < 0) 370 return ctrl2; 371 372 if (!(ctrl2 & DP83822_FX_ENABLE)) { 373 ret = phy_write(phydev, MII_DP83822_CTRL_2, 374 DP83822_FX_ENABLE | ctrl2); 375 if (ret < 0) 376 return ret; 377 } 378 } 379 } 380 381 ret = genphy_read_status(phydev); 382 if (ret) 383 return ret; 384 385 if (status < 0) 386 return status; 387 388 if (status & DP83822_PHYSTS_DUPLEX) 389 phydev->duplex = DUPLEX_FULL; 390 else 391 phydev->duplex = DUPLEX_HALF; 392 393 if (status & DP83822_PHYSTS_10) 394 phydev->speed = SPEED_10; 395 else 396 phydev->speed = SPEED_100; 397 398 return 0; 399 } 400 401 static int dp83822_config_init(struct phy_device *phydev) 402 { 403 struct dp83822_private *dp83822 = phydev->priv; 404 struct device *dev = &phydev->mdio.dev; 405 int rgmii_delay; 406 s32 rx_int_delay; 407 s32 tx_int_delay; 408 int err = 0; 409 int bmcr; 410 411 if (phy_interface_is_rgmii(phydev)) { 412 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 413 true); 414 415 if (rx_int_delay <= 0) 416 rgmii_delay = 0; 417 else 418 rgmii_delay = DP83822_RX_CLK_SHIFT; 419 420 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 421 false); 422 if (tx_int_delay <= 0) 423 rgmii_delay &= ~DP83822_TX_CLK_SHIFT; 424 else 425 rgmii_delay |= DP83822_TX_CLK_SHIFT; 426 427 if (rgmii_delay) { 428 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 429 MII_DP83822_RCSR, rgmii_delay); 430 if (err) 431 return err; 432 } 433 434 phy_set_bits_mmd(phydev, DP83822_DEVADDR, 435 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 436 } else { 437 phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 438 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 439 } 440 441 if (dp83822->fx_enabled) { 442 err = phy_modify(phydev, MII_DP83822_CTRL_2, 443 DP83822_FX_ENABLE, 1); 444 if (err < 0) 445 return err; 446 447 /* Only allow advertising what this PHY supports */ 448 linkmode_and(phydev->advertising, phydev->advertising, 449 phydev->supported); 450 451 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 452 phydev->supported); 453 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 454 phydev->advertising); 455 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 456 phydev->supported); 457 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 458 phydev->supported); 459 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 460 phydev->advertising); 461 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 462 phydev->advertising); 463 464 /* Auto neg is not supported in fiber mode */ 465 bmcr = phy_read(phydev, MII_BMCR); 466 if (bmcr < 0) 467 return bmcr; 468 469 if (bmcr & BMCR_ANENABLE) { 470 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 471 if (err < 0) 472 return err; 473 } 474 phydev->autoneg = AUTONEG_DISABLE; 475 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 476 phydev->supported); 477 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 478 phydev->advertising); 479 480 /* Setup fiber advertisement */ 481 err = phy_modify_changed(phydev, MII_ADVERTISE, 482 MII_DP83822_FIBER_ADVERTISE, 483 MII_DP83822_FIBER_ADVERTISE); 484 485 if (err < 0) 486 return err; 487 488 if (dp83822->fx_signal_det_low) { 489 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 490 MII_DP83822_GENCFG, 491 DP83822_SIG_DET_LOW); 492 if (err) 493 return err; 494 } 495 } 496 return dp8382x_disable_wol(phydev); 497 } 498 499 static int dp83826_config_rmii_mode(struct phy_device *phydev) 500 { 501 struct device *dev = &phydev->mdio.dev; 502 const char *of_val; 503 int ret; 504 505 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { 506 if (strcmp(of_val, "master") == 0) { 507 ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, 508 DP83822_RMII_MODE_SEL); 509 } else if (strcmp(of_val, "slave") == 0) { 510 ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, 511 DP83822_RMII_MODE_SEL); 512 } else { 513 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", 514 of_val); 515 ret = -EINVAL; 516 } 517 518 if (ret) 519 return ret; 520 } 521 522 return 0; 523 } 524 525 static int dp83826_config_init(struct phy_device *phydev) 526 { 527 struct dp83822_private *dp83822 = phydev->priv; 528 u16 val, mask; 529 int ret; 530 531 if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 532 ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, 533 DP83822_RMII_MODE_EN); 534 if (ret) 535 return ret; 536 537 ret = dp83826_config_rmii_mode(phydev); 538 if (ret) 539 return ret; 540 } else { 541 ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, 542 DP83822_RMII_MODE_EN); 543 if (ret) 544 return ret; 545 } 546 547 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 548 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 549 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 550 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 551 dp83822->cfg_dac_minus)); 552 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 553 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val); 554 if (ret) 555 return ret; 556 557 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 558 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 559 dp83822->cfg_dac_minus)); 560 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 561 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val); 562 if (ret) 563 return ret; 564 } 565 566 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 567 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 568 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 569 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 570 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val); 571 if (ret) 572 return ret; 573 } 574 575 return dp8382x_disable_wol(phydev); 576 } 577 578 static int dp8382x_config_init(struct phy_device *phydev) 579 { 580 return dp8382x_disable_wol(phydev); 581 } 582 583 static int dp83822_phy_reset(struct phy_device *phydev) 584 { 585 int err; 586 587 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 588 if (err < 0) 589 return err; 590 591 return phydev->drv->config_init(phydev); 592 } 593 594 #ifdef CONFIG_OF_MDIO 595 static int dp83822_of_init(struct phy_device *phydev) 596 { 597 struct dp83822_private *dp83822 = phydev->priv; 598 struct device *dev = &phydev->mdio.dev; 599 600 /* Signal detection for the PHY is only enabled if the FX_EN and the 601 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 602 * is strapped otherwise signal detection is disabled for the PHY. 603 */ 604 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 605 dp83822->fx_signal_det_low = device_property_present(dev, 606 "ti,link-loss-low"); 607 if (!dp83822->fx_enabled) 608 dp83822->fx_enabled = device_property_present(dev, 609 "ti,fiber-mode"); 610 611 return 0; 612 } 613 614 static int dp83826_to_dac_minus_one_regval(int percent) 615 { 616 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 617 618 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 619 } 620 621 static int dp83826_to_dac_plus_one_regval(int percent) 622 { 623 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 624 625 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 626 } 627 628 static void dp83826_of_init(struct phy_device *phydev) 629 { 630 struct dp83822_private *dp83822 = phydev->priv; 631 struct device *dev = &phydev->mdio.dev; 632 u32 val; 633 634 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 635 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 636 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 637 638 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 639 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 640 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 641 } 642 #else 643 static int dp83822_of_init(struct phy_device *phydev) 644 { 645 return 0; 646 } 647 648 static void dp83826_of_init(struct phy_device *phydev) 649 { 650 } 651 #endif /* CONFIG_OF_MDIO */ 652 653 static int dp83822_read_straps(struct phy_device *phydev) 654 { 655 struct dp83822_private *dp83822 = phydev->priv; 656 int fx_enabled, fx_sd_enable; 657 int val; 658 659 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1); 660 if (val < 0) 661 return val; 662 663 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 664 665 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 666 if (fx_enabled == DP83822_STRAP_MODE2 || 667 fx_enabled == DP83822_STRAP_MODE3) 668 dp83822->fx_enabled = 1; 669 670 if (dp83822->fx_enabled) { 671 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 672 if (fx_sd_enable == DP83822_STRAP_MODE3 || 673 fx_sd_enable == DP83822_STRAP_MODE4) 674 dp83822->fx_sd_enable = 1; 675 } 676 677 return 0; 678 } 679 680 static int dp83822_probe(struct phy_device *phydev) 681 { 682 struct dp83822_private *dp83822; 683 int ret; 684 685 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 686 GFP_KERNEL); 687 if (!dp83822) 688 return -ENOMEM; 689 690 phydev->priv = dp83822; 691 692 ret = dp83822_read_straps(phydev); 693 if (ret) 694 return ret; 695 696 dp83822_of_init(phydev); 697 698 if (dp83822->fx_enabled) 699 phydev->port = PORT_FIBRE; 700 701 return 0; 702 } 703 704 static int dp83826_probe(struct phy_device *phydev) 705 { 706 struct dp83822_private *dp83822; 707 708 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 709 GFP_KERNEL); 710 if (!dp83822) 711 return -ENOMEM; 712 713 phydev->priv = dp83822; 714 715 dp83826_of_init(phydev); 716 717 return 0; 718 } 719 720 static int dp83822_suspend(struct phy_device *phydev) 721 { 722 int value; 723 724 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 725 726 if (!(value & DP83822_WOL_EN)) 727 genphy_suspend(phydev); 728 729 return 0; 730 } 731 732 static int dp83822_resume(struct phy_device *phydev) 733 { 734 int value; 735 736 genphy_resume(phydev); 737 738 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 739 740 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | 741 DP83822_WOL_CLR_INDICATION); 742 743 return 0; 744 } 745 746 #define DP83822_PHY_DRIVER(_id, _name) \ 747 { \ 748 PHY_ID_MATCH_MODEL(_id), \ 749 .name = (_name), \ 750 /* PHY_BASIC_FEATURES */ \ 751 .probe = dp83822_probe, \ 752 .soft_reset = dp83822_phy_reset, \ 753 .config_init = dp83822_config_init, \ 754 .read_status = dp83822_read_status, \ 755 .get_wol = dp83822_get_wol, \ 756 .set_wol = dp83822_set_wol, \ 757 .config_intr = dp83822_config_intr, \ 758 .handle_interrupt = dp83822_handle_interrupt, \ 759 .suspend = dp83822_suspend, \ 760 .resume = dp83822_resume, \ 761 } 762 763 #define DP83826_PHY_DRIVER(_id, _name) \ 764 { \ 765 PHY_ID_MATCH_MODEL(_id), \ 766 .name = (_name), \ 767 /* PHY_BASIC_FEATURES */ \ 768 .probe = dp83826_probe, \ 769 .soft_reset = dp83822_phy_reset, \ 770 .config_init = dp83826_config_init, \ 771 .get_wol = dp83822_get_wol, \ 772 .set_wol = dp83822_set_wol, \ 773 .config_intr = dp83822_config_intr, \ 774 .handle_interrupt = dp83822_handle_interrupt, \ 775 .suspend = dp83822_suspend, \ 776 .resume = dp83822_resume, \ 777 } 778 779 #define DP8382X_PHY_DRIVER(_id, _name) \ 780 { \ 781 PHY_ID_MATCH_MODEL(_id), \ 782 .name = (_name), \ 783 /* PHY_BASIC_FEATURES */ \ 784 .soft_reset = dp83822_phy_reset, \ 785 .config_init = dp8382x_config_init, \ 786 .get_wol = dp83822_get_wol, \ 787 .set_wol = dp83822_set_wol, \ 788 .config_intr = dp83822_config_intr, \ 789 .handle_interrupt = dp83822_handle_interrupt, \ 790 .suspend = dp83822_suspend, \ 791 .resume = dp83822_resume, \ 792 } 793 794 static struct phy_driver dp83822_driver[] = { 795 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 796 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 797 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 798 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 799 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 800 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 801 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 802 }; 803 module_phy_driver(dp83822_driver); 804 805 static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 806 { DP83822_PHY_ID, 0xfffffff0 }, 807 { DP83825I_PHY_ID, 0xfffffff0 }, 808 { DP83826C_PHY_ID, 0xfffffff0 }, 809 { DP83826NC_PHY_ID, 0xfffffff0 }, 810 { DP83825S_PHY_ID, 0xfffffff0 }, 811 { DP83825CM_PHY_ID, 0xfffffff0 }, 812 { DP83825CS_PHY_ID, 0xfffffff0 }, 813 { }, 814 }; 815 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 816 817 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 818 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 819 MODULE_LICENSE("GPL v2"); 820