1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/ethtool.h> 9 #include <linux/etherdevice.h> 10 #include <linux/kernel.h> 11 #include <linux/mii.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/phy.h> 15 #include <linux/phy_port.h> 16 #include <linux/netdevice.h> 17 #include <linux/bitfield.h> 18 19 #define DP83822_PHY_ID 0x2000a240 20 #define DP83825S_PHY_ID 0x2000a140 21 #define DP83825I_PHY_ID 0x2000a150 22 #define DP83825CM_PHY_ID 0x2000a160 23 #define DP83825CS_PHY_ID 0x2000a170 24 #define DP83826C_PHY_ID 0x2000a130 25 #define DP83826NC_PHY_ID 0x2000a110 26 27 #define MII_DP83822_CTRL_2 0x0a 28 #define MII_DP83822_PHYSTS 0x10 29 #define MII_DP83822_PHYSCR 0x11 30 #define MII_DP83822_MISR1 0x12 31 #define MII_DP83822_MISR2 0x13 32 #define MII_DP83822_FCSCR 0x14 33 #define MII_DP83822_RCSR 0x17 34 #define MII_DP83822_RESET_CTRL 0x1f 35 #define MII_DP83822_MLEDCR 0x25 36 #define MII_DP83822_LDCTRL 0x403 37 #define MII_DP83822_LEDCFG1 0x460 38 #define MII_DP83822_IOCTRL 0x461 39 #define MII_DP83822_IOCTRL1 0x462 40 #define MII_DP83822_IOCTRL2 0x463 41 #define MII_DP83822_GENCFG 0x465 42 #define MII_DP83822_SOR1 0x467 43 44 /* DP83826 specific registers */ 45 #define MII_DP83826_VOD_CFG1 0x30b 46 #define MII_DP83826_VOD_CFG2 0x30c 47 48 /* GENCFG */ 49 #define DP83822_SIG_DET_LOW BIT(0) 50 51 /* Control Register 2 bits */ 52 #define DP83822_FX_ENABLE BIT(14) 53 54 #define DP83822_SW_RESET BIT(15) 55 #define DP83822_DIG_RESTART BIT(14) 56 57 /* PHY STS bits */ 58 #define DP83822_PHYSTS_DUPLEX BIT(2) 59 #define DP83822_PHYSTS_10 BIT(1) 60 #define DP83822_PHYSTS_LINK BIT(0) 61 62 /* PHYSCR Register Fields */ 63 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 64 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 65 66 /* MISR1 bits */ 67 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 68 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 69 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 70 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 71 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 72 #define DP83822_LINK_STAT_INT_EN BIT(5) 73 #define DP83822_ENERGY_DET_INT_EN BIT(6) 74 #define DP83822_LINK_QUAL_INT_EN BIT(7) 75 76 /* MISR2 bits */ 77 #define DP83822_JABBER_DET_INT_EN BIT(0) 78 #define DP83822_WOL_PKT_INT_EN BIT(1) 79 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 80 #define DP83822_MDI_XOVER_INT_EN BIT(3) 81 #define DP83822_LB_FIFO_INT_EN BIT(4) 82 #define DP83822_PAGE_RX_INT_EN BIT(5) 83 #define DP83822_ANEG_ERR_INT_EN BIT(6) 84 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 85 86 /* INT_STAT1 bits */ 87 #define DP83822_WOL_INT_EN BIT(4) 88 #define DP83822_WOL_INT_STAT BIT(12) 89 90 #define MII_DP83822_RXSOP1 0x04a5 91 #define MII_DP83822_RXSOP2 0x04a6 92 #define MII_DP83822_RXSOP3 0x04a7 93 94 /* WoL Registers */ 95 #define MII_DP83822_WOL_CFG 0x04a0 96 #define MII_DP83822_WOL_STAT 0x04a1 97 #define MII_DP83822_WOL_DA1 0x04a2 98 #define MII_DP83822_WOL_DA2 0x04a3 99 #define MII_DP83822_WOL_DA3 0x04a4 100 101 /* WoL bits */ 102 #define DP83822_WOL_MAGIC_EN BIT(0) 103 #define DP83822_WOL_SECURE_ON BIT(5) 104 #define DP83822_WOL_EN BIT(7) 105 #define DP83822_WOL_INDICATION_SEL BIT(8) 106 #define DP83822_WOL_CLR_INDICATION BIT(11) 107 108 /* RCSR bits */ 109 #define DP83822_RMII_MODE_EN BIT(5) 110 #define DP83822_RMII_MODE_SEL BIT(7) 111 #define DP83822_RGMII_MODE_EN BIT(9) 112 #define DP83822_RX_CLK_SHIFT BIT(12) 113 #define DP83822_TX_CLK_SHIFT BIT(11) 114 115 /* MLEDCR bits */ 116 #define DP83822_MLEDCR_CFG GENMASK(6, 3) 117 #define DP83822_MLEDCR_ROUTE GENMASK(1, 0) 118 #define DP83822_MLEDCR_ROUTE_LED_0 DP83822_MLEDCR_ROUTE 119 120 /* LEDCFG1 bits */ 121 #define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8) 122 #define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4) 123 124 /* IOCTRL bits */ 125 #define DP83822_IOCTRL_MAC_IMPEDANCE_CTRL GENMASK(4, 1) 126 127 /* IOCTRL1 bits */ 128 #define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8) 129 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3 BIT(0) 130 #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0) 131 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0) 132 133 /* LDCTRL bits */ 134 #define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4) 135 136 /* IOCTRL2 bits */ 137 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4) 138 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0) 139 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0) 140 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED BIT(0) 141 142 #define DP83822_CLK_SRC_MAC_IF 0x0 143 #define DP83822_CLK_SRC_XI 0x1 144 #define DP83822_CLK_SRC_INT_REF 0x2 145 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4 146 #define DP83822_CLK_SRC_FREE_RUNNING 0x6 147 #define DP83822_CLK_SRC_RECOVERED 0x7 148 149 #define DP83822_LED_FN_LINK 0x0 /* Link established */ 150 #define DP83822_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */ 151 #define DP83822_LED_FN_TX 0x2 /* Transmit activity */ 152 #define DP83822_LED_FN_RX 0x3 /* Receive activity */ 153 #define DP83822_LED_FN_COLLISION 0x4 /* Collision detected */ 154 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */ 155 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */ 156 #define DP83822_LED_FN_FULL_DUPLEX 0x7 /* Full duplex */ 157 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */ 158 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */ 159 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */ 160 #define DP83822_LED_FN_LPI_MODE 0xb /* LPI Mode (EEE) */ 161 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */ 162 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */ 163 #define DP83822_LED_FN_PRBS_ERR 0xe /* Blink for PRBS error */ 164 165 /* SOR1 mode */ 166 #define DP83822_STRAP_MODE1 0 167 #define DP83822_STRAP_MODE2 BIT(0) 168 #define DP83822_STRAP_MODE3 BIT(1) 169 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 170 171 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 172 #define DP83822_COL_SHIFT 10 173 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 174 #define DP83822_RX_ER_SHIFT 8 175 176 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 177 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 178 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 179 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 180 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 181 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 182 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 183 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 184 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 185 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 186 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 187 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 188 189 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 190 ADVERTISED_FIBRE | \ 191 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 192 193 #define DP83822_MAX_LED_PINS 4 194 195 #define DP83822_LED_INDEX_LED_0 0 196 #define DP83822_LED_INDEX_LED_1_GPIO1 1 197 #define DP83822_LED_INDEX_COL_GPIO2 2 198 #define DP83822_LED_INDEX_RX_D3_GPIO3 3 199 200 struct dp83822_private { 201 bool fx_signal_det_low; 202 int fx_enabled; 203 u16 fx_sd_enable; 204 u8 cfg_dac_minus; 205 u8 cfg_dac_plus; 206 struct ethtool_wolinfo wol; 207 bool set_gpio2_clk_out; 208 u32 gpio2_clk_out; 209 bool led_pin_enable[DP83822_MAX_LED_PINS]; 210 int tx_amplitude_100base_tx_index; 211 int mac_termination_index; 212 }; 213 214 static int dp83822_config_wol(struct phy_device *phydev, 215 struct ethtool_wolinfo *wol) 216 { 217 struct net_device *ndev = phydev->attached_dev; 218 u16 value; 219 const u8 *mac; 220 221 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 222 mac = (const u8 *)ndev->dev_addr; 223 224 if (!is_valid_ether_addr(mac)) 225 return -EINVAL; 226 227 /* MAC addresses start with byte 5, but stored in mac[0]. 228 * 822 PHYs store bytes 4|5, 2|3, 0|1 229 */ 230 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, 231 (mac[1] << 8) | mac[0]); 232 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, 233 (mac[3] << 8) | mac[2]); 234 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, 235 (mac[5] << 8) | mac[4]); 236 237 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, 238 MII_DP83822_WOL_CFG); 239 if (wol->wolopts & WAKE_MAGIC) 240 value |= DP83822_WOL_MAGIC_EN; 241 else 242 value &= ~DP83822_WOL_MAGIC_EN; 243 244 if (wol->wolopts & WAKE_MAGICSECURE) { 245 phy_write_mmd(phydev, MDIO_MMD_VEND2, 246 MII_DP83822_RXSOP1, 247 (wol->sopass[1] << 8) | wol->sopass[0]); 248 phy_write_mmd(phydev, MDIO_MMD_VEND2, 249 MII_DP83822_RXSOP2, 250 (wol->sopass[3] << 8) | wol->sopass[2]); 251 phy_write_mmd(phydev, MDIO_MMD_VEND2, 252 MII_DP83822_RXSOP3, 253 (wol->sopass[5] << 8) | wol->sopass[4]); 254 value |= DP83822_WOL_SECURE_ON; 255 } else { 256 value &= ~DP83822_WOL_SECURE_ON; 257 } 258 259 /* Clear any pending WoL interrupt */ 260 phy_read(phydev, MII_DP83822_MISR2); 261 262 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 263 DP83822_WOL_CLR_INDICATION; 264 265 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 266 MII_DP83822_WOL_CFG, value); 267 } else { 268 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 269 MII_DP83822_WOL_CFG, 270 DP83822_WOL_EN | 271 DP83822_WOL_MAGIC_EN | 272 DP83822_WOL_SECURE_ON); 273 } 274 } 275 276 static int dp83822_set_wol(struct phy_device *phydev, 277 struct ethtool_wolinfo *wol) 278 { 279 struct dp83822_private *dp83822 = phydev->priv; 280 int ret; 281 282 ret = dp83822_config_wol(phydev, wol); 283 if (!ret) 284 memcpy(&dp83822->wol, wol, sizeof(*wol)); 285 return ret; 286 } 287 288 static void dp83822_get_wol(struct phy_device *phydev, 289 struct ethtool_wolinfo *wol) 290 { 291 int value; 292 u16 sopass_val; 293 294 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 295 wol->wolopts = 0; 296 297 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 298 299 if (value & DP83822_WOL_MAGIC_EN) 300 wol->wolopts |= WAKE_MAGIC; 301 302 if (value & DP83822_WOL_SECURE_ON) { 303 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 304 MII_DP83822_RXSOP1); 305 wol->sopass[0] = (sopass_val & 0xff); 306 wol->sopass[1] = (sopass_val >> 8); 307 308 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 309 MII_DP83822_RXSOP2); 310 wol->sopass[2] = (sopass_val & 0xff); 311 wol->sopass[3] = (sopass_val >> 8); 312 313 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 314 MII_DP83822_RXSOP3); 315 wol->sopass[4] = (sopass_val & 0xff); 316 wol->sopass[5] = (sopass_val >> 8); 317 318 wol->wolopts |= WAKE_MAGICSECURE; 319 } 320 321 /* WoL is not enabled so set wolopts to 0 */ 322 if (!(value & DP83822_WOL_EN)) 323 wol->wolopts = 0; 324 } 325 326 static int dp83822_config_intr(struct phy_device *phydev) 327 { 328 struct dp83822_private *dp83822 = phydev->priv; 329 int misr_status; 330 int physcr_status; 331 int err; 332 333 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 334 misr_status = phy_read(phydev, MII_DP83822_MISR1); 335 if (misr_status < 0) 336 return misr_status; 337 338 misr_status |= (DP83822_LINK_STAT_INT_EN | 339 DP83822_ENERGY_DET_INT_EN | 340 DP83822_LINK_QUAL_INT_EN); 341 342 if (!dp83822->fx_enabled) 343 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 344 DP83822_DUP_MODE_CHANGE_INT_EN | 345 DP83822_SPEED_CHANGED_INT_EN; 346 347 348 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 349 if (err < 0) 350 return err; 351 352 misr_status = phy_read(phydev, MII_DP83822_MISR2); 353 if (misr_status < 0) 354 return misr_status; 355 356 misr_status |= (DP83822_JABBER_DET_INT_EN | 357 DP83822_SLEEP_MODE_INT_EN | 358 DP83822_LB_FIFO_INT_EN | 359 DP83822_PAGE_RX_INT_EN | 360 DP83822_EEE_ERROR_CHANGE_INT_EN); 361 362 if (!dp83822->fx_enabled) 363 misr_status |= DP83822_ANEG_ERR_INT_EN | 364 DP83822_WOL_PKT_INT_EN; 365 366 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 367 if (err < 0) 368 return err; 369 370 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 371 if (physcr_status < 0) 372 return physcr_status; 373 374 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 375 376 } else { 377 err = phy_write(phydev, MII_DP83822_MISR1, 0); 378 if (err < 0) 379 return err; 380 381 err = phy_write(phydev, MII_DP83822_MISR2, 0); 382 if (err < 0) 383 return err; 384 385 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 386 if (physcr_status < 0) 387 return physcr_status; 388 389 physcr_status &= ~DP83822_PHYSCR_INTEN; 390 } 391 392 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 393 } 394 395 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 396 { 397 bool trigger_machine = false; 398 int irq_status; 399 400 /* The MISR1 and MISR2 registers are holding the interrupt status in 401 * the upper half (15:8), while the lower half (7:0) is used for 402 * controlling the interrupt enable state of those individual interrupt 403 * sources. To determine the possible interrupt sources, just read the 404 * MISR* register and use it directly to know which interrupts have 405 * been enabled previously or not. 406 */ 407 irq_status = phy_read(phydev, MII_DP83822_MISR1); 408 if (irq_status < 0) { 409 phy_error(phydev); 410 return IRQ_NONE; 411 } 412 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 413 trigger_machine = true; 414 415 irq_status = phy_read(phydev, MII_DP83822_MISR2); 416 if (irq_status < 0) { 417 phy_error(phydev); 418 return IRQ_NONE; 419 } 420 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 421 trigger_machine = true; 422 423 if (!trigger_machine) 424 return IRQ_NONE; 425 426 phy_trigger_machine(phydev); 427 428 return IRQ_HANDLED; 429 } 430 431 static int dp83822_read_status(struct phy_device *phydev) 432 { 433 struct dp83822_private *dp83822 = phydev->priv; 434 int status = phy_read(phydev, MII_DP83822_PHYSTS); 435 int ctrl2; 436 int ret; 437 438 if (dp83822->fx_enabled) { 439 if (status & DP83822_PHYSTS_LINK) { 440 phydev->speed = SPEED_UNKNOWN; 441 phydev->duplex = DUPLEX_UNKNOWN; 442 } else { 443 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 444 if (ctrl2 < 0) 445 return ctrl2; 446 447 if (!(ctrl2 & DP83822_FX_ENABLE)) { 448 ret = phy_write(phydev, MII_DP83822_CTRL_2, 449 DP83822_FX_ENABLE | ctrl2); 450 if (ret < 0) 451 return ret; 452 } 453 } 454 } 455 456 ret = genphy_read_status(phydev); 457 if (ret) 458 return ret; 459 460 if (status < 0) 461 return status; 462 463 if (status & DP83822_PHYSTS_DUPLEX) 464 phydev->duplex = DUPLEX_FULL; 465 else 466 phydev->duplex = DUPLEX_HALF; 467 468 if (status & DP83822_PHYSTS_10) 469 phydev->speed = SPEED_10; 470 else 471 phydev->speed = SPEED_100; 472 473 return 0; 474 } 475 476 static int dp83822_config_init_leds(struct phy_device *phydev) 477 { 478 struct dp83822_private *dp83822 = phydev->priv; 479 int ret; 480 481 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0]) { 482 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR, 483 DP83822_MLEDCR_ROUTE, 484 FIELD_PREP(DP83822_MLEDCR_ROUTE, 485 DP83822_MLEDCR_ROUTE_LED_0)); 486 if (ret) 487 return ret; 488 } else if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) { 489 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 490 DP83822_IOCTRL2_GPIO2_CTRL, 491 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 492 DP83822_IOCTRL2_GPIO2_CTRL_MLED)); 493 if (ret) 494 return ret; 495 } 496 497 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_1_GPIO1]) { 498 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1, 499 DP83822_IOCTRL1_GPIO1_CTRL, 500 FIELD_PREP(DP83822_IOCTRL1_GPIO1_CTRL, 501 DP83822_IOCTRL1_GPIO1_CTRL_LED_1)); 502 if (ret) 503 return ret; 504 } 505 506 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3]) { 507 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1, 508 DP83822_IOCTRL1_GPIO3_CTRL, 509 FIELD_PREP(DP83822_IOCTRL1_GPIO3_CTRL, 510 DP83822_IOCTRL1_GPIO3_CTRL_LED3)); 511 if (ret) 512 return ret; 513 } 514 515 return 0; 516 } 517 518 static int dp83822_config_init(struct phy_device *phydev) 519 { 520 struct dp83822_private *dp83822 = phydev->priv; 521 int rgmii_delay = 0; 522 s32 rx_int_delay; 523 s32 tx_int_delay; 524 int err = 0; 525 int bmcr; 526 527 if (dp83822->set_gpio2_clk_out) 528 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 529 DP83822_IOCTRL2_GPIO2_CTRL | 530 DP83822_IOCTRL2_GPIO2_CLK_SRC, 531 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 532 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) | 533 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC, 534 dp83822->gpio2_clk_out)); 535 536 if (dp83822->tx_amplitude_100base_tx_index >= 0) 537 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL, 538 DP83822_100BASE_TX_LINE_DRIVER_SWING, 539 FIELD_PREP(DP83822_100BASE_TX_LINE_DRIVER_SWING, 540 dp83822->tx_amplitude_100base_tx_index)); 541 542 if (dp83822->mac_termination_index >= 0) 543 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL, 544 DP83822_IOCTRL_MAC_IMPEDANCE_CTRL, 545 FIELD_PREP(DP83822_IOCTRL_MAC_IMPEDANCE_CTRL, 546 dp83822->mac_termination_index)); 547 548 err = dp83822_config_init_leds(phydev); 549 if (err) 550 return err; 551 552 if (phy_interface_is_rgmii(phydev)) { 553 rx_int_delay = phy_get_internal_delay(phydev, NULL, 0, true); 554 555 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ 556 if (rx_int_delay > 0) 557 rgmii_delay |= DP83822_RX_CLK_SHIFT; 558 559 tx_int_delay = phy_get_internal_delay(phydev, NULL, 0, false); 560 561 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ 562 if (tx_int_delay <= 0) 563 rgmii_delay |= DP83822_TX_CLK_SHIFT; 564 565 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 566 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); 567 if (err) 568 return err; 569 570 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 571 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 572 573 if (err) 574 return err; 575 } else { 576 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 577 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 578 579 if (err) 580 return err; 581 } 582 583 if (dp83822->fx_enabled) { 584 err = phy_modify(phydev, MII_DP83822_CTRL_2, 585 DP83822_FX_ENABLE, 1); 586 if (err < 0) 587 return err; 588 589 /* Only allow advertising what this PHY supports */ 590 linkmode_and(phydev->advertising, phydev->advertising, 591 phydev->supported); 592 593 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 594 phydev->supported); 595 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 596 phydev->advertising); 597 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 598 phydev->supported); 599 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 600 phydev->supported); 601 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 602 phydev->advertising); 603 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 604 phydev->advertising); 605 606 /* Auto neg is not supported in fiber mode */ 607 bmcr = phy_read(phydev, MII_BMCR); 608 if (bmcr < 0) 609 return bmcr; 610 611 if (bmcr & BMCR_ANENABLE) { 612 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 613 if (err < 0) 614 return err; 615 } 616 phydev->autoneg = AUTONEG_DISABLE; 617 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 618 phydev->supported); 619 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 620 phydev->advertising); 621 622 /* Setup fiber advertisement */ 623 err = phy_modify_changed(phydev, MII_ADVERTISE, 624 MII_DP83822_FIBER_ADVERTISE, 625 MII_DP83822_FIBER_ADVERTISE); 626 627 if (err < 0) 628 return err; 629 630 if (dp83822->fx_signal_det_low) { 631 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 632 MII_DP83822_GENCFG, 633 DP83822_SIG_DET_LOW); 634 if (err) 635 return err; 636 } 637 } 638 return dp83822_config_wol(phydev, &dp83822->wol); 639 } 640 641 static int dp8382x_config_rmii_mode(struct phy_device *phydev) 642 { 643 struct device *dev = &phydev->mdio.dev; 644 const char *of_val; 645 int ret; 646 647 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { 648 if (strcmp(of_val, "master") == 0) { 649 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 650 DP83822_RMII_MODE_SEL); 651 } else if (strcmp(of_val, "slave") == 0) { 652 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 653 DP83822_RMII_MODE_SEL); 654 } else { 655 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", 656 of_val); 657 ret = -EINVAL; 658 } 659 660 if (ret) 661 return ret; 662 } 663 664 return 0; 665 } 666 667 static int dp83826_config_init(struct phy_device *phydev) 668 { 669 struct dp83822_private *dp83822 = phydev->priv; 670 u16 val, mask; 671 int ret; 672 673 if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 674 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 675 DP83822_RMII_MODE_EN); 676 if (ret) 677 return ret; 678 679 ret = dp8382x_config_rmii_mode(phydev); 680 if (ret) 681 return ret; 682 } else { 683 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 684 DP83822_RMII_MODE_EN); 685 if (ret) 686 return ret; 687 } 688 689 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 690 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 691 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 692 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 693 dp83822->cfg_dac_minus)); 694 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 695 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val); 696 if (ret) 697 return ret; 698 699 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 700 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 701 dp83822->cfg_dac_minus)); 702 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 703 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 704 if (ret) 705 return ret; 706 } 707 708 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 709 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 710 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 711 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 712 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 713 if (ret) 714 return ret; 715 } 716 717 return dp83822_config_wol(phydev, &dp83822->wol); 718 } 719 720 static int dp83825_config_init(struct phy_device *phydev) 721 { 722 struct dp83822_private *dp83822 = phydev->priv; 723 int ret; 724 725 ret = dp8382x_config_rmii_mode(phydev); 726 if (ret) 727 return ret; 728 729 return dp83822_config_wol(phydev, &dp83822->wol); 730 } 731 732 static int dp83822_phy_reset(struct phy_device *phydev) 733 { 734 int err; 735 736 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 737 if (err < 0) 738 return err; 739 740 return phydev->drv->config_init(phydev); 741 } 742 743 #if IS_ENABLED(CONFIG_OF_MDIO) 744 static const u32 tx_amplitude_100base_tx_gain[] = { 745 80, 82, 83, 85, 87, 88, 90, 92, 746 93, 95, 97, 98, 100, 102, 103, 105, 747 }; 748 749 static const u32 mac_termination[] = { 750 99, 91, 84, 78, 73, 69, 65, 61, 58, 55, 53, 50, 48, 46, 44, 43, 751 }; 752 753 static int dp83822_of_init_leds(struct phy_device *phydev) 754 { 755 struct device_node *node = phydev->mdio.dev.of_node; 756 struct dp83822_private *dp83822 = phydev->priv; 757 struct device_node *leds; 758 u32 index; 759 int err; 760 761 if (!node) 762 return 0; 763 764 leds = of_get_child_by_name(node, "leds"); 765 if (!leds) 766 return 0; 767 768 for_each_available_child_of_node_scoped(leds, led) { 769 err = of_property_read_u32(led, "reg", &index); 770 if (err) { 771 of_node_put(leds); 772 return err; 773 } 774 775 if (index <= DP83822_LED_INDEX_RX_D3_GPIO3) { 776 dp83822->led_pin_enable[index] = true; 777 } else { 778 of_node_put(leds); 779 return -EINVAL; 780 } 781 } 782 783 of_node_put(leds); 784 /* LED_0 and COL(GPIO2) use the MLED function. MLED can be routed to 785 * only one of these two pins at a time. 786 */ 787 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0] && 788 dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) { 789 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n"); 790 return -EINVAL; 791 } 792 793 if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2] && 794 dp83822->set_gpio2_clk_out) { 795 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n"); 796 return -EINVAL; 797 } 798 799 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3] && 800 phydev->interface != PHY_INTERFACE_MODE_RMII) { 801 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n"); 802 return -EINVAL; 803 } 804 805 return 0; 806 } 807 808 static int dp83822_of_init(struct phy_device *phydev) 809 { 810 struct dp83822_private *dp83822 = phydev->priv; 811 struct device *dev = &phydev->mdio.dev; 812 const char *of_val; 813 int i, ret; 814 u32 val; 815 816 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) { 817 if (strcmp(of_val, "mac-if") == 0) { 818 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF; 819 } else if (strcmp(of_val, "xi") == 0) { 820 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI; 821 } else if (strcmp(of_val, "int-ref") == 0) { 822 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF; 823 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) { 824 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF; 825 } else if (strcmp(of_val, "free-running") == 0) { 826 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING; 827 } else if (strcmp(of_val, "recovered") == 0) { 828 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED; 829 } else { 830 phydev_err(phydev, 831 "Invalid value for ti,gpio2-clk-out property (%s)\n", 832 of_val); 833 return -EINVAL; 834 } 835 836 dp83822->set_gpio2_clk_out = true; 837 } 838 839 ret = phy_get_tx_amplitude_gain(phydev, dev, 840 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 841 &val); 842 if (!ret) { 843 for (i = 0; i < ARRAY_SIZE(tx_amplitude_100base_tx_gain); i++) { 844 if (tx_amplitude_100base_tx_gain[i] == val) { 845 dp83822->tx_amplitude_100base_tx_index = i; 846 break; 847 } 848 } 849 850 if (dp83822->tx_amplitude_100base_tx_index < 0) { 851 phydev_err(phydev, 852 "Invalid value for tx-amplitude-100base-tx-percent property (%u)\n", 853 val); 854 return -EINVAL; 855 } 856 } 857 858 ret = phy_get_mac_termination(phydev, dev, &val); 859 if (!ret) { 860 for (i = 0; i < ARRAY_SIZE(mac_termination); i++) { 861 if (mac_termination[i] == val) { 862 dp83822->mac_termination_index = i; 863 break; 864 } 865 } 866 867 if (dp83822->mac_termination_index < 0) { 868 phydev_err(phydev, 869 "Invalid value for mac-termination-ohms property (%u)\n", 870 val); 871 return -EINVAL; 872 } 873 } 874 875 return dp83822_of_init_leds(phydev); 876 } 877 878 static int dp83826_to_dac_minus_one_regval(int percent) 879 { 880 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 881 882 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 883 } 884 885 static int dp83826_to_dac_plus_one_regval(int percent) 886 { 887 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 888 889 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 890 } 891 892 static void dp83826_of_init(struct phy_device *phydev) 893 { 894 struct dp83822_private *dp83822 = phydev->priv; 895 struct device *dev = &phydev->mdio.dev; 896 u32 val; 897 898 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 899 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 900 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 901 902 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 903 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 904 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 905 } 906 #else 907 static int dp83822_of_init(struct phy_device *phydev) 908 { 909 return 0; 910 } 911 912 static void dp83826_of_init(struct phy_device *phydev) 913 { 914 } 915 #endif /* CONFIG_OF_MDIO */ 916 917 static int dp83822_read_straps(struct phy_device *phydev) 918 { 919 struct dp83822_private *dp83822 = phydev->priv; 920 int fx_enabled, fx_sd_enable; 921 int val; 922 923 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1); 924 if (val < 0) 925 return val; 926 927 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 928 929 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 930 if (fx_enabled == DP83822_STRAP_MODE2 || 931 fx_enabled == DP83822_STRAP_MODE3) 932 dp83822->fx_enabled = 1; 933 934 if (dp83822->fx_enabled) { 935 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 936 if (fx_sd_enable == DP83822_STRAP_MODE3 || 937 fx_sd_enable == DP83822_STRAP_MODE4) 938 dp83822->fx_sd_enable = 1; 939 } 940 941 return 0; 942 } 943 944 static int dp83822_attach_mdi_port(struct phy_device *phydev, 945 struct phy_port *port) 946 { 947 struct dp83822_private *dp83822 = phydev->priv; 948 int ret; 949 950 if (port->mediums) { 951 if (phy_port_is_fiber(port)) 952 dp83822->fx_enabled = true; 953 } else { 954 ret = dp83822_read_straps(phydev); 955 if (ret) 956 return ret; 957 958 #if IS_ENABLED(CONFIG_OF_MDIO) 959 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 960 dp83822->fx_signal_det_low = 961 device_property_present(&phydev->mdio.dev, 962 "ti,link-loss-low"); 963 964 /* ti,fiber-mode is still used for backwards compatibility, but 965 * has been replaced with the mdi node definition, see 966 * ethernet-port.yaml 967 */ 968 if (!dp83822->fx_enabled) 969 dp83822->fx_enabled = 970 device_property_present(&phydev->mdio.dev, 971 "ti,fiber-mode"); 972 #endif /* CONFIG_OF_MDIO */ 973 974 if (dp83822->fx_enabled) { 975 port->mediums = BIT(ETHTOOL_LINK_MEDIUM_BASEF); 976 } else { 977 /* This PHY can only to 100BaseTX max, so on 2 pairs */ 978 port->pairs = 2; 979 port->mediums = BIT(ETHTOOL_LINK_MEDIUM_BASET); 980 } 981 } 982 983 return 0; 984 } 985 986 static int dp8382x_probe(struct phy_device *phydev) 987 { 988 struct device *dev = &phydev->mdio.dev; 989 struct dp83822_private *dp83822; 990 struct clk *clk; 991 992 dp83822 = devm_kzalloc(dev, sizeof(*dp83822), GFP_KERNEL); 993 if (!dp83822) 994 return -ENOMEM; 995 996 clk = devm_clk_get_optional_enabled(dev, NULL); 997 if (IS_ERR(clk)) { 998 return dev_err_probe(dev, PTR_ERR(clk), 999 "Failed to request ref clock\n"); 1000 } 1001 1002 dp83822->tx_amplitude_100base_tx_index = -1; 1003 dp83822->mac_termination_index = -1; 1004 phydev->priv = dp83822; 1005 1006 return 0; 1007 } 1008 1009 static int dp83822_probe(struct phy_device *phydev) 1010 { 1011 int ret; 1012 1013 ret = dp8382x_probe(phydev); 1014 if (ret) 1015 return ret; 1016 1017 return dp83822_of_init(phydev); 1018 } 1019 1020 static int dp83826_probe(struct phy_device *phydev) 1021 { 1022 int ret; 1023 1024 ret = dp8382x_probe(phydev); 1025 if (ret) 1026 return ret; 1027 1028 dp83826_of_init(phydev); 1029 1030 return 0; 1031 } 1032 1033 static int dp83822_suspend(struct phy_device *phydev) 1034 { 1035 int value; 1036 1037 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 1038 1039 if (!(value & DP83822_WOL_EN)) 1040 genphy_suspend(phydev); 1041 1042 return 0; 1043 } 1044 1045 static int dp83822_resume(struct phy_device *phydev) 1046 { 1047 int value; 1048 1049 genphy_resume(phydev); 1050 1051 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 1052 1053 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | 1054 DP83822_WOL_CLR_INDICATION); 1055 1056 return 0; 1057 } 1058 1059 static int dp83822_led_mode(u8 index, unsigned long rules) 1060 { 1061 switch (rules) { 1062 case BIT(TRIGGER_NETDEV_LINK): 1063 return DP83822_LED_FN_LINK; 1064 case BIT(TRIGGER_NETDEV_LINK_10): 1065 return DP83822_LED_FN_LINK_10_BT; 1066 case BIT(TRIGGER_NETDEV_LINK_100): 1067 return DP83822_LED_FN_LINK_100_BTX; 1068 case BIT(TRIGGER_NETDEV_FULL_DUPLEX): 1069 return DP83822_LED_FN_FULL_DUPLEX; 1070 case BIT(TRIGGER_NETDEV_TX): 1071 return DP83822_LED_FN_TX; 1072 case BIT(TRIGGER_NETDEV_RX): 1073 return DP83822_LED_FN_RX; 1074 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 1075 return DP83822_LED_FN_RX_TX; 1076 case BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR): 1077 return DP83822_LED_FN_RX_TX_ERR; 1078 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 1079 return DP83822_LED_FN_LINK_RX_TX; 1080 default: 1081 return -EOPNOTSUPP; 1082 } 1083 } 1084 1085 static int dp83822_led_hw_is_supported(struct phy_device *phydev, u8 index, 1086 unsigned long rules) 1087 { 1088 int mode; 1089 1090 mode = dp83822_led_mode(index, rules); 1091 if (mode < 0) 1092 return mode; 1093 1094 return 0; 1095 } 1096 1097 static int dp83822_led_hw_control_set(struct phy_device *phydev, u8 index, 1098 unsigned long rules) 1099 { 1100 int mode; 1101 1102 mode = dp83822_led_mode(index, rules); 1103 if (mode < 0) 1104 return mode; 1105 1106 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) 1107 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1108 MII_DP83822_MLEDCR, DP83822_MLEDCR_CFG, 1109 FIELD_PREP(DP83822_MLEDCR_CFG, mode)); 1110 else if (index == DP83822_LED_INDEX_LED_1_GPIO1) 1111 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1112 MII_DP83822_LEDCFG1, 1113 DP83822_LEDCFG1_LED1_CTRL, 1114 FIELD_PREP(DP83822_LEDCFG1_LED1_CTRL, 1115 mode)); 1116 else 1117 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1118 MII_DP83822_LEDCFG1, 1119 DP83822_LEDCFG1_LED3_CTRL, 1120 FIELD_PREP(DP83822_LEDCFG1_LED3_CTRL, 1121 mode)); 1122 } 1123 1124 static int dp83822_led_hw_control_get(struct phy_device *phydev, u8 index, 1125 unsigned long *rules) 1126 { 1127 int val; 1128 1129 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) { 1130 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR); 1131 if (val < 0) 1132 return val; 1133 1134 val = FIELD_GET(DP83822_MLEDCR_CFG, val); 1135 } else { 1136 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LEDCFG1); 1137 if (val < 0) 1138 return val; 1139 1140 if (index == DP83822_LED_INDEX_LED_1_GPIO1) 1141 val = FIELD_GET(DP83822_LEDCFG1_LED1_CTRL, val); 1142 else 1143 val = FIELD_GET(DP83822_LEDCFG1_LED3_CTRL, val); 1144 } 1145 1146 switch (val) { 1147 case DP83822_LED_FN_LINK: 1148 *rules = BIT(TRIGGER_NETDEV_LINK); 1149 break; 1150 case DP83822_LED_FN_LINK_10_BT: 1151 *rules = BIT(TRIGGER_NETDEV_LINK_10); 1152 break; 1153 case DP83822_LED_FN_LINK_100_BTX: 1154 *rules = BIT(TRIGGER_NETDEV_LINK_100); 1155 break; 1156 case DP83822_LED_FN_FULL_DUPLEX: 1157 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX); 1158 break; 1159 case DP83822_LED_FN_TX: 1160 *rules = BIT(TRIGGER_NETDEV_TX); 1161 break; 1162 case DP83822_LED_FN_RX: 1163 *rules = BIT(TRIGGER_NETDEV_RX); 1164 break; 1165 case DP83822_LED_FN_RX_TX: 1166 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX); 1167 break; 1168 case DP83822_LED_FN_RX_TX_ERR: 1169 *rules = BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR); 1170 break; 1171 case DP83822_LED_FN_LINK_RX_TX: 1172 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | 1173 BIT(TRIGGER_NETDEV_RX); 1174 break; 1175 default: 1176 *rules = 0; 1177 break; 1178 } 1179 1180 return 0; 1181 } 1182 1183 #define DP83822_PHY_DRIVER(_id, _name) \ 1184 { \ 1185 PHY_ID_MATCH_MODEL(_id), \ 1186 .name = (_name), \ 1187 /* PHY_BASIC_FEATURES */ \ 1188 .probe = dp83822_probe, \ 1189 .soft_reset = dp83822_phy_reset, \ 1190 .config_init = dp83822_config_init, \ 1191 .read_status = dp83822_read_status, \ 1192 .get_wol = dp83822_get_wol, \ 1193 .set_wol = dp83822_set_wol, \ 1194 .config_intr = dp83822_config_intr, \ 1195 .handle_interrupt = dp83822_handle_interrupt, \ 1196 .suspend = dp83822_suspend, \ 1197 .resume = dp83822_resume, \ 1198 .led_hw_is_supported = dp83822_led_hw_is_supported, \ 1199 .led_hw_control_set = dp83822_led_hw_control_set, \ 1200 .led_hw_control_get = dp83822_led_hw_control_get, \ 1201 .attach_mdi_port = dp83822_attach_mdi_port \ 1202 } 1203 1204 #define DP83825_PHY_DRIVER(_id, _name) \ 1205 { \ 1206 PHY_ID_MATCH_MODEL(_id), \ 1207 .name = (_name), \ 1208 /* PHY_BASIC_FEATURES */ \ 1209 .probe = dp8382x_probe, \ 1210 .soft_reset = dp83822_phy_reset, \ 1211 .config_init = dp83825_config_init, \ 1212 .get_wol = dp83822_get_wol, \ 1213 .set_wol = dp83822_set_wol, \ 1214 .config_intr = dp83822_config_intr, \ 1215 .handle_interrupt = dp83822_handle_interrupt, \ 1216 .suspend = dp83822_suspend, \ 1217 .resume = dp83822_resume, \ 1218 } 1219 1220 #define DP83826_PHY_DRIVER(_id, _name) \ 1221 { \ 1222 PHY_ID_MATCH_MODEL(_id), \ 1223 .name = (_name), \ 1224 /* PHY_BASIC_FEATURES */ \ 1225 .probe = dp83826_probe, \ 1226 .soft_reset = dp83822_phy_reset, \ 1227 .config_init = dp83826_config_init, \ 1228 .get_wol = dp83822_get_wol, \ 1229 .set_wol = dp83822_set_wol, \ 1230 .config_intr = dp83822_config_intr, \ 1231 .handle_interrupt = dp83822_handle_interrupt, \ 1232 .suspend = dp83822_suspend, \ 1233 .resume = dp83822_resume, \ 1234 } 1235 1236 static struct phy_driver dp83822_driver[] = { 1237 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 1238 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 1239 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 1240 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 1241 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 1242 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 1243 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 1244 }; 1245 module_phy_driver(dp83822_driver); 1246 1247 static const struct mdio_device_id __maybe_unused dp83822_tbl[] = { 1248 { DP83822_PHY_ID, 0xfffffff0 }, 1249 { DP83825I_PHY_ID, 0xfffffff0 }, 1250 { DP83826C_PHY_ID, 0xfffffff0 }, 1251 { DP83826NC_PHY_ID, 0xfffffff0 }, 1252 { DP83825S_PHY_ID, 0xfffffff0 }, 1253 { DP83825CM_PHY_ID, 0xfffffff0 }, 1254 { DP83825CS_PHY_ID, 0xfffffff0 }, 1255 { }, 1256 }; 1257 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 1258 1259 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 1260 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 1261 MODULE_LICENSE("GPL v2"); 1262