1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 #include <linux/bitfield.h> 16 17 #define DP83822_PHY_ID 0x2000a240 18 #define DP83825S_PHY_ID 0x2000a140 19 #define DP83825I_PHY_ID 0x2000a150 20 #define DP83825CM_PHY_ID 0x2000a160 21 #define DP83825CS_PHY_ID 0x2000a170 22 #define DP83826C_PHY_ID 0x2000a130 23 #define DP83826NC_PHY_ID 0x2000a110 24 25 #define MII_DP83822_CTRL_2 0x0a 26 #define MII_DP83822_PHYSTS 0x10 27 #define MII_DP83822_PHYSCR 0x11 28 #define MII_DP83822_MISR1 0x12 29 #define MII_DP83822_MISR2 0x13 30 #define MII_DP83822_FCSCR 0x14 31 #define MII_DP83822_RCSR 0x17 32 #define MII_DP83822_RESET_CTRL 0x1f 33 #define MII_DP83822_GENCFG 0x465 34 #define MII_DP83822_SOR1 0x467 35 36 /* DP83826 specific registers */ 37 #define MII_DP83826_VOD_CFG1 0x30b 38 #define MII_DP83826_VOD_CFG2 0x30c 39 40 /* GENCFG */ 41 #define DP83822_SIG_DET_LOW BIT(0) 42 43 /* Control Register 2 bits */ 44 #define DP83822_FX_ENABLE BIT(14) 45 46 #define DP83822_SW_RESET BIT(15) 47 #define DP83822_DIG_RESTART BIT(14) 48 49 /* PHY STS bits */ 50 #define DP83822_PHYSTS_DUPLEX BIT(2) 51 #define DP83822_PHYSTS_10 BIT(1) 52 #define DP83822_PHYSTS_LINK BIT(0) 53 54 /* PHYSCR Register Fields */ 55 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 56 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 57 58 /* MISR1 bits */ 59 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 60 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 61 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 62 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 63 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 64 #define DP83822_LINK_STAT_INT_EN BIT(5) 65 #define DP83822_ENERGY_DET_INT_EN BIT(6) 66 #define DP83822_LINK_QUAL_INT_EN BIT(7) 67 68 /* MISR2 bits */ 69 #define DP83822_JABBER_DET_INT_EN BIT(0) 70 #define DP83822_WOL_PKT_INT_EN BIT(1) 71 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 72 #define DP83822_MDI_XOVER_INT_EN BIT(3) 73 #define DP83822_LB_FIFO_INT_EN BIT(4) 74 #define DP83822_PAGE_RX_INT_EN BIT(5) 75 #define DP83822_ANEG_ERR_INT_EN BIT(6) 76 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 77 78 /* INT_STAT1 bits */ 79 #define DP83822_WOL_INT_EN BIT(4) 80 #define DP83822_WOL_INT_STAT BIT(12) 81 82 #define MII_DP83822_RXSOP1 0x04a5 83 #define MII_DP83822_RXSOP2 0x04a6 84 #define MII_DP83822_RXSOP3 0x04a7 85 86 /* WoL Registers */ 87 #define MII_DP83822_WOL_CFG 0x04a0 88 #define MII_DP83822_WOL_STAT 0x04a1 89 #define MII_DP83822_WOL_DA1 0x04a2 90 #define MII_DP83822_WOL_DA2 0x04a3 91 #define MII_DP83822_WOL_DA3 0x04a4 92 93 /* WoL bits */ 94 #define DP83822_WOL_MAGIC_EN BIT(0) 95 #define DP83822_WOL_SECURE_ON BIT(5) 96 #define DP83822_WOL_EN BIT(7) 97 #define DP83822_WOL_INDICATION_SEL BIT(8) 98 #define DP83822_WOL_CLR_INDICATION BIT(11) 99 100 /* RCSR bits */ 101 #define DP83822_RMII_MODE_EN BIT(5) 102 #define DP83822_RMII_MODE_SEL BIT(7) 103 #define DP83822_RGMII_MODE_EN BIT(9) 104 #define DP83822_RX_CLK_SHIFT BIT(12) 105 #define DP83822_TX_CLK_SHIFT BIT(11) 106 107 /* SOR1 mode */ 108 #define DP83822_STRAP_MODE1 0 109 #define DP83822_STRAP_MODE2 BIT(0) 110 #define DP83822_STRAP_MODE3 BIT(1) 111 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 112 113 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 114 #define DP83822_COL_SHIFT 10 115 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 116 #define DP83822_RX_ER_SHIFT 8 117 118 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 119 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 120 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 121 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 122 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 123 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 124 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 125 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 126 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 127 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 128 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 129 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 130 131 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 132 ADVERTISED_FIBRE | \ 133 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 134 135 struct dp83822_private { 136 bool fx_signal_det_low; 137 int fx_enabled; 138 u16 fx_sd_enable; 139 u8 cfg_dac_minus; 140 u8 cfg_dac_plus; 141 struct ethtool_wolinfo wol; 142 }; 143 144 static int dp83822_config_wol(struct phy_device *phydev, 145 struct ethtool_wolinfo *wol) 146 { 147 struct net_device *ndev = phydev->attached_dev; 148 u16 value; 149 const u8 *mac; 150 151 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 152 mac = (const u8 *)ndev->dev_addr; 153 154 if (!is_valid_ether_addr(mac)) 155 return -EINVAL; 156 157 /* MAC addresses start with byte 5, but stored in mac[0]. 158 * 822 PHYs store bytes 4|5, 2|3, 0|1 159 */ 160 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, 161 (mac[1] << 8) | mac[0]); 162 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, 163 (mac[3] << 8) | mac[2]); 164 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, 165 (mac[5] << 8) | mac[4]); 166 167 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, 168 MII_DP83822_WOL_CFG); 169 if (wol->wolopts & WAKE_MAGIC) 170 value |= DP83822_WOL_MAGIC_EN; 171 else 172 value &= ~DP83822_WOL_MAGIC_EN; 173 174 if (wol->wolopts & WAKE_MAGICSECURE) { 175 phy_write_mmd(phydev, MDIO_MMD_VEND2, 176 MII_DP83822_RXSOP1, 177 (wol->sopass[1] << 8) | wol->sopass[0]); 178 phy_write_mmd(phydev, MDIO_MMD_VEND2, 179 MII_DP83822_RXSOP2, 180 (wol->sopass[3] << 8) | wol->sopass[2]); 181 phy_write_mmd(phydev, MDIO_MMD_VEND2, 182 MII_DP83822_RXSOP3, 183 (wol->sopass[5] << 8) | wol->sopass[4]); 184 value |= DP83822_WOL_SECURE_ON; 185 } else { 186 value &= ~DP83822_WOL_SECURE_ON; 187 } 188 189 /* Clear any pending WoL interrupt */ 190 phy_read(phydev, MII_DP83822_MISR2); 191 192 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 193 DP83822_WOL_CLR_INDICATION; 194 195 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 196 MII_DP83822_WOL_CFG, value); 197 } else { 198 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 199 MII_DP83822_WOL_CFG, 200 DP83822_WOL_EN | 201 DP83822_WOL_MAGIC_EN | 202 DP83822_WOL_SECURE_ON); 203 } 204 } 205 206 static int dp83822_set_wol(struct phy_device *phydev, 207 struct ethtool_wolinfo *wol) 208 { 209 struct dp83822_private *dp83822 = phydev->priv; 210 int ret; 211 212 ret = dp83822_config_wol(phydev, wol); 213 if (!ret) 214 memcpy(&dp83822->wol, wol, sizeof(*wol)); 215 return ret; 216 } 217 218 static void dp83822_get_wol(struct phy_device *phydev, 219 struct ethtool_wolinfo *wol) 220 { 221 int value; 222 u16 sopass_val; 223 224 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 225 wol->wolopts = 0; 226 227 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 228 229 if (value & DP83822_WOL_MAGIC_EN) 230 wol->wolopts |= WAKE_MAGIC; 231 232 if (value & DP83822_WOL_SECURE_ON) { 233 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 234 MII_DP83822_RXSOP1); 235 wol->sopass[0] = (sopass_val & 0xff); 236 wol->sopass[1] = (sopass_val >> 8); 237 238 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 239 MII_DP83822_RXSOP2); 240 wol->sopass[2] = (sopass_val & 0xff); 241 wol->sopass[3] = (sopass_val >> 8); 242 243 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 244 MII_DP83822_RXSOP3); 245 wol->sopass[4] = (sopass_val & 0xff); 246 wol->sopass[5] = (sopass_val >> 8); 247 248 wol->wolopts |= WAKE_MAGICSECURE; 249 } 250 251 /* WoL is not enabled so set wolopts to 0 */ 252 if (!(value & DP83822_WOL_EN)) 253 wol->wolopts = 0; 254 } 255 256 static int dp83822_config_intr(struct phy_device *phydev) 257 { 258 struct dp83822_private *dp83822 = phydev->priv; 259 int misr_status; 260 int physcr_status; 261 int err; 262 263 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 264 misr_status = phy_read(phydev, MII_DP83822_MISR1); 265 if (misr_status < 0) 266 return misr_status; 267 268 misr_status |= (DP83822_LINK_STAT_INT_EN | 269 DP83822_ENERGY_DET_INT_EN | 270 DP83822_LINK_QUAL_INT_EN); 271 272 if (!dp83822->fx_enabled) 273 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 274 DP83822_DUP_MODE_CHANGE_INT_EN | 275 DP83822_SPEED_CHANGED_INT_EN; 276 277 278 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 279 if (err < 0) 280 return err; 281 282 misr_status = phy_read(phydev, MII_DP83822_MISR2); 283 if (misr_status < 0) 284 return misr_status; 285 286 misr_status |= (DP83822_JABBER_DET_INT_EN | 287 DP83822_SLEEP_MODE_INT_EN | 288 DP83822_LB_FIFO_INT_EN | 289 DP83822_PAGE_RX_INT_EN | 290 DP83822_EEE_ERROR_CHANGE_INT_EN); 291 292 if (!dp83822->fx_enabled) 293 misr_status |= DP83822_ANEG_ERR_INT_EN | 294 DP83822_WOL_PKT_INT_EN; 295 296 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 297 if (err < 0) 298 return err; 299 300 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 301 if (physcr_status < 0) 302 return physcr_status; 303 304 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 305 306 } else { 307 err = phy_write(phydev, MII_DP83822_MISR1, 0); 308 if (err < 0) 309 return err; 310 311 err = phy_write(phydev, MII_DP83822_MISR2, 0); 312 if (err < 0) 313 return err; 314 315 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 316 if (physcr_status < 0) 317 return physcr_status; 318 319 physcr_status &= ~DP83822_PHYSCR_INTEN; 320 } 321 322 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 323 } 324 325 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 326 { 327 bool trigger_machine = false; 328 int irq_status; 329 330 /* The MISR1 and MISR2 registers are holding the interrupt status in 331 * the upper half (15:8), while the lower half (7:0) is used for 332 * controlling the interrupt enable state of those individual interrupt 333 * sources. To determine the possible interrupt sources, just read the 334 * MISR* register and use it directly to know which interrupts have 335 * been enabled previously or not. 336 */ 337 irq_status = phy_read(phydev, MII_DP83822_MISR1); 338 if (irq_status < 0) { 339 phy_error(phydev); 340 return IRQ_NONE; 341 } 342 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 343 trigger_machine = true; 344 345 irq_status = phy_read(phydev, MII_DP83822_MISR2); 346 if (irq_status < 0) { 347 phy_error(phydev); 348 return IRQ_NONE; 349 } 350 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 351 trigger_machine = true; 352 353 if (!trigger_machine) 354 return IRQ_NONE; 355 356 phy_trigger_machine(phydev); 357 358 return IRQ_HANDLED; 359 } 360 361 static int dp83822_read_status(struct phy_device *phydev) 362 { 363 struct dp83822_private *dp83822 = phydev->priv; 364 int status = phy_read(phydev, MII_DP83822_PHYSTS); 365 int ctrl2; 366 int ret; 367 368 if (dp83822->fx_enabled) { 369 if (status & DP83822_PHYSTS_LINK) { 370 phydev->speed = SPEED_UNKNOWN; 371 phydev->duplex = DUPLEX_UNKNOWN; 372 } else { 373 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 374 if (ctrl2 < 0) 375 return ctrl2; 376 377 if (!(ctrl2 & DP83822_FX_ENABLE)) { 378 ret = phy_write(phydev, MII_DP83822_CTRL_2, 379 DP83822_FX_ENABLE | ctrl2); 380 if (ret < 0) 381 return ret; 382 } 383 } 384 } 385 386 ret = genphy_read_status(phydev); 387 if (ret) 388 return ret; 389 390 if (status < 0) 391 return status; 392 393 if (status & DP83822_PHYSTS_DUPLEX) 394 phydev->duplex = DUPLEX_FULL; 395 else 396 phydev->duplex = DUPLEX_HALF; 397 398 if (status & DP83822_PHYSTS_10) 399 phydev->speed = SPEED_10; 400 else 401 phydev->speed = SPEED_100; 402 403 return 0; 404 } 405 406 static int dp83822_config_init(struct phy_device *phydev) 407 { 408 struct dp83822_private *dp83822 = phydev->priv; 409 struct device *dev = &phydev->mdio.dev; 410 int rgmii_delay = 0; 411 s32 rx_int_delay; 412 s32 tx_int_delay; 413 int err = 0; 414 int bmcr; 415 416 if (phy_interface_is_rgmii(phydev)) { 417 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 418 true); 419 420 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ 421 if (rx_int_delay > 0) 422 rgmii_delay |= DP83822_RX_CLK_SHIFT; 423 424 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 425 false); 426 427 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ 428 if (tx_int_delay <= 0) 429 rgmii_delay |= DP83822_TX_CLK_SHIFT; 430 431 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 432 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); 433 if (err) 434 return err; 435 436 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 437 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 438 439 if (err) 440 return err; 441 } else { 442 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 443 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 444 445 if (err) 446 return err; 447 } 448 449 if (dp83822->fx_enabled) { 450 err = phy_modify(phydev, MII_DP83822_CTRL_2, 451 DP83822_FX_ENABLE, 1); 452 if (err < 0) 453 return err; 454 455 /* Only allow advertising what this PHY supports */ 456 linkmode_and(phydev->advertising, phydev->advertising, 457 phydev->supported); 458 459 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 460 phydev->supported); 461 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 462 phydev->advertising); 463 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 464 phydev->supported); 465 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 466 phydev->supported); 467 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 468 phydev->advertising); 469 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 470 phydev->advertising); 471 472 /* Auto neg is not supported in fiber mode */ 473 bmcr = phy_read(phydev, MII_BMCR); 474 if (bmcr < 0) 475 return bmcr; 476 477 if (bmcr & BMCR_ANENABLE) { 478 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 479 if (err < 0) 480 return err; 481 } 482 phydev->autoneg = AUTONEG_DISABLE; 483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 484 phydev->supported); 485 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 486 phydev->advertising); 487 488 /* Setup fiber advertisement */ 489 err = phy_modify_changed(phydev, MII_ADVERTISE, 490 MII_DP83822_FIBER_ADVERTISE, 491 MII_DP83822_FIBER_ADVERTISE); 492 493 if (err < 0) 494 return err; 495 496 if (dp83822->fx_signal_det_low) { 497 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 498 MII_DP83822_GENCFG, 499 DP83822_SIG_DET_LOW); 500 if (err) 501 return err; 502 } 503 } 504 return dp83822_config_wol(phydev, &dp83822->wol); 505 } 506 507 static int dp8382x_config_rmii_mode(struct phy_device *phydev) 508 { 509 struct device *dev = &phydev->mdio.dev; 510 const char *of_val; 511 int ret; 512 513 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { 514 if (strcmp(of_val, "master") == 0) { 515 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 516 DP83822_RMII_MODE_SEL); 517 } else if (strcmp(of_val, "slave") == 0) { 518 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 519 DP83822_RMII_MODE_SEL); 520 } else { 521 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", 522 of_val); 523 ret = -EINVAL; 524 } 525 526 if (ret) 527 return ret; 528 } 529 530 return 0; 531 } 532 533 static int dp83826_config_init(struct phy_device *phydev) 534 { 535 struct dp83822_private *dp83822 = phydev->priv; 536 u16 val, mask; 537 int ret; 538 539 if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 540 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 541 DP83822_RMII_MODE_EN); 542 if (ret) 543 return ret; 544 545 ret = dp8382x_config_rmii_mode(phydev); 546 if (ret) 547 return ret; 548 } else { 549 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 550 DP83822_RMII_MODE_EN); 551 if (ret) 552 return ret; 553 } 554 555 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 556 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 557 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 558 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 559 dp83822->cfg_dac_minus)); 560 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 561 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val); 562 if (ret) 563 return ret; 564 565 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 566 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 567 dp83822->cfg_dac_minus)); 568 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 569 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 570 if (ret) 571 return ret; 572 } 573 574 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 575 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 576 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 577 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 578 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 579 if (ret) 580 return ret; 581 } 582 583 return dp83822_config_wol(phydev, &dp83822->wol); 584 } 585 586 static int dp83825_config_init(struct phy_device *phydev) 587 { 588 struct dp83822_private *dp83822 = phydev->priv; 589 int ret; 590 591 ret = dp8382x_config_rmii_mode(phydev); 592 if (ret) 593 return ret; 594 595 return dp83822_config_wol(phydev, &dp83822->wol); 596 } 597 598 static int dp83822_phy_reset(struct phy_device *phydev) 599 { 600 int err; 601 602 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 603 if (err < 0) 604 return err; 605 606 return phydev->drv->config_init(phydev); 607 } 608 609 #ifdef CONFIG_OF_MDIO 610 static int dp83822_of_init(struct phy_device *phydev) 611 { 612 struct dp83822_private *dp83822 = phydev->priv; 613 struct device *dev = &phydev->mdio.dev; 614 615 /* Signal detection for the PHY is only enabled if the FX_EN and the 616 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 617 * is strapped otherwise signal detection is disabled for the PHY. 618 */ 619 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 620 dp83822->fx_signal_det_low = device_property_present(dev, 621 "ti,link-loss-low"); 622 if (!dp83822->fx_enabled) 623 dp83822->fx_enabled = device_property_present(dev, 624 "ti,fiber-mode"); 625 626 return 0; 627 } 628 629 static int dp83826_to_dac_minus_one_regval(int percent) 630 { 631 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 632 633 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 634 } 635 636 static int dp83826_to_dac_plus_one_regval(int percent) 637 { 638 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 639 640 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 641 } 642 643 static void dp83826_of_init(struct phy_device *phydev) 644 { 645 struct dp83822_private *dp83822 = phydev->priv; 646 struct device *dev = &phydev->mdio.dev; 647 u32 val; 648 649 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 650 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 651 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 652 653 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 654 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 655 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 656 } 657 #else 658 static int dp83822_of_init(struct phy_device *phydev) 659 { 660 return 0; 661 } 662 663 static void dp83826_of_init(struct phy_device *phydev) 664 { 665 } 666 #endif /* CONFIG_OF_MDIO */ 667 668 static int dp83822_read_straps(struct phy_device *phydev) 669 { 670 struct dp83822_private *dp83822 = phydev->priv; 671 int fx_enabled, fx_sd_enable; 672 int val; 673 674 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1); 675 if (val < 0) 676 return val; 677 678 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 679 680 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 681 if (fx_enabled == DP83822_STRAP_MODE2 || 682 fx_enabled == DP83822_STRAP_MODE3) 683 dp83822->fx_enabled = 1; 684 685 if (dp83822->fx_enabled) { 686 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 687 if (fx_sd_enable == DP83822_STRAP_MODE3 || 688 fx_sd_enable == DP83822_STRAP_MODE4) 689 dp83822->fx_sd_enable = 1; 690 } 691 692 return 0; 693 } 694 695 static int dp8382x_probe(struct phy_device *phydev) 696 { 697 struct dp83822_private *dp83822; 698 699 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 700 GFP_KERNEL); 701 if (!dp83822) 702 return -ENOMEM; 703 704 phydev->priv = dp83822; 705 706 return 0; 707 } 708 709 static int dp83822_probe(struct phy_device *phydev) 710 { 711 struct dp83822_private *dp83822; 712 int ret; 713 714 ret = dp8382x_probe(phydev); 715 if (ret) 716 return ret; 717 718 dp83822 = phydev->priv; 719 720 ret = dp83822_read_straps(phydev); 721 if (ret) 722 return ret; 723 724 dp83822_of_init(phydev); 725 726 if (dp83822->fx_enabled) 727 phydev->port = PORT_FIBRE; 728 729 return 0; 730 } 731 732 static int dp83826_probe(struct phy_device *phydev) 733 { 734 int ret; 735 736 ret = dp8382x_probe(phydev); 737 if (ret) 738 return ret; 739 740 dp83826_of_init(phydev); 741 742 return 0; 743 } 744 745 static int dp83822_suspend(struct phy_device *phydev) 746 { 747 int value; 748 749 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 750 751 if (!(value & DP83822_WOL_EN)) 752 genphy_suspend(phydev); 753 754 return 0; 755 } 756 757 static int dp83822_resume(struct phy_device *phydev) 758 { 759 int value; 760 761 genphy_resume(phydev); 762 763 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 764 765 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | 766 DP83822_WOL_CLR_INDICATION); 767 768 return 0; 769 } 770 771 #define DP83822_PHY_DRIVER(_id, _name) \ 772 { \ 773 PHY_ID_MATCH_MODEL(_id), \ 774 .name = (_name), \ 775 /* PHY_BASIC_FEATURES */ \ 776 .probe = dp83822_probe, \ 777 .soft_reset = dp83822_phy_reset, \ 778 .config_init = dp83822_config_init, \ 779 .read_status = dp83822_read_status, \ 780 .get_wol = dp83822_get_wol, \ 781 .set_wol = dp83822_set_wol, \ 782 .config_intr = dp83822_config_intr, \ 783 .handle_interrupt = dp83822_handle_interrupt, \ 784 .suspend = dp83822_suspend, \ 785 .resume = dp83822_resume, \ 786 } 787 788 #define DP83825_PHY_DRIVER(_id, _name) \ 789 { \ 790 PHY_ID_MATCH_MODEL(_id), \ 791 .name = (_name), \ 792 /* PHY_BASIC_FEATURES */ \ 793 .probe = dp8382x_probe, \ 794 .soft_reset = dp83822_phy_reset, \ 795 .config_init = dp83825_config_init, \ 796 .get_wol = dp83822_get_wol, \ 797 .set_wol = dp83822_set_wol, \ 798 .config_intr = dp83822_config_intr, \ 799 .handle_interrupt = dp83822_handle_interrupt, \ 800 .suspend = dp83822_suspend, \ 801 .resume = dp83822_resume, \ 802 } 803 804 #define DP83826_PHY_DRIVER(_id, _name) \ 805 { \ 806 PHY_ID_MATCH_MODEL(_id), \ 807 .name = (_name), \ 808 /* PHY_BASIC_FEATURES */ \ 809 .probe = dp83826_probe, \ 810 .soft_reset = dp83822_phy_reset, \ 811 .config_init = dp83826_config_init, \ 812 .get_wol = dp83822_get_wol, \ 813 .set_wol = dp83822_set_wol, \ 814 .config_intr = dp83822_config_intr, \ 815 .handle_interrupt = dp83822_handle_interrupt, \ 816 .suspend = dp83822_suspend, \ 817 .resume = dp83822_resume, \ 818 } 819 820 static struct phy_driver dp83822_driver[] = { 821 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 822 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 823 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 824 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 825 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 826 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 827 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 828 }; 829 module_phy_driver(dp83822_driver); 830 831 static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 832 { DP83822_PHY_ID, 0xfffffff0 }, 833 { DP83825I_PHY_ID, 0xfffffff0 }, 834 { DP83826C_PHY_ID, 0xfffffff0 }, 835 { DP83826NC_PHY_ID, 0xfffffff0 }, 836 { DP83825S_PHY_ID, 0xfffffff0 }, 837 { DP83825CM_PHY_ID, 0xfffffff0 }, 838 { DP83825CS_PHY_ID, 0xfffffff0 }, 839 { }, 840 }; 841 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 842 843 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 844 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 845 MODULE_LICENSE("GPL v2"); 846