1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 #include <linux/bitfield.h> 16 17 #define DP83822_PHY_ID 0x2000a240 18 #define DP83825S_PHY_ID 0x2000a140 19 #define DP83825I_PHY_ID 0x2000a150 20 #define DP83825CM_PHY_ID 0x2000a160 21 #define DP83825CS_PHY_ID 0x2000a170 22 #define DP83826C_PHY_ID 0x2000a130 23 #define DP83826NC_PHY_ID 0x2000a110 24 25 #define DP83822_DEVADDR 0x1f 26 27 #define MII_DP83822_CTRL_2 0x0a 28 #define MII_DP83822_PHYSTS 0x10 29 #define MII_DP83822_PHYSCR 0x11 30 #define MII_DP83822_MISR1 0x12 31 #define MII_DP83822_MISR2 0x13 32 #define MII_DP83822_FCSCR 0x14 33 #define MII_DP83822_RCSR 0x17 34 #define MII_DP83822_RESET_CTRL 0x1f 35 #define MII_DP83822_GENCFG 0x465 36 #define MII_DP83822_SOR1 0x467 37 38 /* DP83826 specific registers */ 39 #define MII_DP83826_VOD_CFG1 0x30b 40 #define MII_DP83826_VOD_CFG2 0x30c 41 42 /* GENCFG */ 43 #define DP83822_SIG_DET_LOW BIT(0) 44 45 /* Control Register 2 bits */ 46 #define DP83822_FX_ENABLE BIT(14) 47 48 #define DP83822_HW_RESET BIT(15) 49 #define DP83822_SW_RESET BIT(14) 50 51 /* PHY STS bits */ 52 #define DP83822_PHYSTS_DUPLEX BIT(2) 53 #define DP83822_PHYSTS_10 BIT(1) 54 #define DP83822_PHYSTS_LINK BIT(0) 55 56 /* PHYSCR Register Fields */ 57 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 58 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 59 60 /* MISR1 bits */ 61 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 62 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 63 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 64 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 65 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 66 #define DP83822_LINK_STAT_INT_EN BIT(5) 67 #define DP83822_ENERGY_DET_INT_EN BIT(6) 68 #define DP83822_LINK_QUAL_INT_EN BIT(7) 69 70 /* MISR2 bits */ 71 #define DP83822_JABBER_DET_INT_EN BIT(0) 72 #define DP83822_WOL_PKT_INT_EN BIT(1) 73 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 74 #define DP83822_MDI_XOVER_INT_EN BIT(3) 75 #define DP83822_LB_FIFO_INT_EN BIT(4) 76 #define DP83822_PAGE_RX_INT_EN BIT(5) 77 #define DP83822_ANEG_ERR_INT_EN BIT(6) 78 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 79 80 /* INT_STAT1 bits */ 81 #define DP83822_WOL_INT_EN BIT(4) 82 #define DP83822_WOL_INT_STAT BIT(12) 83 84 #define MII_DP83822_RXSOP1 0x04a5 85 #define MII_DP83822_RXSOP2 0x04a6 86 #define MII_DP83822_RXSOP3 0x04a7 87 88 /* WoL Registers */ 89 #define MII_DP83822_WOL_CFG 0x04a0 90 #define MII_DP83822_WOL_STAT 0x04a1 91 #define MII_DP83822_WOL_DA1 0x04a2 92 #define MII_DP83822_WOL_DA2 0x04a3 93 #define MII_DP83822_WOL_DA3 0x04a4 94 95 /* WoL bits */ 96 #define DP83822_WOL_MAGIC_EN BIT(0) 97 #define DP83822_WOL_SECURE_ON BIT(5) 98 #define DP83822_WOL_EN BIT(7) 99 #define DP83822_WOL_INDICATION_SEL BIT(8) 100 #define DP83822_WOL_CLR_INDICATION BIT(11) 101 102 /* RCSR bits */ 103 #define DP83822_RGMII_MODE_EN BIT(9) 104 #define DP83822_RX_CLK_SHIFT BIT(12) 105 #define DP83822_TX_CLK_SHIFT BIT(11) 106 107 /* SOR1 mode */ 108 #define DP83822_STRAP_MODE1 0 109 #define DP83822_STRAP_MODE2 BIT(0) 110 #define DP83822_STRAP_MODE3 BIT(1) 111 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 112 113 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 114 #define DP83822_COL_SHIFT 10 115 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 116 #define DP83822_RX_ER_SHIFT 8 117 118 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 119 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 120 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 121 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 122 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 123 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 124 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 125 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 126 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 127 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 128 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 129 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 130 131 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 132 ADVERTISED_FIBRE | \ 133 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 134 135 struct dp83822_private { 136 bool fx_signal_det_low; 137 int fx_enabled; 138 u16 fx_sd_enable; 139 u8 cfg_dac_minus; 140 u8 cfg_dac_plus; 141 }; 142 143 static int dp83822_set_wol(struct phy_device *phydev, 144 struct ethtool_wolinfo *wol) 145 { 146 struct net_device *ndev = phydev->attached_dev; 147 u16 value; 148 const u8 *mac; 149 150 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 151 mac = (const u8 *)ndev->dev_addr; 152 153 if (!is_valid_ether_addr(mac)) 154 return -EINVAL; 155 156 /* MAC addresses start with byte 5, but stored in mac[0]. 157 * 822 PHYs store bytes 4|5, 2|3, 0|1 158 */ 159 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, 160 (mac[1] << 8) | mac[0]); 161 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, 162 (mac[3] << 8) | mac[2]); 163 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, 164 (mac[5] << 8) | mac[4]); 165 166 value = phy_read_mmd(phydev, DP83822_DEVADDR, 167 MII_DP83822_WOL_CFG); 168 if (wol->wolopts & WAKE_MAGIC) 169 value |= DP83822_WOL_MAGIC_EN; 170 else 171 value &= ~DP83822_WOL_MAGIC_EN; 172 173 if (wol->wolopts & WAKE_MAGICSECURE) { 174 phy_write_mmd(phydev, DP83822_DEVADDR, 175 MII_DP83822_RXSOP1, 176 (wol->sopass[1] << 8) | wol->sopass[0]); 177 phy_write_mmd(phydev, DP83822_DEVADDR, 178 MII_DP83822_RXSOP2, 179 (wol->sopass[3] << 8) | wol->sopass[2]); 180 phy_write_mmd(phydev, DP83822_DEVADDR, 181 MII_DP83822_RXSOP3, 182 (wol->sopass[5] << 8) | wol->sopass[4]); 183 value |= DP83822_WOL_SECURE_ON; 184 } else { 185 value &= ~DP83822_WOL_SECURE_ON; 186 } 187 188 /* Clear any pending WoL interrupt */ 189 phy_read(phydev, MII_DP83822_MISR2); 190 191 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 192 DP83822_WOL_CLR_INDICATION; 193 194 return phy_write_mmd(phydev, DP83822_DEVADDR, 195 MII_DP83822_WOL_CFG, value); 196 } else { 197 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 198 MII_DP83822_WOL_CFG, DP83822_WOL_EN); 199 } 200 } 201 202 static void dp83822_get_wol(struct phy_device *phydev, 203 struct ethtool_wolinfo *wol) 204 { 205 int value; 206 u16 sopass_val; 207 208 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 209 wol->wolopts = 0; 210 211 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 212 213 if (value & DP83822_WOL_MAGIC_EN) 214 wol->wolopts |= WAKE_MAGIC; 215 216 if (value & DP83822_WOL_SECURE_ON) { 217 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 218 MII_DP83822_RXSOP1); 219 wol->sopass[0] = (sopass_val & 0xff); 220 wol->sopass[1] = (sopass_val >> 8); 221 222 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 223 MII_DP83822_RXSOP2); 224 wol->sopass[2] = (sopass_val & 0xff); 225 wol->sopass[3] = (sopass_val >> 8); 226 227 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 228 MII_DP83822_RXSOP3); 229 wol->sopass[4] = (sopass_val & 0xff); 230 wol->sopass[5] = (sopass_val >> 8); 231 232 wol->wolopts |= WAKE_MAGICSECURE; 233 } 234 235 /* WoL is not enabled so set wolopts to 0 */ 236 if (!(value & DP83822_WOL_EN)) 237 wol->wolopts = 0; 238 } 239 240 static int dp83822_config_intr(struct phy_device *phydev) 241 { 242 struct dp83822_private *dp83822 = phydev->priv; 243 int misr_status; 244 int physcr_status; 245 int err; 246 247 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 248 misr_status = phy_read(phydev, MII_DP83822_MISR1); 249 if (misr_status < 0) 250 return misr_status; 251 252 misr_status |= (DP83822_LINK_STAT_INT_EN | 253 DP83822_ENERGY_DET_INT_EN | 254 DP83822_LINK_QUAL_INT_EN); 255 256 /* Private data pointer is NULL on DP83825 */ 257 if (!dp83822 || !dp83822->fx_enabled) 258 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 259 DP83822_DUP_MODE_CHANGE_INT_EN | 260 DP83822_SPEED_CHANGED_INT_EN; 261 262 263 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 264 if (err < 0) 265 return err; 266 267 misr_status = phy_read(phydev, MII_DP83822_MISR2); 268 if (misr_status < 0) 269 return misr_status; 270 271 misr_status |= (DP83822_JABBER_DET_INT_EN | 272 DP83822_SLEEP_MODE_INT_EN | 273 DP83822_LB_FIFO_INT_EN | 274 DP83822_PAGE_RX_INT_EN | 275 DP83822_EEE_ERROR_CHANGE_INT_EN); 276 277 /* Private data pointer is NULL on DP83825 */ 278 if (!dp83822 || !dp83822->fx_enabled) 279 misr_status |= DP83822_ANEG_ERR_INT_EN | 280 DP83822_WOL_PKT_INT_EN; 281 282 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 283 if (err < 0) 284 return err; 285 286 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 287 if (physcr_status < 0) 288 return physcr_status; 289 290 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 291 292 } else { 293 err = phy_write(phydev, MII_DP83822_MISR1, 0); 294 if (err < 0) 295 return err; 296 297 err = phy_write(phydev, MII_DP83822_MISR2, 0); 298 if (err < 0) 299 return err; 300 301 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 302 if (physcr_status < 0) 303 return physcr_status; 304 305 physcr_status &= ~DP83822_PHYSCR_INTEN; 306 } 307 308 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 309 } 310 311 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 312 { 313 bool trigger_machine = false; 314 int irq_status; 315 316 /* The MISR1 and MISR2 registers are holding the interrupt status in 317 * the upper half (15:8), while the lower half (7:0) is used for 318 * controlling the interrupt enable state of those individual interrupt 319 * sources. To determine the possible interrupt sources, just read the 320 * MISR* register and use it directly to know which interrupts have 321 * been enabled previously or not. 322 */ 323 irq_status = phy_read(phydev, MII_DP83822_MISR1); 324 if (irq_status < 0) { 325 phy_error(phydev); 326 return IRQ_NONE; 327 } 328 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 329 trigger_machine = true; 330 331 irq_status = phy_read(phydev, MII_DP83822_MISR2); 332 if (irq_status < 0) { 333 phy_error(phydev); 334 return IRQ_NONE; 335 } 336 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 337 trigger_machine = true; 338 339 if (!trigger_machine) 340 return IRQ_NONE; 341 342 phy_trigger_machine(phydev); 343 344 return IRQ_HANDLED; 345 } 346 347 static int dp8382x_disable_wol(struct phy_device *phydev) 348 { 349 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, 350 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | 351 DP83822_WOL_SECURE_ON); 352 } 353 354 static int dp83822_read_status(struct phy_device *phydev) 355 { 356 struct dp83822_private *dp83822 = phydev->priv; 357 int status = phy_read(phydev, MII_DP83822_PHYSTS); 358 int ctrl2; 359 int ret; 360 361 if (dp83822->fx_enabled) { 362 if (status & DP83822_PHYSTS_LINK) { 363 phydev->speed = SPEED_UNKNOWN; 364 phydev->duplex = DUPLEX_UNKNOWN; 365 } else { 366 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 367 if (ctrl2 < 0) 368 return ctrl2; 369 370 if (!(ctrl2 & DP83822_FX_ENABLE)) { 371 ret = phy_write(phydev, MII_DP83822_CTRL_2, 372 DP83822_FX_ENABLE | ctrl2); 373 if (ret < 0) 374 return ret; 375 } 376 } 377 } 378 379 ret = genphy_read_status(phydev); 380 if (ret) 381 return ret; 382 383 if (status < 0) 384 return status; 385 386 if (status & DP83822_PHYSTS_DUPLEX) 387 phydev->duplex = DUPLEX_FULL; 388 else 389 phydev->duplex = DUPLEX_HALF; 390 391 if (status & DP83822_PHYSTS_10) 392 phydev->speed = SPEED_10; 393 else 394 phydev->speed = SPEED_100; 395 396 return 0; 397 } 398 399 static int dp83822_config_init(struct phy_device *phydev) 400 { 401 struct dp83822_private *dp83822 = phydev->priv; 402 struct device *dev = &phydev->mdio.dev; 403 int rgmii_delay; 404 s32 rx_int_delay; 405 s32 tx_int_delay; 406 int err = 0; 407 int bmcr; 408 409 if (phy_interface_is_rgmii(phydev)) { 410 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 411 true); 412 413 if (rx_int_delay <= 0) 414 rgmii_delay = 0; 415 else 416 rgmii_delay = DP83822_RX_CLK_SHIFT; 417 418 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 419 false); 420 if (tx_int_delay <= 0) 421 rgmii_delay &= ~DP83822_TX_CLK_SHIFT; 422 else 423 rgmii_delay |= DP83822_TX_CLK_SHIFT; 424 425 if (rgmii_delay) { 426 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 427 MII_DP83822_RCSR, rgmii_delay); 428 if (err) 429 return err; 430 } 431 432 phy_set_bits_mmd(phydev, DP83822_DEVADDR, 433 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 434 } else { 435 phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 436 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 437 } 438 439 if (dp83822->fx_enabled) { 440 err = phy_modify(phydev, MII_DP83822_CTRL_2, 441 DP83822_FX_ENABLE, 1); 442 if (err < 0) 443 return err; 444 445 /* Only allow advertising what this PHY supports */ 446 linkmode_and(phydev->advertising, phydev->advertising, 447 phydev->supported); 448 449 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 450 phydev->supported); 451 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 452 phydev->advertising); 453 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 454 phydev->supported); 455 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 456 phydev->supported); 457 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 458 phydev->advertising); 459 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 460 phydev->advertising); 461 462 /* Auto neg is not supported in fiber mode */ 463 bmcr = phy_read(phydev, MII_BMCR); 464 if (bmcr < 0) 465 return bmcr; 466 467 if (bmcr & BMCR_ANENABLE) { 468 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 469 if (err < 0) 470 return err; 471 } 472 phydev->autoneg = AUTONEG_DISABLE; 473 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 474 phydev->supported); 475 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 476 phydev->advertising); 477 478 /* Setup fiber advertisement */ 479 err = phy_modify_changed(phydev, MII_ADVERTISE, 480 MII_DP83822_FIBER_ADVERTISE, 481 MII_DP83822_FIBER_ADVERTISE); 482 483 if (err < 0) 484 return err; 485 486 if (dp83822->fx_signal_det_low) { 487 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 488 MII_DP83822_GENCFG, 489 DP83822_SIG_DET_LOW); 490 if (err) 491 return err; 492 } 493 } 494 return dp8382x_disable_wol(phydev); 495 } 496 497 static int dp83826_config_init(struct phy_device *phydev) 498 { 499 struct dp83822_private *dp83822 = phydev->priv; 500 u16 val, mask; 501 int ret; 502 503 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 504 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 505 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 506 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 507 dp83822->cfg_dac_minus)); 508 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 509 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val); 510 if (ret) 511 return ret; 512 513 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 514 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 515 dp83822->cfg_dac_minus)); 516 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 517 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val); 518 if (ret) 519 return ret; 520 } 521 522 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 523 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 524 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 525 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 526 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val); 527 if (ret) 528 return ret; 529 } 530 531 return 0; 532 } 533 534 static int dp8382x_config_init(struct phy_device *phydev) 535 { 536 return dp8382x_disable_wol(phydev); 537 } 538 539 static int dp83822_phy_reset(struct phy_device *phydev) 540 { 541 int err; 542 543 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 544 if (err < 0) 545 return err; 546 547 return phydev->drv->config_init(phydev); 548 } 549 550 #ifdef CONFIG_OF_MDIO 551 static int dp83822_of_init(struct phy_device *phydev) 552 { 553 struct dp83822_private *dp83822 = phydev->priv; 554 struct device *dev = &phydev->mdio.dev; 555 556 /* Signal detection for the PHY is only enabled if the FX_EN and the 557 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 558 * is strapped otherwise signal detection is disabled for the PHY. 559 */ 560 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 561 dp83822->fx_signal_det_low = device_property_present(dev, 562 "ti,link-loss-low"); 563 if (!dp83822->fx_enabled) 564 dp83822->fx_enabled = device_property_present(dev, 565 "ti,fiber-mode"); 566 567 return 0; 568 } 569 570 static int dp83826_to_dac_minus_one_regval(int percent) 571 { 572 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 573 574 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 575 } 576 577 static int dp83826_to_dac_plus_one_regval(int percent) 578 { 579 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 580 581 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 582 } 583 584 static void dp83826_of_init(struct phy_device *phydev) 585 { 586 struct dp83822_private *dp83822 = phydev->priv; 587 struct device *dev = &phydev->mdio.dev; 588 u32 val; 589 590 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 591 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 592 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 593 594 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 595 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 596 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 597 } 598 #else 599 static int dp83822_of_init(struct phy_device *phydev) 600 { 601 return 0; 602 } 603 604 static void dp83826_of_init(struct phy_device *phydev) 605 { 606 } 607 #endif /* CONFIG_OF_MDIO */ 608 609 static int dp83822_read_straps(struct phy_device *phydev) 610 { 611 struct dp83822_private *dp83822 = phydev->priv; 612 int fx_enabled, fx_sd_enable; 613 int val; 614 615 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1); 616 if (val < 0) 617 return val; 618 619 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 620 621 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 622 if (fx_enabled == DP83822_STRAP_MODE2 || 623 fx_enabled == DP83822_STRAP_MODE3) 624 dp83822->fx_enabled = 1; 625 626 if (dp83822->fx_enabled) { 627 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 628 if (fx_sd_enable == DP83822_STRAP_MODE3 || 629 fx_sd_enable == DP83822_STRAP_MODE4) 630 dp83822->fx_sd_enable = 1; 631 } 632 633 return 0; 634 } 635 636 static int dp83822_probe(struct phy_device *phydev) 637 { 638 struct dp83822_private *dp83822; 639 int ret; 640 641 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 642 GFP_KERNEL); 643 if (!dp83822) 644 return -ENOMEM; 645 646 phydev->priv = dp83822; 647 648 ret = dp83822_read_straps(phydev); 649 if (ret) 650 return ret; 651 652 dp83822_of_init(phydev); 653 654 if (dp83822->fx_enabled) 655 phydev->port = PORT_FIBRE; 656 657 return 0; 658 } 659 660 static int dp83826_probe(struct phy_device *phydev) 661 { 662 struct dp83822_private *dp83822; 663 664 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 665 GFP_KERNEL); 666 if (!dp83822) 667 return -ENOMEM; 668 669 phydev->priv = dp83822; 670 671 dp83826_of_init(phydev); 672 673 return 0; 674 } 675 676 static int dp83822_suspend(struct phy_device *phydev) 677 { 678 int value; 679 680 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 681 682 if (!(value & DP83822_WOL_EN)) 683 genphy_suspend(phydev); 684 685 return 0; 686 } 687 688 static int dp83822_resume(struct phy_device *phydev) 689 { 690 int value; 691 692 genphy_resume(phydev); 693 694 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 695 696 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | 697 DP83822_WOL_CLR_INDICATION); 698 699 return 0; 700 } 701 702 #define DP83822_PHY_DRIVER(_id, _name) \ 703 { \ 704 PHY_ID_MATCH_MODEL(_id), \ 705 .name = (_name), \ 706 /* PHY_BASIC_FEATURES */ \ 707 .probe = dp83822_probe, \ 708 .soft_reset = dp83822_phy_reset, \ 709 .config_init = dp83822_config_init, \ 710 .read_status = dp83822_read_status, \ 711 .get_wol = dp83822_get_wol, \ 712 .set_wol = dp83822_set_wol, \ 713 .config_intr = dp83822_config_intr, \ 714 .handle_interrupt = dp83822_handle_interrupt, \ 715 .suspend = dp83822_suspend, \ 716 .resume = dp83822_resume, \ 717 } 718 719 #define DP83826_PHY_DRIVER(_id, _name) \ 720 { \ 721 PHY_ID_MATCH_MODEL(_id), \ 722 .name = (_name), \ 723 /* PHY_BASIC_FEATURES */ \ 724 .probe = dp83826_probe, \ 725 .soft_reset = dp83822_phy_reset, \ 726 .config_init = dp83826_config_init, \ 727 .get_wol = dp83822_get_wol, \ 728 .set_wol = dp83822_set_wol, \ 729 .config_intr = dp83822_config_intr, \ 730 .handle_interrupt = dp83822_handle_interrupt, \ 731 .suspend = dp83822_suspend, \ 732 .resume = dp83822_resume, \ 733 } 734 735 #define DP8382X_PHY_DRIVER(_id, _name) \ 736 { \ 737 PHY_ID_MATCH_MODEL(_id), \ 738 .name = (_name), \ 739 /* PHY_BASIC_FEATURES */ \ 740 .soft_reset = dp83822_phy_reset, \ 741 .config_init = dp8382x_config_init, \ 742 .get_wol = dp83822_get_wol, \ 743 .set_wol = dp83822_set_wol, \ 744 .config_intr = dp83822_config_intr, \ 745 .handle_interrupt = dp83822_handle_interrupt, \ 746 .suspend = dp83822_suspend, \ 747 .resume = dp83822_resume, \ 748 } 749 750 static struct phy_driver dp83822_driver[] = { 751 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 752 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 753 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 754 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 755 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 756 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 757 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 758 }; 759 module_phy_driver(dp83822_driver); 760 761 static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 762 { DP83822_PHY_ID, 0xfffffff0 }, 763 { DP83825I_PHY_ID, 0xfffffff0 }, 764 { DP83826C_PHY_ID, 0xfffffff0 }, 765 { DP83826NC_PHY_ID, 0xfffffff0 }, 766 { DP83825S_PHY_ID, 0xfffffff0 }, 767 { DP83825CM_PHY_ID, 0xfffffff0 }, 768 { DP83825CS_PHY_ID, 0xfffffff0 }, 769 { }, 770 }; 771 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 772 773 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 774 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 775 MODULE_LICENSE("GPL v2"); 776