1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 #include <linux/bitfield.h> 16 17 #define DP83822_PHY_ID 0x2000a240 18 #define DP83825S_PHY_ID 0x2000a140 19 #define DP83825I_PHY_ID 0x2000a150 20 #define DP83825CM_PHY_ID 0x2000a160 21 #define DP83825CS_PHY_ID 0x2000a170 22 #define DP83826C_PHY_ID 0x2000a130 23 #define DP83826NC_PHY_ID 0x2000a110 24 25 #define MII_DP83822_CTRL_2 0x0a 26 #define MII_DP83822_PHYSTS 0x10 27 #define MII_DP83822_PHYSCR 0x11 28 #define MII_DP83822_MISR1 0x12 29 #define MII_DP83822_MISR2 0x13 30 #define MII_DP83822_FCSCR 0x14 31 #define MII_DP83822_RCSR 0x17 32 #define MII_DP83822_RESET_CTRL 0x1f 33 #define MII_DP83822_MLEDCR 0x25 34 #define MII_DP83822_LEDCFG1 0x460 35 #define MII_DP83822_IOCTRL1 0x462 36 #define MII_DP83822_IOCTRL2 0x463 37 #define MII_DP83822_GENCFG 0x465 38 #define MII_DP83822_SOR1 0x467 39 40 /* DP83826 specific registers */ 41 #define MII_DP83826_VOD_CFG1 0x30b 42 #define MII_DP83826_VOD_CFG2 0x30c 43 44 /* GENCFG */ 45 #define DP83822_SIG_DET_LOW BIT(0) 46 47 /* Control Register 2 bits */ 48 #define DP83822_FX_ENABLE BIT(14) 49 50 #define DP83822_SW_RESET BIT(15) 51 #define DP83822_DIG_RESTART BIT(14) 52 53 /* PHY STS bits */ 54 #define DP83822_PHYSTS_DUPLEX BIT(2) 55 #define DP83822_PHYSTS_10 BIT(1) 56 #define DP83822_PHYSTS_LINK BIT(0) 57 58 /* PHYSCR Register Fields */ 59 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 60 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 61 62 /* MISR1 bits */ 63 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 64 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 65 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 66 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 67 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 68 #define DP83822_LINK_STAT_INT_EN BIT(5) 69 #define DP83822_ENERGY_DET_INT_EN BIT(6) 70 #define DP83822_LINK_QUAL_INT_EN BIT(7) 71 72 /* MISR2 bits */ 73 #define DP83822_JABBER_DET_INT_EN BIT(0) 74 #define DP83822_WOL_PKT_INT_EN BIT(1) 75 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 76 #define DP83822_MDI_XOVER_INT_EN BIT(3) 77 #define DP83822_LB_FIFO_INT_EN BIT(4) 78 #define DP83822_PAGE_RX_INT_EN BIT(5) 79 #define DP83822_ANEG_ERR_INT_EN BIT(6) 80 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 81 82 /* INT_STAT1 bits */ 83 #define DP83822_WOL_INT_EN BIT(4) 84 #define DP83822_WOL_INT_STAT BIT(12) 85 86 #define MII_DP83822_RXSOP1 0x04a5 87 #define MII_DP83822_RXSOP2 0x04a6 88 #define MII_DP83822_RXSOP3 0x04a7 89 90 /* WoL Registers */ 91 #define MII_DP83822_WOL_CFG 0x04a0 92 #define MII_DP83822_WOL_STAT 0x04a1 93 #define MII_DP83822_WOL_DA1 0x04a2 94 #define MII_DP83822_WOL_DA2 0x04a3 95 #define MII_DP83822_WOL_DA3 0x04a4 96 97 /* WoL bits */ 98 #define DP83822_WOL_MAGIC_EN BIT(0) 99 #define DP83822_WOL_SECURE_ON BIT(5) 100 #define DP83822_WOL_EN BIT(7) 101 #define DP83822_WOL_INDICATION_SEL BIT(8) 102 #define DP83822_WOL_CLR_INDICATION BIT(11) 103 104 /* RCSR bits */ 105 #define DP83822_RMII_MODE_EN BIT(5) 106 #define DP83822_RMII_MODE_SEL BIT(7) 107 #define DP83822_RGMII_MODE_EN BIT(9) 108 #define DP83822_RX_CLK_SHIFT BIT(12) 109 #define DP83822_TX_CLK_SHIFT BIT(11) 110 111 /* MLEDCR bits */ 112 #define DP83822_MLEDCR_CFG GENMASK(6, 3) 113 #define DP83822_MLEDCR_ROUTE GENMASK(1, 0) 114 #define DP83822_MLEDCR_ROUTE_LED_0 DP83822_MLEDCR_ROUTE 115 116 /* LEDCFG1 bits */ 117 #define DP83822_LEDCFG1_LED1_CTRL GENMASK(11, 8) 118 #define DP83822_LEDCFG1_LED3_CTRL GENMASK(7, 4) 119 120 /* IOCTRL1 bits */ 121 #define DP83822_IOCTRL1_GPIO3_CTRL GENMASK(10, 8) 122 #define DP83822_IOCTRL1_GPIO3_CTRL_LED3 BIT(0) 123 #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0) 124 #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0) 125 126 /* IOCTRL2 bits */ 127 #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4) 128 #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0) 129 #define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0) 130 #define DP83822_IOCTRL2_GPIO2_CTRL_MLED BIT(0) 131 132 #define DP83822_CLK_SRC_MAC_IF 0x0 133 #define DP83822_CLK_SRC_XI 0x1 134 #define DP83822_CLK_SRC_INT_REF 0x2 135 #define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4 136 #define DP83822_CLK_SRC_FREE_RUNNING 0x6 137 #define DP83822_CLK_SRC_RECOVERED 0x7 138 139 #define DP83822_LED_FN_LINK 0x0 /* Link established */ 140 #define DP83822_LED_FN_RX_TX 0x1 /* Receive or Transmit activity */ 141 #define DP83822_LED_FN_TX 0x2 /* Transmit activity */ 142 #define DP83822_LED_FN_RX 0x3 /* Receive activity */ 143 #define DP83822_LED_FN_COLLISION 0x4 /* Collision detected */ 144 #define DP83822_LED_FN_LINK_100_BTX 0x5 /* 100 BTX link established */ 145 #define DP83822_LED_FN_LINK_10_BT 0x6 /* 10BT link established */ 146 #define DP83822_LED_FN_FULL_DUPLEX 0x7 /* Full duplex */ 147 #define DP83822_LED_FN_LINK_RX_TX 0x8 /* Link established, blink for rx or tx activity */ 148 #define DP83822_LED_FN_ACTIVE_STRETCH 0x9 /* Active Stretch Signal */ 149 #define DP83822_LED_FN_MII_LINK 0xa /* MII LINK (100BT+FD) */ 150 #define DP83822_LED_FN_LPI_MODE 0xb /* LPI Mode (EEE) */ 151 #define DP83822_LED_FN_RX_TX_ERR 0xc /* TX/RX MII Error */ 152 #define DP83822_LED_FN_LINK_LOST 0xd /* Link Lost */ 153 #define DP83822_LED_FN_PRBS_ERR 0xe /* Blink for PRBS error */ 154 155 /* SOR1 mode */ 156 #define DP83822_STRAP_MODE1 0 157 #define DP83822_STRAP_MODE2 BIT(0) 158 #define DP83822_STRAP_MODE3 BIT(1) 159 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 160 161 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 162 #define DP83822_COL_SHIFT 10 163 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 164 #define DP83822_RX_ER_SHIFT 8 165 166 /* DP83826: VOD_CFG1 & VOD_CFG2 */ 167 #define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12) 168 #define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6) 169 #define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12) 170 #define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6) 171 #define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0) 172 #define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4) 173 #define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0) 174 #define DP83826_CFG_DAC_PERCENT_PER_STEP 625 175 #define DP83826_CFG_DAC_PERCENT_DEFAULT 10000 176 #define DP83826_CFG_DAC_MINUS_DEFAULT 0x30 177 #define DP83826_CFG_DAC_PLUS_DEFAULT 0x10 178 179 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 180 ADVERTISED_FIBRE | \ 181 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 182 183 #define DP83822_MAX_LED_PINS 4 184 185 #define DP83822_LED_INDEX_LED_0 0 186 #define DP83822_LED_INDEX_LED_1_GPIO1 1 187 #define DP83822_LED_INDEX_COL_GPIO2 2 188 #define DP83822_LED_INDEX_RX_D3_GPIO3 3 189 190 struct dp83822_private { 191 bool fx_signal_det_low; 192 int fx_enabled; 193 u16 fx_sd_enable; 194 u8 cfg_dac_minus; 195 u8 cfg_dac_plus; 196 struct ethtool_wolinfo wol; 197 bool set_gpio2_clk_out; 198 u32 gpio2_clk_out; 199 bool led_pin_enable[DP83822_MAX_LED_PINS]; 200 }; 201 202 static int dp83822_config_wol(struct phy_device *phydev, 203 struct ethtool_wolinfo *wol) 204 { 205 struct net_device *ndev = phydev->attached_dev; 206 u16 value; 207 const u8 *mac; 208 209 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 210 mac = (const u8 *)ndev->dev_addr; 211 212 if (!is_valid_ether_addr(mac)) 213 return -EINVAL; 214 215 /* MAC addresses start with byte 5, but stored in mac[0]. 216 * 822 PHYs store bytes 4|5, 2|3, 0|1 217 */ 218 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, 219 (mac[1] << 8) | mac[0]); 220 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, 221 (mac[3] << 8) | mac[2]); 222 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, 223 (mac[5] << 8) | mac[4]); 224 225 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, 226 MII_DP83822_WOL_CFG); 227 if (wol->wolopts & WAKE_MAGIC) 228 value |= DP83822_WOL_MAGIC_EN; 229 else 230 value &= ~DP83822_WOL_MAGIC_EN; 231 232 if (wol->wolopts & WAKE_MAGICSECURE) { 233 phy_write_mmd(phydev, MDIO_MMD_VEND2, 234 MII_DP83822_RXSOP1, 235 (wol->sopass[1] << 8) | wol->sopass[0]); 236 phy_write_mmd(phydev, MDIO_MMD_VEND2, 237 MII_DP83822_RXSOP2, 238 (wol->sopass[3] << 8) | wol->sopass[2]); 239 phy_write_mmd(phydev, MDIO_MMD_VEND2, 240 MII_DP83822_RXSOP3, 241 (wol->sopass[5] << 8) | wol->sopass[4]); 242 value |= DP83822_WOL_SECURE_ON; 243 } else { 244 value &= ~DP83822_WOL_SECURE_ON; 245 } 246 247 /* Clear any pending WoL interrupt */ 248 phy_read(phydev, MII_DP83822_MISR2); 249 250 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 251 DP83822_WOL_CLR_INDICATION; 252 253 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 254 MII_DP83822_WOL_CFG, value); 255 } else { 256 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 257 MII_DP83822_WOL_CFG, 258 DP83822_WOL_EN | 259 DP83822_WOL_MAGIC_EN | 260 DP83822_WOL_SECURE_ON); 261 } 262 } 263 264 static int dp83822_set_wol(struct phy_device *phydev, 265 struct ethtool_wolinfo *wol) 266 { 267 struct dp83822_private *dp83822 = phydev->priv; 268 int ret; 269 270 ret = dp83822_config_wol(phydev, wol); 271 if (!ret) 272 memcpy(&dp83822->wol, wol, sizeof(*wol)); 273 return ret; 274 } 275 276 static void dp83822_get_wol(struct phy_device *phydev, 277 struct ethtool_wolinfo *wol) 278 { 279 int value; 280 u16 sopass_val; 281 282 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 283 wol->wolopts = 0; 284 285 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 286 287 if (value & DP83822_WOL_MAGIC_EN) 288 wol->wolopts |= WAKE_MAGIC; 289 290 if (value & DP83822_WOL_SECURE_ON) { 291 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 292 MII_DP83822_RXSOP1); 293 wol->sopass[0] = (sopass_val & 0xff); 294 wol->sopass[1] = (sopass_val >> 8); 295 296 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 297 MII_DP83822_RXSOP2); 298 wol->sopass[2] = (sopass_val & 0xff); 299 wol->sopass[3] = (sopass_val >> 8); 300 301 sopass_val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 302 MII_DP83822_RXSOP3); 303 wol->sopass[4] = (sopass_val & 0xff); 304 wol->sopass[5] = (sopass_val >> 8); 305 306 wol->wolopts |= WAKE_MAGICSECURE; 307 } 308 309 /* WoL is not enabled so set wolopts to 0 */ 310 if (!(value & DP83822_WOL_EN)) 311 wol->wolopts = 0; 312 } 313 314 static int dp83822_config_intr(struct phy_device *phydev) 315 { 316 struct dp83822_private *dp83822 = phydev->priv; 317 int misr_status; 318 int physcr_status; 319 int err; 320 321 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 322 misr_status = phy_read(phydev, MII_DP83822_MISR1); 323 if (misr_status < 0) 324 return misr_status; 325 326 misr_status |= (DP83822_LINK_STAT_INT_EN | 327 DP83822_ENERGY_DET_INT_EN | 328 DP83822_LINK_QUAL_INT_EN); 329 330 if (!dp83822->fx_enabled) 331 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 332 DP83822_DUP_MODE_CHANGE_INT_EN | 333 DP83822_SPEED_CHANGED_INT_EN; 334 335 336 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 337 if (err < 0) 338 return err; 339 340 misr_status = phy_read(phydev, MII_DP83822_MISR2); 341 if (misr_status < 0) 342 return misr_status; 343 344 misr_status |= (DP83822_JABBER_DET_INT_EN | 345 DP83822_SLEEP_MODE_INT_EN | 346 DP83822_LB_FIFO_INT_EN | 347 DP83822_PAGE_RX_INT_EN | 348 DP83822_EEE_ERROR_CHANGE_INT_EN); 349 350 if (!dp83822->fx_enabled) 351 misr_status |= DP83822_ANEG_ERR_INT_EN | 352 DP83822_WOL_PKT_INT_EN; 353 354 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 355 if (err < 0) 356 return err; 357 358 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 359 if (physcr_status < 0) 360 return physcr_status; 361 362 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 363 364 } else { 365 err = phy_write(phydev, MII_DP83822_MISR1, 0); 366 if (err < 0) 367 return err; 368 369 err = phy_write(phydev, MII_DP83822_MISR2, 0); 370 if (err < 0) 371 return err; 372 373 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 374 if (physcr_status < 0) 375 return physcr_status; 376 377 physcr_status &= ~DP83822_PHYSCR_INTEN; 378 } 379 380 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 381 } 382 383 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 384 { 385 bool trigger_machine = false; 386 int irq_status; 387 388 /* The MISR1 and MISR2 registers are holding the interrupt status in 389 * the upper half (15:8), while the lower half (7:0) is used for 390 * controlling the interrupt enable state of those individual interrupt 391 * sources. To determine the possible interrupt sources, just read the 392 * MISR* register and use it directly to know which interrupts have 393 * been enabled previously or not. 394 */ 395 irq_status = phy_read(phydev, MII_DP83822_MISR1); 396 if (irq_status < 0) { 397 phy_error(phydev); 398 return IRQ_NONE; 399 } 400 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 401 trigger_machine = true; 402 403 irq_status = phy_read(phydev, MII_DP83822_MISR2); 404 if (irq_status < 0) { 405 phy_error(phydev); 406 return IRQ_NONE; 407 } 408 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 409 trigger_machine = true; 410 411 if (!trigger_machine) 412 return IRQ_NONE; 413 414 phy_trigger_machine(phydev); 415 416 return IRQ_HANDLED; 417 } 418 419 static int dp83822_read_status(struct phy_device *phydev) 420 { 421 struct dp83822_private *dp83822 = phydev->priv; 422 int status = phy_read(phydev, MII_DP83822_PHYSTS); 423 int ctrl2; 424 int ret; 425 426 if (dp83822->fx_enabled) { 427 if (status & DP83822_PHYSTS_LINK) { 428 phydev->speed = SPEED_UNKNOWN; 429 phydev->duplex = DUPLEX_UNKNOWN; 430 } else { 431 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 432 if (ctrl2 < 0) 433 return ctrl2; 434 435 if (!(ctrl2 & DP83822_FX_ENABLE)) { 436 ret = phy_write(phydev, MII_DP83822_CTRL_2, 437 DP83822_FX_ENABLE | ctrl2); 438 if (ret < 0) 439 return ret; 440 } 441 } 442 } 443 444 ret = genphy_read_status(phydev); 445 if (ret) 446 return ret; 447 448 if (status < 0) 449 return status; 450 451 if (status & DP83822_PHYSTS_DUPLEX) 452 phydev->duplex = DUPLEX_FULL; 453 else 454 phydev->duplex = DUPLEX_HALF; 455 456 if (status & DP83822_PHYSTS_10) 457 phydev->speed = SPEED_10; 458 else 459 phydev->speed = SPEED_100; 460 461 return 0; 462 } 463 464 static int dp83822_config_init_leds(struct phy_device *phydev) 465 { 466 struct dp83822_private *dp83822 = phydev->priv; 467 int ret; 468 469 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0]) { 470 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR, 471 DP83822_MLEDCR_ROUTE, 472 FIELD_PREP(DP83822_MLEDCR_ROUTE, 473 DP83822_MLEDCR_ROUTE_LED_0)); 474 if (ret) 475 return ret; 476 } else if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) { 477 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 478 DP83822_IOCTRL2_GPIO2_CTRL, 479 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 480 DP83822_IOCTRL2_GPIO2_CTRL_MLED)); 481 if (ret) 482 return ret; 483 } 484 485 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_1_GPIO1]) { 486 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1, 487 DP83822_IOCTRL1_GPIO1_CTRL, 488 FIELD_PREP(DP83822_IOCTRL1_GPIO1_CTRL, 489 DP83822_IOCTRL1_GPIO1_CTRL_LED_1)); 490 if (ret) 491 return ret; 492 } 493 494 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3]) { 495 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL1, 496 DP83822_IOCTRL1_GPIO3_CTRL, 497 FIELD_PREP(DP83822_IOCTRL1_GPIO3_CTRL, 498 DP83822_IOCTRL1_GPIO3_CTRL_LED3)); 499 if (ret) 500 return ret; 501 } 502 503 return 0; 504 } 505 506 static int dp83822_config_init(struct phy_device *phydev) 507 { 508 struct dp83822_private *dp83822 = phydev->priv; 509 struct device *dev = &phydev->mdio.dev; 510 int rgmii_delay = 0; 511 s32 rx_int_delay; 512 s32 tx_int_delay; 513 int err = 0; 514 int bmcr; 515 516 if (dp83822->set_gpio2_clk_out) 517 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, 518 DP83822_IOCTRL2_GPIO2_CTRL | 519 DP83822_IOCTRL2_GPIO2_CLK_SRC, 520 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, 521 DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) | 522 FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC, 523 dp83822->gpio2_clk_out)); 524 525 err = dp83822_config_init_leds(phydev); 526 if (err) 527 return err; 528 529 if (phy_interface_is_rgmii(phydev)) { 530 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 531 true); 532 533 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ 534 if (rx_int_delay > 0) 535 rgmii_delay |= DP83822_RX_CLK_SHIFT; 536 537 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 538 false); 539 540 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ 541 if (tx_int_delay <= 0) 542 rgmii_delay |= DP83822_TX_CLK_SHIFT; 543 544 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 545 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); 546 if (err) 547 return err; 548 549 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 550 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 551 552 if (err) 553 return err; 554 } else { 555 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 556 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 557 558 if (err) 559 return err; 560 } 561 562 if (dp83822->fx_enabled) { 563 err = phy_modify(phydev, MII_DP83822_CTRL_2, 564 DP83822_FX_ENABLE, 1); 565 if (err < 0) 566 return err; 567 568 /* Only allow advertising what this PHY supports */ 569 linkmode_and(phydev->advertising, phydev->advertising, 570 phydev->supported); 571 572 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 573 phydev->supported); 574 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 575 phydev->advertising); 576 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 577 phydev->supported); 578 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 579 phydev->supported); 580 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 581 phydev->advertising); 582 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 583 phydev->advertising); 584 585 /* Auto neg is not supported in fiber mode */ 586 bmcr = phy_read(phydev, MII_BMCR); 587 if (bmcr < 0) 588 return bmcr; 589 590 if (bmcr & BMCR_ANENABLE) { 591 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 592 if (err < 0) 593 return err; 594 } 595 phydev->autoneg = AUTONEG_DISABLE; 596 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 597 phydev->supported); 598 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 599 phydev->advertising); 600 601 /* Setup fiber advertisement */ 602 err = phy_modify_changed(phydev, MII_ADVERTISE, 603 MII_DP83822_FIBER_ADVERTISE, 604 MII_DP83822_FIBER_ADVERTISE); 605 606 if (err < 0) 607 return err; 608 609 if (dp83822->fx_signal_det_low) { 610 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 611 MII_DP83822_GENCFG, 612 DP83822_SIG_DET_LOW); 613 if (err) 614 return err; 615 } 616 } 617 return dp83822_config_wol(phydev, &dp83822->wol); 618 } 619 620 static int dp8382x_config_rmii_mode(struct phy_device *phydev) 621 { 622 struct device *dev = &phydev->mdio.dev; 623 const char *of_val; 624 int ret; 625 626 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) { 627 if (strcmp(of_val, "master") == 0) { 628 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 629 DP83822_RMII_MODE_SEL); 630 } else if (strcmp(of_val, "slave") == 0) { 631 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 632 DP83822_RMII_MODE_SEL); 633 } else { 634 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", 635 of_val); 636 ret = -EINVAL; 637 } 638 639 if (ret) 640 return ret; 641 } 642 643 return 0; 644 } 645 646 static int dp83826_config_init(struct phy_device *phydev) 647 { 648 struct dp83822_private *dp83822 = phydev->priv; 649 u16 val, mask; 650 int ret; 651 652 if (phydev->interface == PHY_INTERFACE_MODE_RMII) { 653 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 654 DP83822_RMII_MODE_EN); 655 if (ret) 656 return ret; 657 658 ret = dp8382x_config_rmii_mode(phydev); 659 if (ret) 660 return ret; 661 } else { 662 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, 663 DP83822_RMII_MODE_EN); 664 if (ret) 665 return ret; 666 } 667 668 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) { 669 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) | 670 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK, 671 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4, 672 dp83822->cfg_dac_minus)); 673 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK; 674 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG1, mask, val); 675 if (ret) 676 return ret; 677 678 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK, 679 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0, 680 dp83822->cfg_dac_minus)); 681 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK; 682 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 683 if (ret) 684 return ret; 685 } 686 687 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) { 688 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) | 689 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus); 690 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK; 691 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83826_VOD_CFG2, mask, val); 692 if (ret) 693 return ret; 694 } 695 696 return dp83822_config_wol(phydev, &dp83822->wol); 697 } 698 699 static int dp83825_config_init(struct phy_device *phydev) 700 { 701 struct dp83822_private *dp83822 = phydev->priv; 702 int ret; 703 704 ret = dp8382x_config_rmii_mode(phydev); 705 if (ret) 706 return ret; 707 708 return dp83822_config_wol(phydev, &dp83822->wol); 709 } 710 711 static int dp83822_phy_reset(struct phy_device *phydev) 712 { 713 int err; 714 715 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 716 if (err < 0) 717 return err; 718 719 return phydev->drv->config_init(phydev); 720 } 721 722 #ifdef CONFIG_OF_MDIO 723 static int dp83822_of_init_leds(struct phy_device *phydev) 724 { 725 struct device_node *node = phydev->mdio.dev.of_node; 726 struct dp83822_private *dp83822 = phydev->priv; 727 struct device_node *leds; 728 u32 index; 729 int err; 730 731 if (!node) 732 return 0; 733 734 leds = of_get_child_by_name(node, "leds"); 735 if (!leds) 736 return 0; 737 738 for_each_available_child_of_node_scoped(leds, led) { 739 err = of_property_read_u32(led, "reg", &index); 740 if (err) { 741 of_node_put(leds); 742 return err; 743 } 744 745 if (index <= DP83822_LED_INDEX_RX_D3_GPIO3) { 746 dp83822->led_pin_enable[index] = true; 747 } else { 748 of_node_put(leds); 749 return -EINVAL; 750 } 751 } 752 753 of_node_put(leds); 754 /* LED_0 and COL(GPIO2) use the MLED function. MLED can be routed to 755 * only one of these two pins at a time. 756 */ 757 if (dp83822->led_pin_enable[DP83822_LED_INDEX_LED_0] && 758 dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2]) { 759 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n"); 760 return -EINVAL; 761 } 762 763 if (dp83822->led_pin_enable[DP83822_LED_INDEX_COL_GPIO2] && 764 dp83822->set_gpio2_clk_out) { 765 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n"); 766 return -EINVAL; 767 } 768 769 if (dp83822->led_pin_enable[DP83822_LED_INDEX_RX_D3_GPIO3] && 770 phydev->interface != PHY_INTERFACE_MODE_RMII) { 771 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n"); 772 return -EINVAL; 773 } 774 775 return 0; 776 } 777 778 static int dp83822_of_init(struct phy_device *phydev) 779 { 780 struct dp83822_private *dp83822 = phydev->priv; 781 struct device *dev = &phydev->mdio.dev; 782 const char *of_val; 783 784 /* Signal detection for the PHY is only enabled if the FX_EN and the 785 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 786 * is strapped otherwise signal detection is disabled for the PHY. 787 */ 788 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 789 dp83822->fx_signal_det_low = device_property_present(dev, 790 "ti,link-loss-low"); 791 if (!dp83822->fx_enabled) 792 dp83822->fx_enabled = device_property_present(dev, 793 "ti,fiber-mode"); 794 795 if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) { 796 if (strcmp(of_val, "mac-if") == 0) { 797 dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF; 798 } else if (strcmp(of_val, "xi") == 0) { 799 dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI; 800 } else if (strcmp(of_val, "int-ref") == 0) { 801 dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF; 802 } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) { 803 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF; 804 } else if (strcmp(of_val, "free-running") == 0) { 805 dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING; 806 } else if (strcmp(of_val, "recovered") == 0) { 807 dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED; 808 } else { 809 phydev_err(phydev, 810 "Invalid value for ti,gpio2-clk-out property (%s)\n", 811 of_val); 812 return -EINVAL; 813 } 814 815 dp83822->set_gpio2_clk_out = true; 816 } 817 818 return dp83822_of_init_leds(phydev); 819 } 820 821 static int dp83826_to_dac_minus_one_regval(int percent) 822 { 823 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent; 824 825 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 826 } 827 828 static int dp83826_to_dac_plus_one_regval(int percent) 829 { 830 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT; 831 832 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP; 833 } 834 835 static void dp83826_of_init(struct phy_device *phydev) 836 { 837 struct dp83822_private *dp83822 = phydev->priv; 838 struct device *dev = &phydev->mdio.dev; 839 u32 val; 840 841 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT; 842 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val)) 843 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val); 844 845 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT; 846 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val)) 847 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val); 848 } 849 #else 850 static int dp83822_of_init(struct phy_device *phydev) 851 { 852 return 0; 853 } 854 855 static void dp83826_of_init(struct phy_device *phydev) 856 { 857 } 858 #endif /* CONFIG_OF_MDIO */ 859 860 static int dp83822_read_straps(struct phy_device *phydev) 861 { 862 struct dp83822_private *dp83822 = phydev->priv; 863 int fx_enabled, fx_sd_enable; 864 int val; 865 866 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_SOR1); 867 if (val < 0) 868 return val; 869 870 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 871 872 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 873 if (fx_enabled == DP83822_STRAP_MODE2 || 874 fx_enabled == DP83822_STRAP_MODE3) 875 dp83822->fx_enabled = 1; 876 877 if (dp83822->fx_enabled) { 878 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 879 if (fx_sd_enable == DP83822_STRAP_MODE3 || 880 fx_sd_enable == DP83822_STRAP_MODE4) 881 dp83822->fx_sd_enable = 1; 882 } 883 884 return 0; 885 } 886 887 static int dp8382x_probe(struct phy_device *phydev) 888 { 889 struct dp83822_private *dp83822; 890 891 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 892 GFP_KERNEL); 893 if (!dp83822) 894 return -ENOMEM; 895 896 phydev->priv = dp83822; 897 898 return 0; 899 } 900 901 static int dp83822_probe(struct phy_device *phydev) 902 { 903 struct dp83822_private *dp83822; 904 int ret; 905 906 ret = dp8382x_probe(phydev); 907 if (ret) 908 return ret; 909 910 dp83822 = phydev->priv; 911 912 ret = dp83822_read_straps(phydev); 913 if (ret) 914 return ret; 915 916 ret = dp83822_of_init(phydev); 917 if (ret) 918 return ret; 919 920 if (dp83822->fx_enabled) 921 phydev->port = PORT_FIBRE; 922 923 return 0; 924 } 925 926 static int dp83826_probe(struct phy_device *phydev) 927 { 928 int ret; 929 930 ret = dp8382x_probe(phydev); 931 if (ret) 932 return ret; 933 934 dp83826_of_init(phydev); 935 936 return 0; 937 } 938 939 static int dp83822_suspend(struct phy_device *phydev) 940 { 941 int value; 942 943 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 944 945 if (!(value & DP83822_WOL_EN)) 946 genphy_suspend(phydev); 947 948 return 0; 949 } 950 951 static int dp83822_resume(struct phy_device *phydev) 952 { 953 int value; 954 955 genphy_resume(phydev); 956 957 value = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG); 958 959 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | 960 DP83822_WOL_CLR_INDICATION); 961 962 return 0; 963 } 964 965 static int dp83822_led_mode(u8 index, unsigned long rules) 966 { 967 switch (rules) { 968 case BIT(TRIGGER_NETDEV_LINK): 969 return DP83822_LED_FN_LINK; 970 case BIT(TRIGGER_NETDEV_LINK_10): 971 return DP83822_LED_FN_LINK_10_BT; 972 case BIT(TRIGGER_NETDEV_LINK_100): 973 return DP83822_LED_FN_LINK_100_BTX; 974 case BIT(TRIGGER_NETDEV_FULL_DUPLEX): 975 return DP83822_LED_FN_FULL_DUPLEX; 976 case BIT(TRIGGER_NETDEV_TX): 977 return DP83822_LED_FN_TX; 978 case BIT(TRIGGER_NETDEV_RX): 979 return DP83822_LED_FN_RX; 980 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 981 return DP83822_LED_FN_RX_TX; 982 case BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR): 983 return DP83822_LED_FN_RX_TX_ERR; 984 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): 985 return DP83822_LED_FN_LINK_RX_TX; 986 default: 987 return -EOPNOTSUPP; 988 } 989 } 990 991 static int dp83822_led_hw_is_supported(struct phy_device *phydev, u8 index, 992 unsigned long rules) 993 { 994 int mode; 995 996 mode = dp83822_led_mode(index, rules); 997 if (mode < 0) 998 return mode; 999 1000 return 0; 1001 } 1002 1003 static int dp83822_led_hw_control_set(struct phy_device *phydev, u8 index, 1004 unsigned long rules) 1005 { 1006 int mode; 1007 1008 mode = dp83822_led_mode(index, rules); 1009 if (mode < 0) 1010 return mode; 1011 1012 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) 1013 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1014 MII_DP83822_MLEDCR, DP83822_MLEDCR_CFG, 1015 FIELD_PREP(DP83822_MLEDCR_CFG, mode)); 1016 else if (index == DP83822_LED_INDEX_LED_1_GPIO1) 1017 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1018 MII_DP83822_LEDCFG1, 1019 DP83822_LEDCFG1_LED1_CTRL, 1020 FIELD_PREP(DP83822_LEDCFG1_LED1_CTRL, 1021 mode)); 1022 else 1023 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1024 MII_DP83822_LEDCFG1, 1025 DP83822_LEDCFG1_LED3_CTRL, 1026 FIELD_PREP(DP83822_LEDCFG1_LED3_CTRL, 1027 mode)); 1028 } 1029 1030 static int dp83822_led_hw_control_get(struct phy_device *phydev, u8 index, 1031 unsigned long *rules) 1032 { 1033 int val; 1034 1035 if (index == DP83822_LED_INDEX_LED_0 || index == DP83822_LED_INDEX_COL_GPIO2) { 1036 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_MLEDCR); 1037 if (val < 0) 1038 return val; 1039 1040 val = FIELD_GET(DP83822_MLEDCR_CFG, val); 1041 } else { 1042 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LEDCFG1); 1043 if (val < 0) 1044 return val; 1045 1046 if (index == DP83822_LED_INDEX_LED_1_GPIO1) 1047 val = FIELD_GET(DP83822_LEDCFG1_LED1_CTRL, val); 1048 else 1049 val = FIELD_GET(DP83822_LEDCFG1_LED3_CTRL, val); 1050 } 1051 1052 switch (val) { 1053 case DP83822_LED_FN_LINK: 1054 *rules = BIT(TRIGGER_NETDEV_LINK); 1055 break; 1056 case DP83822_LED_FN_LINK_10_BT: 1057 *rules = BIT(TRIGGER_NETDEV_LINK_10); 1058 break; 1059 case DP83822_LED_FN_LINK_100_BTX: 1060 *rules = BIT(TRIGGER_NETDEV_LINK_100); 1061 break; 1062 case DP83822_LED_FN_FULL_DUPLEX: 1063 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX); 1064 break; 1065 case DP83822_LED_FN_TX: 1066 *rules = BIT(TRIGGER_NETDEV_TX); 1067 break; 1068 case DP83822_LED_FN_RX: 1069 *rules = BIT(TRIGGER_NETDEV_RX); 1070 break; 1071 case DP83822_LED_FN_RX_TX: 1072 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX); 1073 break; 1074 case DP83822_LED_FN_RX_TX_ERR: 1075 *rules = BIT(TRIGGER_NETDEV_TX_ERR) | BIT(TRIGGER_NETDEV_RX_ERR); 1076 break; 1077 case DP83822_LED_FN_LINK_RX_TX: 1078 *rules = BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) | 1079 BIT(TRIGGER_NETDEV_RX); 1080 break; 1081 default: 1082 *rules = 0; 1083 break; 1084 } 1085 1086 return 0; 1087 } 1088 1089 #define DP83822_PHY_DRIVER(_id, _name) \ 1090 { \ 1091 PHY_ID_MATCH_MODEL(_id), \ 1092 .name = (_name), \ 1093 /* PHY_BASIC_FEATURES */ \ 1094 .probe = dp83822_probe, \ 1095 .soft_reset = dp83822_phy_reset, \ 1096 .config_init = dp83822_config_init, \ 1097 .read_status = dp83822_read_status, \ 1098 .get_wol = dp83822_get_wol, \ 1099 .set_wol = dp83822_set_wol, \ 1100 .config_intr = dp83822_config_intr, \ 1101 .handle_interrupt = dp83822_handle_interrupt, \ 1102 .suspend = dp83822_suspend, \ 1103 .resume = dp83822_resume, \ 1104 .led_hw_is_supported = dp83822_led_hw_is_supported, \ 1105 .led_hw_control_set = dp83822_led_hw_control_set, \ 1106 .led_hw_control_get = dp83822_led_hw_control_get, \ 1107 } 1108 1109 #define DP83825_PHY_DRIVER(_id, _name) \ 1110 { \ 1111 PHY_ID_MATCH_MODEL(_id), \ 1112 .name = (_name), \ 1113 /* PHY_BASIC_FEATURES */ \ 1114 .probe = dp8382x_probe, \ 1115 .soft_reset = dp83822_phy_reset, \ 1116 .config_init = dp83825_config_init, \ 1117 .get_wol = dp83822_get_wol, \ 1118 .set_wol = dp83822_set_wol, \ 1119 .config_intr = dp83822_config_intr, \ 1120 .handle_interrupt = dp83822_handle_interrupt, \ 1121 .suspend = dp83822_suspend, \ 1122 .resume = dp83822_resume, \ 1123 } 1124 1125 #define DP83826_PHY_DRIVER(_id, _name) \ 1126 { \ 1127 PHY_ID_MATCH_MODEL(_id), \ 1128 .name = (_name), \ 1129 /* PHY_BASIC_FEATURES */ \ 1130 .probe = dp83826_probe, \ 1131 .soft_reset = dp83822_phy_reset, \ 1132 .config_init = dp83826_config_init, \ 1133 .get_wol = dp83822_get_wol, \ 1134 .set_wol = dp83822_set_wol, \ 1135 .config_intr = dp83822_config_intr, \ 1136 .handle_interrupt = dp83822_handle_interrupt, \ 1137 .suspend = dp83822_suspend, \ 1138 .resume = dp83822_resume, \ 1139 } 1140 1141 static struct phy_driver dp83822_driver[] = { 1142 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 1143 DP83825_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 1144 DP83825_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 1145 DP83825_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 1146 DP83825_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 1147 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 1148 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 1149 }; 1150 module_phy_driver(dp83822_driver); 1151 1152 static const struct mdio_device_id __maybe_unused dp83822_tbl[] = { 1153 { DP83822_PHY_ID, 0xfffffff0 }, 1154 { DP83825I_PHY_ID, 0xfffffff0 }, 1155 { DP83826C_PHY_ID, 0xfffffff0 }, 1156 { DP83826NC_PHY_ID, 0xfffffff0 }, 1157 { DP83825S_PHY_ID, 0xfffffff0 }, 1158 { DP83825CM_PHY_ID, 0xfffffff0 }, 1159 { DP83825CS_PHY_ID, 0xfffffff0 }, 1160 { }, 1161 }; 1162 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 1163 1164 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 1165 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 1166 MODULE_LICENSE("GPL v2"); 1167