1*cb646e2bSRichard Cochran /* dp83640_reg.h 2*cb646e2bSRichard Cochran * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011 3*cb646e2bSRichard Cochran */ 4*cb646e2bSRichard Cochran #ifndef HAVE_DP83640_REGISTERS 5*cb646e2bSRichard Cochran #define HAVE_DP83640_REGISTERS 6*cb646e2bSRichard Cochran 7*cb646e2bSRichard Cochran #define PAGE0 0x0000 8*cb646e2bSRichard Cochran #define PHYCR2 0x001c /* PHY Control Register 2 */ 9*cb646e2bSRichard Cochran 10*cb646e2bSRichard Cochran #define PAGE4 0x0004 11*cb646e2bSRichard Cochran #define PTP_CTL 0x0014 /* PTP Control Register */ 12*cb646e2bSRichard Cochran #define PTP_TDR 0x0015 /* PTP Time Data Register */ 13*cb646e2bSRichard Cochran #define PTP_STS 0x0016 /* PTP Status Register */ 14*cb646e2bSRichard Cochran #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */ 15*cb646e2bSRichard Cochran #define PTP_RATEL 0x0018 /* PTP Rate Low Register */ 16*cb646e2bSRichard Cochran #define PTP_RATEH 0x0019 /* PTP Rate High Register */ 17*cb646e2bSRichard Cochran #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */ 18*cb646e2bSRichard Cochran #define PTP_WRCKSUM 0x001b /* PTP Write Checksum */ 19*cb646e2bSRichard Cochran #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */ 20*cb646e2bSRichard Cochran #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */ 21*cb646e2bSRichard Cochran #define PTP_ESTS 0x001e /* PTP Event Status Register */ 22*cb646e2bSRichard Cochran #define PTP_EDATA 0x001f /* PTP Event Data Register */ 23*cb646e2bSRichard Cochran 24*cb646e2bSRichard Cochran #define PAGE5 0x0005 25*cb646e2bSRichard Cochran #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */ 26*cb646e2bSRichard Cochran #define PTP_EVNT 0x0015 /* PTP Event Configuration Register */ 27*cb646e2bSRichard Cochran #define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */ 28*cb646e2bSRichard Cochran #define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */ 29*cb646e2bSRichard Cochran #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */ 30*cb646e2bSRichard Cochran #define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */ 31*cb646e2bSRichard Cochran #define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */ 32*cb646e2bSRichard Cochran #define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */ 33*cb646e2bSRichard Cochran #define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */ 34*cb646e2bSRichard Cochran #define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */ 35*cb646e2bSRichard Cochran #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */ 36*cb646e2bSRichard Cochran #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */ 37*cb646e2bSRichard Cochran 38*cb646e2bSRichard Cochran #define PAGE6 0x0006 39*cb646e2bSRichard Cochran #define PTP_COC 0x0014 /* PTP Clock Output Control Register */ 40*cb646e2bSRichard Cochran #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */ 41*cb646e2bSRichard Cochran #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */ 42*cb646e2bSRichard Cochran #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */ 43*cb646e2bSRichard Cochran #define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */ 44*cb646e2bSRichard Cochran #define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */ 45*cb646e2bSRichard Cochran #define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */ 46*cb646e2bSRichard Cochran #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */ 47*cb646e2bSRichard Cochran #define PTP_ETR 0x001c /* PTP Ethernet Type Register */ 48*cb646e2bSRichard Cochran #define PTP_OFF 0x001d /* PTP Offset Register */ 49*cb646e2bSRichard Cochran #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */ 50*cb646e2bSRichard Cochran #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */ 51*cb646e2bSRichard Cochran 52*cb646e2bSRichard Cochran /* Bit definitions for the PHYCR2 register */ 53*cb646e2bSRichard Cochran #define BC_WRITE (1<<11) /* Broadcast Write Enable */ 54*cb646e2bSRichard Cochran 55*cb646e2bSRichard Cochran /* Bit definitions for the PTP_CTL register */ 56*cb646e2bSRichard Cochran #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */ 57*cb646e2bSRichard Cochran #define TRIG_SEL_MASK (0x7) 58*cb646e2bSRichard Cochran #define TRIG_DIS (1<<9) /* Disable PTP Trigger */ 59*cb646e2bSRichard Cochran #define TRIG_EN (1<<8) /* Enable PTP Trigger */ 60*cb646e2bSRichard Cochran #define TRIG_READ (1<<7) /* Read PTP Trigger */ 61*cb646e2bSRichard Cochran #define TRIG_LOAD (1<<6) /* Load PTP Trigger */ 62*cb646e2bSRichard Cochran #define PTP_RD_CLK (1<<5) /* Read PTP Clock */ 63*cb646e2bSRichard Cochran #define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */ 64*cb646e2bSRichard Cochran #define PTP_STEP_CLK (1<<3) /* Step PTP Clock */ 65*cb646e2bSRichard Cochran #define PTP_ENABLE (1<<2) /* Enable PTP Clock */ 66*cb646e2bSRichard Cochran #define PTP_DISABLE (1<<1) /* Disable PTP Clock */ 67*cb646e2bSRichard Cochran #define PTP_RESET (1<<0) /* Reset PTP Clock */ 68*cb646e2bSRichard Cochran 69*cb646e2bSRichard Cochran /* Bit definitions for the PTP_STS register */ 70*cb646e2bSRichard Cochran #define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */ 71*cb646e2bSRichard Cochran #define RXTS_RDY (1<<10) /* Receive Timestamp Ready */ 72*cb646e2bSRichard Cochran #define TRIG_DONE (1<<9) /* PTP Trigger Done */ 73*cb646e2bSRichard Cochran #define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */ 74*cb646e2bSRichard Cochran #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */ 75*cb646e2bSRichard Cochran #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */ 76*cb646e2bSRichard Cochran #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */ 77*cb646e2bSRichard Cochran #define EVENT_IE (1<<0) /* Event Interrupt Enable */ 78*cb646e2bSRichard Cochran 79*cb646e2bSRichard Cochran /* Bit definitions for the PTP_TSTS register */ 80*cb646e2bSRichard Cochran #define TRIG7_ERROR (1<<15) /* Trigger 7 Error */ 81*cb646e2bSRichard Cochran #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */ 82*cb646e2bSRichard Cochran #define TRIG6_ERROR (1<<13) /* Trigger 6 Error */ 83*cb646e2bSRichard Cochran #define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */ 84*cb646e2bSRichard Cochran #define TRIG5_ERROR (1<<11) /* Trigger 5 Error */ 85*cb646e2bSRichard Cochran #define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */ 86*cb646e2bSRichard Cochran #define TRIG4_ERROR (1<<9) /* Trigger 4 Error */ 87*cb646e2bSRichard Cochran #define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */ 88*cb646e2bSRichard Cochran #define TRIG3_ERROR (1<<7) /* Trigger 3 Error */ 89*cb646e2bSRichard Cochran #define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */ 90*cb646e2bSRichard Cochran #define TRIG2_ERROR (1<<5) /* Trigger 2 Error */ 91*cb646e2bSRichard Cochran #define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */ 92*cb646e2bSRichard Cochran #define TRIG1_ERROR (1<<3) /* Trigger 1 Error */ 93*cb646e2bSRichard Cochran #define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */ 94*cb646e2bSRichard Cochran #define TRIG0_ERROR (1<<1) /* Trigger 0 Error */ 95*cb646e2bSRichard Cochran #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */ 96*cb646e2bSRichard Cochran 97*cb646e2bSRichard Cochran /* Bit definitions for the PTP_RATEH register */ 98*cb646e2bSRichard Cochran #define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */ 99*cb646e2bSRichard Cochran #define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */ 100*cb646e2bSRichard Cochran #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */ 101*cb646e2bSRichard Cochran #define PTP_RATE_HI_MASK (0x3ff) 102*cb646e2bSRichard Cochran 103*cb646e2bSRichard Cochran /* Bit definitions for the PTP_ESTS register */ 104*cb646e2bSRichard Cochran #define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */ 105*cb646e2bSRichard Cochran #define EVNTS_MISSED_MASK (0x7) 106*cb646e2bSRichard Cochran #define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */ 107*cb646e2bSRichard Cochran #define EVNT_TS_LEN_MASK (0x3) 108*cb646e2bSRichard Cochran #define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */ 109*cb646e2bSRichard Cochran #define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */ 110*cb646e2bSRichard Cochran #define EVNT_NUM_MASK (0x7) 111*cb646e2bSRichard Cochran #define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */ 112*cb646e2bSRichard Cochran #define EVENT_DET (1<<0) /* PTP Event Detected */ 113*cb646e2bSRichard Cochran 114*cb646e2bSRichard Cochran /* Bit definitions for the PTP_EDATA register */ 115*cb646e2bSRichard Cochran #define E7_RISE (1<<15) /* Indicates direction of Event 7 */ 116*cb646e2bSRichard Cochran #define E7_DET (1<<14) /* Indicates Event 7 detected */ 117*cb646e2bSRichard Cochran #define E6_RISE (1<<13) /* Indicates direction of Event 6 */ 118*cb646e2bSRichard Cochran #define E6_DET (1<<12) /* Indicates Event 6 detected */ 119*cb646e2bSRichard Cochran #define E5_RISE (1<<11) /* Indicates direction of Event 5 */ 120*cb646e2bSRichard Cochran #define E5_DET (1<<10) /* Indicates Event 5 detected */ 121*cb646e2bSRichard Cochran #define E4_RISE (1<<9) /* Indicates direction of Event 4 */ 122*cb646e2bSRichard Cochran #define E4_DET (1<<8) /* Indicates Event 4 detected */ 123*cb646e2bSRichard Cochran #define E3_RISE (1<<7) /* Indicates direction of Event 3 */ 124*cb646e2bSRichard Cochran #define E3_DET (1<<6) /* Indicates Event 3 detected */ 125*cb646e2bSRichard Cochran #define E2_RISE (1<<5) /* Indicates direction of Event 2 */ 126*cb646e2bSRichard Cochran #define E2_DET (1<<4) /* Indicates Event 2 detected */ 127*cb646e2bSRichard Cochran #define E1_RISE (1<<3) /* Indicates direction of Event 1 */ 128*cb646e2bSRichard Cochran #define E1_DET (1<<2) /* Indicates Event 1 detected */ 129*cb646e2bSRichard Cochran #define E0_RISE (1<<1) /* Indicates direction of Event 0 */ 130*cb646e2bSRichard Cochran #define E0_DET (1<<0) /* Indicates Event 0 detected */ 131*cb646e2bSRichard Cochran 132*cb646e2bSRichard Cochran /* Bit definitions for the PTP_TRIG register */ 133*cb646e2bSRichard Cochran #define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */ 134*cb646e2bSRichard Cochran #define TRIG_PER (1<<14) /* generate a periodic signal */ 135*cb646e2bSRichard Cochran #define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */ 136*cb646e2bSRichard Cochran #define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */ 137*cb646e2bSRichard Cochran #define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */ 138*cb646e2bSRichard Cochran #define TRIG_GPIO_MASK (0xf) 139*cb646e2bSRichard Cochran #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */ 140*cb646e2bSRichard Cochran #define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */ 141*cb646e2bSRichard Cochran #define TRIG_CSEL_MASK (0x7) 142*cb646e2bSRichard Cochran #define TRIG_WR (1<<0) /* Trigger Configuration Write */ 143*cb646e2bSRichard Cochran 144*cb646e2bSRichard Cochran /* Bit definitions for the PTP_EVNT register */ 145*cb646e2bSRichard Cochran #define EVNT_RISE (1<<14) /* Event Rise Detect Enable */ 146*cb646e2bSRichard Cochran #define EVNT_FALL (1<<13) /* Event Fall Detect Enable */ 147*cb646e2bSRichard Cochran #define EVNT_SINGLE (1<<12) /* enable single event capture operation */ 148*cb646e2bSRichard Cochran #define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */ 149*cb646e2bSRichard Cochran #define EVNT_GPIO_MASK (0xf) 150*cb646e2bSRichard Cochran #define EVNT_SEL_SHIFT (1) /* Event Select */ 151*cb646e2bSRichard Cochran #define EVNT_SEL_MASK (0x7) 152*cb646e2bSRichard Cochran #define EVNT_WR (1<<0) /* Event Configuration Write */ 153*cb646e2bSRichard Cochran 154*cb646e2bSRichard Cochran /* Bit definitions for the PTP_TXCFG0 register */ 155*cb646e2bSRichard Cochran #define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */ 156*cb646e2bSRichard Cochran #define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */ 157*cb646e2bSRichard Cochran #define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */ 158*cb646e2bSRichard Cochran #define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */ 159*cb646e2bSRichard Cochran #define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */ 160*cb646e2bSRichard Cochran #define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */ 161*cb646e2bSRichard Cochran #define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */ 162*cb646e2bSRichard Cochran #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */ 163*cb646e2bSRichard Cochran #define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */ 164*cb646e2bSRichard Cochran #define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */ 165*cb646e2bSRichard Cochran #define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */ 166*cb646e2bSRichard Cochran #define TX_PTP_VER_MASK (0xf) 167*cb646e2bSRichard Cochran #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */ 168*cb646e2bSRichard Cochran 169*cb646e2bSRichard Cochran /* Bit definitions for the PTP_TXCFG1 register */ 170*cb646e2bSRichard Cochran #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */ 171*cb646e2bSRichard Cochran #define BYTE0_MASK_MASK (0xff) 172*cb646e2bSRichard Cochran #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */ 173*cb646e2bSRichard Cochran #define BYTE0_DATA_MASK (0xff) 174*cb646e2bSRichard Cochran 175*cb646e2bSRichard Cochran /* Bit definitions for the PSF_CFG0 register */ 176*cb646e2bSRichard Cochran #define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */ 177*cb646e2bSRichard Cochran #define MAC_SRC_ADD_MASK (0x3) 178*cb646e2bSRichard Cochran #define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */ 179*cb646e2bSRichard Cochran #define MIN_PRE_MASK (0x7) 180*cb646e2bSRichard Cochran #define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */ 181*cb646e2bSRichard Cochran #define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */ 182*cb646e2bSRichard Cochran #define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */ 183*cb646e2bSRichard Cochran #define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */ 184*cb646e2bSRichard Cochran #define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */ 185*cb646e2bSRichard Cochran #define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */ 186*cb646e2bSRichard Cochran #define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */ 187*cb646e2bSRichard Cochran #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */ 188*cb646e2bSRichard Cochran 189*cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG0 register */ 190*cb646e2bSRichard Cochran #define DOMAIN_EN (1<<15) /* Domain Match Enable */ 191*cb646e2bSRichard Cochran #define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */ 192*cb646e2bSRichard Cochran #define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */ 193*cb646e2bSRichard Cochran #define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */ 194*cb646e2bSRichard Cochran #define RX_SLAVE (1<<11) /* Receive Slave Only */ 195*cb646e2bSRichard Cochran #define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */ 196*cb646e2bSRichard Cochran #define IP1588_EN_MASK (0xf) 197*cb646e2bSRichard Cochran #define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */ 198*cb646e2bSRichard Cochran #define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */ 199*cb646e2bSRichard Cochran #define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */ 200*cb646e2bSRichard Cochran #define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */ 201*cb646e2bSRichard Cochran #define RX_PTP_VER_MASK (0xf) 202*cb646e2bSRichard Cochran #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */ 203*cb646e2bSRichard Cochran 204*cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG1 register */ 205*cb646e2bSRichard Cochran #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */ 206*cb646e2bSRichard Cochran #define BYTE0_MASK_MASK (0xff) 207*cb646e2bSRichard Cochran #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */ 208*cb646e2bSRichard Cochran #define BYTE0_DATA_MASK (0xff) 209*cb646e2bSRichard Cochran 210*cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG3 register */ 211*cb646e2bSRichard Cochran #define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */ 212*cb646e2bSRichard Cochran #define TS_MIN_IFG_MASK (0xf) 213*cb646e2bSRichard Cochran #define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */ 214*cb646e2bSRichard Cochran #define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */ 215*cb646e2bSRichard Cochran #define TS_APPEND (1<<9) /* Append Timestamp for L2 */ 216*cb646e2bSRichard Cochran #define TS_INSERT (1<<8) /* Enable Timestamp Insertion */ 217*cb646e2bSRichard Cochran #define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */ 218*cb646e2bSRichard Cochran #define PTP_DOMAIN_MASK (0xff) 219*cb646e2bSRichard Cochran 220*cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG4 register */ 221*cb646e2bSRichard Cochran #define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */ 222*cb646e2bSRichard Cochran #define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */ 223*cb646e2bSRichard Cochran #define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */ 224*cb646e2bSRichard Cochran #define TS_SEC_LEN_MASK (0x3) 225*cb646e2bSRichard Cochran #define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */ 226*cb646e2bSRichard Cochran #define RXTS_NS_OFF_MASK (0x3f) 227*cb646e2bSRichard Cochran #define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */ 228*cb646e2bSRichard Cochran #define RXTS_SEC_OFF_MASK (0x3f) 229*cb646e2bSRichard Cochran 230*cb646e2bSRichard Cochran /* Bit definitions for the PTP_COC register */ 231*cb646e2bSRichard Cochran #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */ 232*cb646e2bSRichard Cochran #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */ 233*cb646e2bSRichard Cochran #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */ 234*cb646e2bSRichard Cochran #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */ 235*cb646e2bSRichard Cochran #define PTP_CLKDIV_MASK (0xff) 236*cb646e2bSRichard Cochran 237*cb646e2bSRichard Cochran /* Bit definitions for the PSF_CFG1 register */ 238*cb646e2bSRichard Cochran #define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */ 239*cb646e2bSRichard Cochran #define PTPRESERVED_MASK (0xf) 240*cb646e2bSRichard Cochran #define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */ 241*cb646e2bSRichard Cochran #define VERSIONPTP_MASK (0xf) 242*cb646e2bSRichard Cochran #define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */ 243*cb646e2bSRichard Cochran #define TRANSPORT_SPECIFIC_MASK (0xf) 244*cb646e2bSRichard Cochran #define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */ 245*cb646e2bSRichard Cochran #define MESSAGETYPE_MASK (0xf) 246*cb646e2bSRichard Cochran 247*cb646e2bSRichard Cochran /* Bit definitions for the PTP_SFDCFG register */ 248*cb646e2bSRichard Cochran #define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */ 249*cb646e2bSRichard Cochran #define TX_SFD_GPIO_MASK (0xf) 250*cb646e2bSRichard Cochran #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */ 251*cb646e2bSRichard Cochran #define RX_SFD_GPIO_MASK (0xf) 252*cb646e2bSRichard Cochran 253*cb646e2bSRichard Cochran /* Bit definitions for the PTP_INTCTL register */ 254*cb646e2bSRichard Cochran #define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */ 255*cb646e2bSRichard Cochran #define PTP_INT_GPIO_MASK (0xf) 256*cb646e2bSRichard Cochran 257*cb646e2bSRichard Cochran /* Bit definitions for the PTP_CLKSRC register */ 258*cb646e2bSRichard Cochran #define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */ 259*cb646e2bSRichard Cochran #define CLK_SRC_MASK (0x3) 260*cb646e2bSRichard Cochran #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */ 261*cb646e2bSRichard Cochran #define CLK_SRC_PER_MASK (0x7f) 262*cb646e2bSRichard Cochran 263*cb646e2bSRichard Cochran /* Bit definitions for the PTP_OFF register */ 264*cb646e2bSRichard Cochran #define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */ 265*cb646e2bSRichard Cochran #define PTP_OFFSET_MASK (0xff) 266*cb646e2bSRichard Cochran 267*cb646e2bSRichard Cochran #endif 268