1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2cb646e2bSRichard Cochran /* dp83640_reg.h 3cb646e2bSRichard Cochran * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011 4cb646e2bSRichard Cochran */ 5cb646e2bSRichard Cochran #ifndef HAVE_DP83640_REGISTERS 6cb646e2bSRichard Cochran #define HAVE_DP83640_REGISTERS 7cb646e2bSRichard Cochran 8*7366c23fSRandy Dunlap /* #define PAGE0 0x0000 */ 9cb646e2bSRichard Cochran #define PHYCR2 0x001c /* PHY Control Register 2 */ 10cb646e2bSRichard Cochran 11cb646e2bSRichard Cochran #define PAGE4 0x0004 12cb646e2bSRichard Cochran #define PTP_CTL 0x0014 /* PTP Control Register */ 13cb646e2bSRichard Cochran #define PTP_TDR 0x0015 /* PTP Time Data Register */ 14cb646e2bSRichard Cochran #define PTP_STS 0x0016 /* PTP Status Register */ 15cb646e2bSRichard Cochran #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */ 16cb646e2bSRichard Cochran #define PTP_RATEL 0x0018 /* PTP Rate Low Register */ 17cb646e2bSRichard Cochran #define PTP_RATEH 0x0019 /* PTP Rate High Register */ 18cb646e2bSRichard Cochran #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */ 19cb646e2bSRichard Cochran #define PTP_WRCKSUM 0x001b /* PTP Write Checksum */ 20cb646e2bSRichard Cochran #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */ 21cb646e2bSRichard Cochran #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */ 22cb646e2bSRichard Cochran #define PTP_ESTS 0x001e /* PTP Event Status Register */ 23cb646e2bSRichard Cochran #define PTP_EDATA 0x001f /* PTP Event Data Register */ 24cb646e2bSRichard Cochran 25cb646e2bSRichard Cochran #define PAGE5 0x0005 26cb646e2bSRichard Cochran #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */ 27cb646e2bSRichard Cochran #define PTP_EVNT 0x0015 /* PTP Event Configuration Register */ 28cb646e2bSRichard Cochran #define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */ 29cb646e2bSRichard Cochran #define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */ 30cb646e2bSRichard Cochran #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */ 31cb646e2bSRichard Cochran #define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */ 32cb646e2bSRichard Cochran #define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */ 33cb646e2bSRichard Cochran #define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */ 34cb646e2bSRichard Cochran #define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */ 35cb646e2bSRichard Cochran #define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */ 36cb646e2bSRichard Cochran #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */ 37cb646e2bSRichard Cochran #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */ 38cb646e2bSRichard Cochran 39cb646e2bSRichard Cochran #define PAGE6 0x0006 40cb646e2bSRichard Cochran #define PTP_COC 0x0014 /* PTP Clock Output Control Register */ 41cb646e2bSRichard Cochran #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */ 42cb646e2bSRichard Cochran #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */ 43cb646e2bSRichard Cochran #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */ 44cb646e2bSRichard Cochran #define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */ 45cb646e2bSRichard Cochran #define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */ 46cb646e2bSRichard Cochran #define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */ 47cb646e2bSRichard Cochran #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */ 48cb646e2bSRichard Cochran #define PTP_ETR 0x001c /* PTP Ethernet Type Register */ 49cb646e2bSRichard Cochran #define PTP_OFF 0x001d /* PTP Offset Register */ 50cb646e2bSRichard Cochran #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */ 51cb646e2bSRichard Cochran #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */ 52cb646e2bSRichard Cochran 53cb646e2bSRichard Cochran /* Bit definitions for the PHYCR2 register */ 54cb646e2bSRichard Cochran #define BC_WRITE (1<<11) /* Broadcast Write Enable */ 55cb646e2bSRichard Cochran 56cb646e2bSRichard Cochran /* Bit definitions for the PTP_CTL register */ 57cb646e2bSRichard Cochran #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */ 58cb646e2bSRichard Cochran #define TRIG_SEL_MASK (0x7) 59cb646e2bSRichard Cochran #define TRIG_DIS (1<<9) /* Disable PTP Trigger */ 60cb646e2bSRichard Cochran #define TRIG_EN (1<<8) /* Enable PTP Trigger */ 61cb646e2bSRichard Cochran #define TRIG_READ (1<<7) /* Read PTP Trigger */ 62cb646e2bSRichard Cochran #define TRIG_LOAD (1<<6) /* Load PTP Trigger */ 63cb646e2bSRichard Cochran #define PTP_RD_CLK (1<<5) /* Read PTP Clock */ 64cb646e2bSRichard Cochran #define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */ 65cb646e2bSRichard Cochran #define PTP_STEP_CLK (1<<3) /* Step PTP Clock */ 66cb646e2bSRichard Cochran #define PTP_ENABLE (1<<2) /* Enable PTP Clock */ 67cb646e2bSRichard Cochran #define PTP_DISABLE (1<<1) /* Disable PTP Clock */ 68cb646e2bSRichard Cochran #define PTP_RESET (1<<0) /* Reset PTP Clock */ 69cb646e2bSRichard Cochran 70cb646e2bSRichard Cochran /* Bit definitions for the PTP_STS register */ 71cb646e2bSRichard Cochran #define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */ 72cb646e2bSRichard Cochran #define RXTS_RDY (1<<10) /* Receive Timestamp Ready */ 73cb646e2bSRichard Cochran #define TRIG_DONE (1<<9) /* PTP Trigger Done */ 74cb646e2bSRichard Cochran #define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */ 75cb646e2bSRichard Cochran #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */ 76cb646e2bSRichard Cochran #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */ 77cb646e2bSRichard Cochran #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */ 78cb646e2bSRichard Cochran #define EVENT_IE (1<<0) /* Event Interrupt Enable */ 79cb646e2bSRichard Cochran 80cb646e2bSRichard Cochran /* Bit definitions for the PTP_TSTS register */ 81cb646e2bSRichard Cochran #define TRIG7_ERROR (1<<15) /* Trigger 7 Error */ 82cb646e2bSRichard Cochran #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */ 83cb646e2bSRichard Cochran #define TRIG6_ERROR (1<<13) /* Trigger 6 Error */ 84cb646e2bSRichard Cochran #define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */ 85cb646e2bSRichard Cochran #define TRIG5_ERROR (1<<11) /* Trigger 5 Error */ 86cb646e2bSRichard Cochran #define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */ 87cb646e2bSRichard Cochran #define TRIG4_ERROR (1<<9) /* Trigger 4 Error */ 88cb646e2bSRichard Cochran #define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */ 89cb646e2bSRichard Cochran #define TRIG3_ERROR (1<<7) /* Trigger 3 Error */ 90cb646e2bSRichard Cochran #define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */ 91cb646e2bSRichard Cochran #define TRIG2_ERROR (1<<5) /* Trigger 2 Error */ 92cb646e2bSRichard Cochran #define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */ 93cb646e2bSRichard Cochran #define TRIG1_ERROR (1<<3) /* Trigger 1 Error */ 94cb646e2bSRichard Cochran #define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */ 95cb646e2bSRichard Cochran #define TRIG0_ERROR (1<<1) /* Trigger 0 Error */ 96cb646e2bSRichard Cochran #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */ 97cb646e2bSRichard Cochran 98cb646e2bSRichard Cochran /* Bit definitions for the PTP_RATEH register */ 99cb646e2bSRichard Cochran #define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */ 100cb646e2bSRichard Cochran #define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */ 101cb646e2bSRichard Cochran #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */ 102cb646e2bSRichard Cochran #define PTP_RATE_HI_MASK (0x3ff) 103cb646e2bSRichard Cochran 104cb646e2bSRichard Cochran /* Bit definitions for the PTP_ESTS register */ 105cb646e2bSRichard Cochran #define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */ 106cb646e2bSRichard Cochran #define EVNTS_MISSED_MASK (0x7) 107cb646e2bSRichard Cochran #define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */ 108cb646e2bSRichard Cochran #define EVNT_TS_LEN_MASK (0x3) 109cb646e2bSRichard Cochran #define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */ 110cb646e2bSRichard Cochran #define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */ 111cb646e2bSRichard Cochran #define EVNT_NUM_MASK (0x7) 112cb646e2bSRichard Cochran #define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */ 113cb646e2bSRichard Cochran #define EVENT_DET (1<<0) /* PTP Event Detected */ 114cb646e2bSRichard Cochran 115cb646e2bSRichard Cochran /* Bit definitions for the PTP_EDATA register */ 116cb646e2bSRichard Cochran #define E7_RISE (1<<15) /* Indicates direction of Event 7 */ 117cb646e2bSRichard Cochran #define E7_DET (1<<14) /* Indicates Event 7 detected */ 118cb646e2bSRichard Cochran #define E6_RISE (1<<13) /* Indicates direction of Event 6 */ 119cb646e2bSRichard Cochran #define E6_DET (1<<12) /* Indicates Event 6 detected */ 120cb646e2bSRichard Cochran #define E5_RISE (1<<11) /* Indicates direction of Event 5 */ 121cb646e2bSRichard Cochran #define E5_DET (1<<10) /* Indicates Event 5 detected */ 122cb646e2bSRichard Cochran #define E4_RISE (1<<9) /* Indicates direction of Event 4 */ 123cb646e2bSRichard Cochran #define E4_DET (1<<8) /* Indicates Event 4 detected */ 124cb646e2bSRichard Cochran #define E3_RISE (1<<7) /* Indicates direction of Event 3 */ 125cb646e2bSRichard Cochran #define E3_DET (1<<6) /* Indicates Event 3 detected */ 126cb646e2bSRichard Cochran #define E2_RISE (1<<5) /* Indicates direction of Event 2 */ 127cb646e2bSRichard Cochran #define E2_DET (1<<4) /* Indicates Event 2 detected */ 128cb646e2bSRichard Cochran #define E1_RISE (1<<3) /* Indicates direction of Event 1 */ 129cb646e2bSRichard Cochran #define E1_DET (1<<2) /* Indicates Event 1 detected */ 130cb646e2bSRichard Cochran #define E0_RISE (1<<1) /* Indicates direction of Event 0 */ 131cb646e2bSRichard Cochran #define E0_DET (1<<0) /* Indicates Event 0 detected */ 132cb646e2bSRichard Cochran 133cb646e2bSRichard Cochran /* Bit definitions for the PTP_TRIG register */ 134cb646e2bSRichard Cochran #define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */ 135cb646e2bSRichard Cochran #define TRIG_PER (1<<14) /* generate a periodic signal */ 136cb646e2bSRichard Cochran #define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */ 137cb646e2bSRichard Cochran #define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */ 138cb646e2bSRichard Cochran #define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */ 139cb646e2bSRichard Cochran #define TRIG_GPIO_MASK (0xf) 140cb646e2bSRichard Cochran #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */ 141cb646e2bSRichard Cochran #define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */ 142cb646e2bSRichard Cochran #define TRIG_CSEL_MASK (0x7) 143cb646e2bSRichard Cochran #define TRIG_WR (1<<0) /* Trigger Configuration Write */ 144cb646e2bSRichard Cochran 145cb646e2bSRichard Cochran /* Bit definitions for the PTP_EVNT register */ 146cb646e2bSRichard Cochran #define EVNT_RISE (1<<14) /* Event Rise Detect Enable */ 147cb646e2bSRichard Cochran #define EVNT_FALL (1<<13) /* Event Fall Detect Enable */ 148cb646e2bSRichard Cochran #define EVNT_SINGLE (1<<12) /* enable single event capture operation */ 149cb646e2bSRichard Cochran #define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */ 150cb646e2bSRichard Cochran #define EVNT_GPIO_MASK (0xf) 151cb646e2bSRichard Cochran #define EVNT_SEL_SHIFT (1) /* Event Select */ 152cb646e2bSRichard Cochran #define EVNT_SEL_MASK (0x7) 153cb646e2bSRichard Cochran #define EVNT_WR (1<<0) /* Event Configuration Write */ 154cb646e2bSRichard Cochran 155cb646e2bSRichard Cochran /* Bit definitions for the PTP_TXCFG0 register */ 156cb646e2bSRichard Cochran #define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */ 157cb646e2bSRichard Cochran #define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */ 158cb646e2bSRichard Cochran #define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */ 159cb646e2bSRichard Cochran #define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */ 160cb646e2bSRichard Cochran #define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */ 161cb646e2bSRichard Cochran #define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */ 162cb646e2bSRichard Cochran #define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */ 163cb646e2bSRichard Cochran #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */ 164cb646e2bSRichard Cochran #define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */ 165cb646e2bSRichard Cochran #define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */ 166cb646e2bSRichard Cochran #define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */ 167cb646e2bSRichard Cochran #define TX_PTP_VER_MASK (0xf) 168cb646e2bSRichard Cochran #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */ 169cb646e2bSRichard Cochran 170cb646e2bSRichard Cochran /* Bit definitions for the PTP_TXCFG1 register */ 171cb646e2bSRichard Cochran #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */ 172cb646e2bSRichard Cochran #define BYTE0_MASK_MASK (0xff) 173cb646e2bSRichard Cochran #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */ 174cb646e2bSRichard Cochran #define BYTE0_DATA_MASK (0xff) 175cb646e2bSRichard Cochran 176cb646e2bSRichard Cochran /* Bit definitions for the PSF_CFG0 register */ 177cb646e2bSRichard Cochran #define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */ 178cb646e2bSRichard Cochran #define MAC_SRC_ADD_MASK (0x3) 179cb646e2bSRichard Cochran #define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */ 180cb646e2bSRichard Cochran #define MIN_PRE_MASK (0x7) 181cb646e2bSRichard Cochran #define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */ 182cb646e2bSRichard Cochran #define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */ 183cb646e2bSRichard Cochran #define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */ 184cb646e2bSRichard Cochran #define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */ 185cb646e2bSRichard Cochran #define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */ 186cb646e2bSRichard Cochran #define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */ 187cb646e2bSRichard Cochran #define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */ 188cb646e2bSRichard Cochran #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */ 189cb646e2bSRichard Cochran 190cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG0 register */ 191cb646e2bSRichard Cochran #define DOMAIN_EN (1<<15) /* Domain Match Enable */ 192cb646e2bSRichard Cochran #define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */ 193cb646e2bSRichard Cochran #define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */ 194cb646e2bSRichard Cochran #define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */ 195cb646e2bSRichard Cochran #define RX_SLAVE (1<<11) /* Receive Slave Only */ 196cb646e2bSRichard Cochran #define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */ 197cb646e2bSRichard Cochran #define IP1588_EN_MASK (0xf) 198cb646e2bSRichard Cochran #define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */ 199cb646e2bSRichard Cochran #define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */ 200cb646e2bSRichard Cochran #define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */ 201cb646e2bSRichard Cochran #define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */ 202cb646e2bSRichard Cochran #define RX_PTP_VER_MASK (0xf) 203cb646e2bSRichard Cochran #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */ 204cb646e2bSRichard Cochran 205cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG1 register */ 206cb646e2bSRichard Cochran #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */ 207cb646e2bSRichard Cochran #define BYTE0_MASK_MASK (0xff) 208cb646e2bSRichard Cochran #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */ 209cb646e2bSRichard Cochran #define BYTE0_DATA_MASK (0xff) 210cb646e2bSRichard Cochran 211cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG3 register */ 212cb646e2bSRichard Cochran #define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */ 213cb646e2bSRichard Cochran #define TS_MIN_IFG_MASK (0xf) 214cb646e2bSRichard Cochran #define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */ 215cb646e2bSRichard Cochran #define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */ 216cb646e2bSRichard Cochran #define TS_APPEND (1<<9) /* Append Timestamp for L2 */ 217cb646e2bSRichard Cochran #define TS_INSERT (1<<8) /* Enable Timestamp Insertion */ 218cb646e2bSRichard Cochran #define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */ 219cb646e2bSRichard Cochran #define PTP_DOMAIN_MASK (0xff) 220cb646e2bSRichard Cochran 221cb646e2bSRichard Cochran /* Bit definitions for the PTP_RXCFG4 register */ 222cb646e2bSRichard Cochran #define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */ 223cb646e2bSRichard Cochran #define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */ 224cb646e2bSRichard Cochran #define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */ 225cb646e2bSRichard Cochran #define TS_SEC_LEN_MASK (0x3) 226cb646e2bSRichard Cochran #define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */ 227cb646e2bSRichard Cochran #define RXTS_NS_OFF_MASK (0x3f) 228cb646e2bSRichard Cochran #define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */ 229cb646e2bSRichard Cochran #define RXTS_SEC_OFF_MASK (0x3f) 230cb646e2bSRichard Cochran 231cb646e2bSRichard Cochran /* Bit definitions for the PTP_COC register */ 232cb646e2bSRichard Cochran #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */ 233cb646e2bSRichard Cochran #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */ 234cb646e2bSRichard Cochran #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */ 235cb646e2bSRichard Cochran #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */ 236cb646e2bSRichard Cochran #define PTP_CLKDIV_MASK (0xff) 237cb646e2bSRichard Cochran 238cb646e2bSRichard Cochran /* Bit definitions for the PSF_CFG1 register */ 239cb646e2bSRichard Cochran #define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */ 240cb646e2bSRichard Cochran #define PTPRESERVED_MASK (0xf) 241cb646e2bSRichard Cochran #define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */ 242cb646e2bSRichard Cochran #define VERSIONPTP_MASK (0xf) 243cb646e2bSRichard Cochran #define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */ 244cb646e2bSRichard Cochran #define TRANSPORT_SPECIFIC_MASK (0xf) 245cb646e2bSRichard Cochran #define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */ 246cb646e2bSRichard Cochran #define MESSAGETYPE_MASK (0xf) 247cb646e2bSRichard Cochran 248cb646e2bSRichard Cochran /* Bit definitions for the PTP_SFDCFG register */ 249cb646e2bSRichard Cochran #define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */ 250cb646e2bSRichard Cochran #define TX_SFD_GPIO_MASK (0xf) 251cb646e2bSRichard Cochran #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */ 252cb646e2bSRichard Cochran #define RX_SFD_GPIO_MASK (0xf) 253cb646e2bSRichard Cochran 254cb646e2bSRichard Cochran /* Bit definitions for the PTP_INTCTL register */ 255cb646e2bSRichard Cochran #define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */ 256cb646e2bSRichard Cochran #define PTP_INT_GPIO_MASK (0xf) 257cb646e2bSRichard Cochran 258cb646e2bSRichard Cochran /* Bit definitions for the PTP_CLKSRC register */ 259cb646e2bSRichard Cochran #define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */ 260cb646e2bSRichard Cochran #define CLK_SRC_MASK (0x3) 261cb646e2bSRichard Cochran #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */ 262cb646e2bSRichard Cochran #define CLK_SRC_PER_MASK (0x7f) 263cb646e2bSRichard Cochran 264cb646e2bSRichard Cochran /* Bit definitions for the PTP_OFF register */ 265cb646e2bSRichard Cochran #define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */ 266cb646e2bSRichard Cochran #define PTP_OFFSET_MASK (0xff) 267cb646e2bSRichard Cochran 268cb646e2bSRichard Cochran #endif 269