1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the National Semiconductor DP83640 PHYTER 4 * 5 * Copyright (C) 2010 OMICRON electronics GmbH 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/crc32.h> 11 #include <linux/ethtool.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/module.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/netdevice.h> 18 #include <linux/if_vlan.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_classify.h> 21 #include <linux/ptp_clock_kernel.h> 22 23 #include "dp83640_reg.h" 24 #include "phylib.h" 25 26 #define DP83640_PHY_ID 0x20005ce1 27 #define PAGESEL 0x13 28 #define MAX_RXTS 64 29 #define N_EXT_TS 6 30 #define N_PER_OUT 7 31 #define PSF_PTPVER 2 32 #define PSF_EVNT 0x4000 33 #define PSF_RX 0x2000 34 #define PSF_TX 0x1000 35 #define EXT_EVENT 1 36 #define CAL_EVENT 7 37 #define CAL_TRIGGER 1 38 #define DP83640_N_PINS 12 39 40 #define MII_DP83640_MICR 0x11 41 #define MII_DP83640_MISR 0x12 42 43 #define MII_DP83640_MICR_OE 0x1 44 #define MII_DP83640_MICR_IE 0x2 45 46 #define MII_DP83640_MISR_RHF_INT_EN 0x01 47 #define MII_DP83640_MISR_FHF_INT_EN 0x02 48 #define MII_DP83640_MISR_ANC_INT_EN 0x04 49 #define MII_DP83640_MISR_DUP_INT_EN 0x08 50 #define MII_DP83640_MISR_SPD_INT_EN 0x10 51 #define MII_DP83640_MISR_LINK_INT_EN 0x20 52 #define MII_DP83640_MISR_ED_INT_EN 0x40 53 #define MII_DP83640_MISR_LQ_INT_EN 0x80 54 #define MII_DP83640_MISR_ANC_INT 0x400 55 #define MII_DP83640_MISR_DUP_INT 0x800 56 #define MII_DP83640_MISR_SPD_INT 0x1000 57 #define MII_DP83640_MISR_LINK_INT 0x2000 58 #define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\ 59 MII_DP83640_MISR_DUP_INT |\ 60 MII_DP83640_MISR_SPD_INT |\ 61 MII_DP83640_MISR_LINK_INT) 62 63 /* phyter seems to miss the mark by 16 ns */ 64 #define ADJTIME_FIX 16 65 66 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ 67 68 #if defined(__BIG_ENDIAN) 69 #define ENDIAN_FLAG 0 70 #elif defined(__LITTLE_ENDIAN) 71 #define ENDIAN_FLAG PSF_ENDIAN 72 #endif 73 74 struct dp83640_skb_info { 75 int ptp_type; 76 unsigned long tmo; 77 }; 78 79 struct phy_rxts { 80 u16 ns_lo; /* ns[15:0] */ 81 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 82 u16 sec_lo; /* sec[15:0] */ 83 u16 sec_hi; /* sec[31:16] */ 84 u16 seqid; /* sequenceId[15:0] */ 85 u16 msgtype; /* messageType[3:0], hash[11:0] */ 86 }; 87 88 struct phy_txts { 89 u16 ns_lo; /* ns[15:0] */ 90 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 91 u16 sec_lo; /* sec[15:0] */ 92 u16 sec_hi; /* sec[31:16] */ 93 }; 94 95 struct rxts { 96 struct list_head list; 97 unsigned long tmo; 98 u64 ns; 99 u16 seqid; 100 u8 msgtype; 101 u16 hash; 102 }; 103 104 struct dp83640_clock; 105 106 struct dp83640_private { 107 struct list_head list; 108 struct dp83640_clock *clock; 109 struct phy_device *phydev; 110 struct mii_timestamper mii_ts; 111 struct delayed_work ts_work; 112 int hwts_tx_en; 113 int hwts_rx_en; 114 int layer; 115 int version; 116 /* remember state of cfg0 during calibration */ 117 int cfg0; 118 /* remember the last event time stamp */ 119 struct phy_txts edata; 120 /* list of rx timestamps */ 121 struct list_head rxts; 122 struct list_head rxpool; 123 struct rxts rx_pool_data[MAX_RXTS]; 124 /* protects above three fields from concurrent access */ 125 spinlock_t rx_lock; 126 /* queues of incoming and outgoing packets */ 127 struct sk_buff_head rx_queue; 128 struct sk_buff_head tx_queue; 129 }; 130 131 struct dp83640_clock { 132 /* protects extended registers from concurrent access */ 133 struct mutex extreg_lock; 134 /* remembers which page was last selected */ 135 int page; 136 /* our advertised capabilities */ 137 struct ptp_clock_info caps; 138 /* protects the three fields below from concurrent access */ 139 struct mutex clock_lock; 140 /* the one phyter from which we shall read */ 141 struct dp83640_private *chosen; 142 /* list of the other attached phyters, not chosen */ 143 struct list_head phylist; 144 /* reference to our PTP hardware clock */ 145 struct ptp_clock *ptp_clock; 146 /* protected by the PTP core pin configuration lock */ 147 struct ptp_pin_desc pin_config[DP83640_N_PINS]; 148 }; 149 150 /* globals */ 151 152 enum { 153 CALIBRATE_GPIO, 154 PEROUT_GPIO, 155 EXTTS0_GPIO, 156 EXTTS1_GPIO, 157 EXTTS2_GPIO, 158 EXTTS3_GPIO, 159 EXTTS4_GPIO, 160 EXTTS5_GPIO, 161 GPIO_TABLE_SIZE 162 }; 163 164 static int chosen_phy = -1; 165 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 166 1, 2, 3, 4, 8, 9, 10, 11 167 }; 168 169 module_param(chosen_phy, int, 0444); 170 module_param_array(gpio_tab, ushort, NULL, 0444); 171 172 MODULE_PARM_DESC(chosen_phy, 173 "The address of the PHY to use for the ancillary clock features"); 174 MODULE_PARM_DESC(gpio_tab, 175 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 176 177 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 178 { 179 int i, index; 180 181 for (i = 0; i < DP83640_N_PINS; i++) { 182 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 183 pd[i].index = i; 184 } 185 186 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 187 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 188 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 189 return; 190 } 191 } 192 193 index = gpio_tab[CALIBRATE_GPIO] - 1; 194 pd[index].func = PTP_PF_PHYSYNC; 195 pd[index].chan = 0; 196 197 index = gpio_tab[PEROUT_GPIO] - 1; 198 pd[index].func = PTP_PF_PEROUT; 199 pd[index].chan = 0; 200 201 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 202 index = gpio_tab[i] - 1; 203 pd[index].func = PTP_PF_EXTTS; 204 pd[index].chan = i - EXTTS0_GPIO; 205 } 206 } 207 208 static void rx_timestamp_work(struct work_struct *work); 209 210 /* extended register access functions */ 211 212 #define BROADCAST_ADDR 31 213 214 static inline int broadcast_write(struct phy_device *phydev, u32 regnum, 215 u16 val) 216 { 217 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); 218 } 219 220 /* Caller must hold extreg_lock. */ 221 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 222 { 223 struct dp83640_private *dp83640 = phydev->priv; 224 int val; 225 226 if (dp83640->clock->page != page) { 227 broadcast_write(phydev, PAGESEL, page); 228 dp83640->clock->page = page; 229 } 230 val = phy_read(phydev, regnum); 231 232 return val; 233 } 234 235 /* Caller must hold extreg_lock. */ 236 static void ext_write(int broadcast, struct phy_device *phydev, 237 int page, u32 regnum, u16 val) 238 { 239 struct dp83640_private *dp83640 = phydev->priv; 240 241 if (dp83640->clock->page != page) { 242 broadcast_write(phydev, PAGESEL, page); 243 dp83640->clock->page = page; 244 } 245 if (broadcast) 246 broadcast_write(phydev, regnum, val); 247 else 248 phy_write(phydev, regnum, val); 249 } 250 251 /* Caller must hold extreg_lock. */ 252 static int tdr_write(int bc, struct phy_device *dev, 253 const struct timespec64 *ts, u16 cmd) 254 { 255 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 256 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 257 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 258 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 259 260 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 261 262 return 0; 263 } 264 265 /* convert phy timestamps into driver timestamps */ 266 267 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 268 { 269 u32 sec; 270 271 sec = p->sec_lo; 272 sec |= p->sec_hi << 16; 273 274 rxts->ns = p->ns_lo; 275 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 276 rxts->ns += ((u64)sec) * 1000000000ULL; 277 rxts->seqid = p->seqid; 278 rxts->msgtype = (p->msgtype >> 12) & 0xf; 279 rxts->hash = p->msgtype & 0x0fff; 280 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 281 } 282 283 static u64 phy2txts(struct phy_txts *p) 284 { 285 u64 ns; 286 u32 sec; 287 288 sec = p->sec_lo; 289 sec |= p->sec_hi << 16; 290 291 ns = p->ns_lo; 292 ns |= (p->ns_hi & 0x3fff) << 16; 293 ns += ((u64)sec) * 1000000000ULL; 294 295 return ns; 296 } 297 298 static int periodic_output(struct dp83640_clock *clock, 299 struct ptp_clock_request *clkreq, bool on, 300 int trigger) 301 { 302 struct dp83640_private *dp83640 = clock->chosen; 303 struct phy_device *phydev = dp83640->phydev; 304 u32 sec, nsec, pwidth; 305 u16 gpio, ptp_trig, val; 306 307 if (on) { 308 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 309 trigger); 310 if (gpio < 1) 311 return -EINVAL; 312 } else { 313 gpio = 0; 314 } 315 316 ptp_trig = TRIG_WR | 317 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 318 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 319 TRIG_PER | 320 TRIG_PULSE; 321 322 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 323 324 if (!on) { 325 val |= TRIG_DIS; 326 mutex_lock(&clock->extreg_lock); 327 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 328 ext_write(0, phydev, PAGE4, PTP_CTL, val); 329 mutex_unlock(&clock->extreg_lock); 330 return 0; 331 } 332 333 sec = clkreq->perout.start.sec; 334 nsec = clkreq->perout.start.nsec; 335 pwidth = clkreq->perout.period.sec * 1000000000UL; 336 pwidth += clkreq->perout.period.nsec; 337 pwidth /= 2; 338 339 mutex_lock(&clock->extreg_lock); 340 341 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 342 343 /*load trigger*/ 344 val |= TRIG_LOAD; 345 ext_write(0, phydev, PAGE4, PTP_CTL, val); 346 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 347 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 348 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 349 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 350 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 351 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 352 /* Triggers 0 and 1 has programmable pulsewidth2 */ 353 if (trigger < 2) { 354 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 356 } 357 358 /*enable trigger*/ 359 val &= ~TRIG_LOAD; 360 val |= TRIG_EN; 361 ext_write(0, phydev, PAGE4, PTP_CTL, val); 362 363 mutex_unlock(&clock->extreg_lock); 364 return 0; 365 } 366 367 /* ptp clock methods */ 368 369 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 370 { 371 struct dp83640_clock *clock = 372 container_of(ptp, struct dp83640_clock, caps); 373 struct phy_device *phydev = clock->chosen->phydev; 374 u64 rate; 375 int neg_adj = 0; 376 u16 hi, lo; 377 378 if (scaled_ppm < 0) { 379 neg_adj = 1; 380 scaled_ppm = -scaled_ppm; 381 } 382 rate = scaled_ppm; 383 rate <<= 13; 384 rate = div_u64(rate, 15625); 385 386 hi = (rate >> 16) & PTP_RATE_HI_MASK; 387 if (neg_adj) 388 hi |= PTP_RATE_DIR; 389 390 lo = rate & 0xffff; 391 392 mutex_lock(&clock->extreg_lock); 393 394 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 395 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 396 397 mutex_unlock(&clock->extreg_lock); 398 399 return 0; 400 } 401 402 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 403 { 404 struct dp83640_clock *clock = 405 container_of(ptp, struct dp83640_clock, caps); 406 struct phy_device *phydev = clock->chosen->phydev; 407 struct timespec64 ts; 408 int err; 409 410 delta += ADJTIME_FIX; 411 412 ts = ns_to_timespec64(delta); 413 414 mutex_lock(&clock->extreg_lock); 415 416 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 417 418 mutex_unlock(&clock->extreg_lock); 419 420 return err; 421 } 422 423 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, 424 struct timespec64 *ts) 425 { 426 struct dp83640_clock *clock = 427 container_of(ptp, struct dp83640_clock, caps); 428 struct phy_device *phydev = clock->chosen->phydev; 429 unsigned int val[4]; 430 431 mutex_lock(&clock->extreg_lock); 432 433 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 434 435 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 436 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 437 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 438 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 439 440 mutex_unlock(&clock->extreg_lock); 441 442 ts->tv_nsec = val[0] | (val[1] << 16); 443 ts->tv_sec = val[2] | (val[3] << 16); 444 445 return 0; 446 } 447 448 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 449 const struct timespec64 *ts) 450 { 451 struct dp83640_clock *clock = 452 container_of(ptp, struct dp83640_clock, caps); 453 struct phy_device *phydev = clock->chosen->phydev; 454 int err; 455 456 mutex_lock(&clock->extreg_lock); 457 458 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 459 460 mutex_unlock(&clock->extreg_lock); 461 462 return err; 463 } 464 465 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 466 struct ptp_clock_request *rq, int on) 467 { 468 struct dp83640_clock *clock = 469 container_of(ptp, struct dp83640_clock, caps); 470 struct phy_device *phydev = clock->chosen->phydev; 471 unsigned int index; 472 u16 evnt, event_num, gpio_num; 473 474 switch (rq->type) { 475 case PTP_CLK_REQ_EXTTS: 476 /* Reject requests to enable time stamping on both edges. */ 477 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 478 (rq->extts.flags & PTP_ENABLE_FEATURE) && 479 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 480 return -EOPNOTSUPP; 481 482 index = rq->extts.index; 483 if (index >= N_EXT_TS) 484 return -EINVAL; 485 event_num = EXT_EVENT + index; 486 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 487 if (on) { 488 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 489 PTP_PF_EXTTS, index); 490 if (gpio_num < 1) 491 return -EINVAL; 492 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 493 if (rq->extts.flags & PTP_FALLING_EDGE) 494 evnt |= EVNT_FALL; 495 else 496 evnt |= EVNT_RISE; 497 } 498 mutex_lock(&clock->extreg_lock); 499 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 500 mutex_unlock(&clock->extreg_lock); 501 return 0; 502 503 case PTP_CLK_REQ_PEROUT: 504 if (rq->perout.index >= N_PER_OUT) 505 return -EINVAL; 506 return periodic_output(clock, rq, on, rq->perout.index); 507 508 default: 509 break; 510 } 511 512 return -EOPNOTSUPP; 513 } 514 515 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 516 enum ptp_pin_function func, unsigned int chan) 517 { 518 struct dp83640_clock *clock = 519 container_of(ptp, struct dp83640_clock, caps); 520 521 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 522 !list_empty(&clock->phylist)) 523 return 1; 524 525 if (func == PTP_PF_PHYSYNC) 526 return 1; 527 528 return 0; 529 } 530 531 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 532 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 533 534 static void enable_status_frames(struct phy_device *phydev, bool on) 535 { 536 struct dp83640_private *dp83640 = phydev->priv; 537 struct dp83640_clock *clock = dp83640->clock; 538 u16 cfg0 = 0, ver; 539 540 if (on) 541 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 542 543 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 544 545 mutex_lock(&clock->extreg_lock); 546 547 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 548 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 549 550 mutex_unlock(&clock->extreg_lock); 551 552 if (!phydev->attached_dev) { 553 phydev_warn(phydev, 554 "expected to find an attached netdevice\n"); 555 return; 556 } 557 558 if (on) { 559 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 560 phydev_warn(phydev, "failed to add mc address\n"); 561 } else { 562 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 563 phydev_warn(phydev, "failed to delete mc address\n"); 564 } 565 } 566 567 static bool is_status_frame(struct sk_buff *skb, int type) 568 { 569 struct ethhdr *h = eth_hdr(skb); 570 571 if (PTP_CLASS_V2_L2 == type && 572 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 573 return true; 574 else 575 return false; 576 } 577 578 static int expired(struct rxts *rxts) 579 { 580 return time_after(jiffies, rxts->tmo); 581 } 582 583 /* Caller must hold rx_lock. */ 584 static void prune_rx_ts(struct dp83640_private *dp83640) 585 { 586 struct list_head *this, *next; 587 struct rxts *rxts; 588 589 list_for_each_safe(this, next, &dp83640->rxts) { 590 rxts = list_entry(this, struct rxts, list); 591 if (expired(rxts)) { 592 list_del_init(&rxts->list); 593 list_add(&rxts->list, &dp83640->rxpool); 594 } 595 } 596 } 597 598 /* synchronize the phyters so they act as one clock */ 599 600 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 601 { 602 int val; 603 604 phy_write(phydev, PAGESEL, 0); 605 val = phy_read(phydev, PHYCR2); 606 if (on) 607 val |= BC_WRITE; 608 else 609 val &= ~BC_WRITE; 610 phy_write(phydev, PHYCR2, val); 611 phy_write(phydev, PAGESEL, init_page); 612 } 613 614 static void recalibrate(struct dp83640_clock *clock) 615 { 616 s64 now, diff; 617 struct phy_txts event_ts; 618 struct timespec64 ts; 619 struct dp83640_private *tmp; 620 struct phy_device *master = clock->chosen->phydev; 621 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 622 623 trigger = CAL_TRIGGER; 624 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 625 if (cal_gpio < 1) { 626 pr_err("PHY calibration pin not available - PHY is not calibrated."); 627 return; 628 } 629 630 mutex_lock(&clock->extreg_lock); 631 632 /* 633 * enable broadcast, disable status frames, enable ptp clock 634 */ 635 list_for_each_entry(tmp, &clock->phylist, list) { 636 enable_broadcast(tmp->phydev, clock->page, 1); 637 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 638 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 639 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 640 } 641 enable_broadcast(master, clock->page, 1); 642 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 643 ext_write(0, master, PAGE5, PSF_CFG0, 0); 644 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 645 646 /* 647 * enable an event timestamp 648 */ 649 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 650 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 651 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 652 653 list_for_each_entry(tmp, &clock->phylist, list) 654 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 655 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 656 657 /* 658 * configure a trigger 659 */ 660 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 661 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 662 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 663 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 664 665 /* load trigger */ 666 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 667 val |= TRIG_LOAD; 668 ext_write(0, master, PAGE4, PTP_CTL, val); 669 670 /* enable trigger */ 671 val &= ~TRIG_LOAD; 672 val |= TRIG_EN; 673 ext_write(0, master, PAGE4, PTP_CTL, val); 674 675 /* disable trigger */ 676 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 677 val |= TRIG_DIS; 678 ext_write(0, master, PAGE4, PTP_CTL, val); 679 680 /* 681 * read out and correct offsets 682 */ 683 val = ext_read(master, PAGE4, PTP_STS); 684 phydev_info(master, "master PTP_STS 0x%04hx\n", val); 685 val = ext_read(master, PAGE4, PTP_ESTS); 686 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val); 687 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 688 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 689 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 690 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 691 now = phy2txts(&event_ts); 692 693 list_for_each_entry(tmp, &clock->phylist, list) { 694 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 695 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); 696 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 697 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); 698 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 699 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 700 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 701 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 702 diff = now - (s64) phy2txts(&event_ts); 703 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", 704 diff); 705 diff += ADJTIME_FIX; 706 ts = ns_to_timespec64(diff); 707 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 708 } 709 710 /* 711 * restore status frames 712 */ 713 list_for_each_entry(tmp, &clock->phylist, list) 714 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 715 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 716 717 mutex_unlock(&clock->extreg_lock); 718 } 719 720 /* time stamping methods */ 721 722 static inline u16 exts_chan_to_edata(int ch) 723 { 724 return 1 << ((ch + EXT_EVENT) * 2); 725 } 726 727 static int decode_evnt(struct dp83640_private *dp83640, 728 void *data, int len, u16 ests) 729 { 730 struct phy_txts *phy_txts; 731 struct ptp_clock_event event; 732 int i, parsed; 733 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 734 u16 ext_status = 0; 735 736 /* calculate length of the event timestamp status message */ 737 if (ests & MULT_EVNT) 738 parsed = (words + 2) * sizeof(u16); 739 else 740 parsed = (words + 1) * sizeof(u16); 741 742 /* check if enough data is available */ 743 if (len < parsed) 744 return len; 745 746 if (ests & MULT_EVNT) { 747 ext_status = *(u16 *) data; 748 data += sizeof(ext_status); 749 } 750 751 phy_txts = data; 752 753 switch (words) { 754 case 3: 755 dp83640->edata.sec_hi = phy_txts->sec_hi; 756 fallthrough; 757 case 2: 758 dp83640->edata.sec_lo = phy_txts->sec_lo; 759 fallthrough; 760 case 1: 761 dp83640->edata.ns_hi = phy_txts->ns_hi; 762 fallthrough; 763 case 0: 764 dp83640->edata.ns_lo = phy_txts->ns_lo; 765 } 766 767 if (!ext_status) { 768 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 769 ext_status = exts_chan_to_edata(i); 770 } 771 772 event.type = PTP_CLOCK_EXTTS; 773 event.timestamp = phy2txts(&dp83640->edata); 774 775 /* Compensate for input path and synchronization delays */ 776 event.timestamp -= 35; 777 778 for (i = 0; i < N_EXT_TS; i++) { 779 if (ext_status & exts_chan_to_edata(i)) { 780 event.index = i; 781 ptp_clock_event(dp83640->clock->ptp_clock, &event); 782 } 783 } 784 785 return parsed; 786 } 787 788 #define DP83640_PACKET_HASH_LEN 10 789 790 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 791 { 792 struct ptp_header *hdr; 793 u8 msgtype; 794 u16 seqid; 795 u16 hash; 796 797 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 798 799 hdr = ptp_parse_header(skb, type); 800 if (!hdr) 801 return 0; 802 803 msgtype = ptp_get_msgtype(hdr, type); 804 805 if (rxts->msgtype != (msgtype & 0xf)) 806 return 0; 807 808 seqid = be16_to_cpu(hdr->sequence_id); 809 if (rxts->seqid != seqid) 810 return 0; 811 812 hash = ether_crc(DP83640_PACKET_HASH_LEN, 813 (unsigned char *)&hdr->source_port_identity) >> 20; 814 if (rxts->hash != hash) 815 return 0; 816 817 return 1; 818 } 819 820 static void decode_rxts(struct dp83640_private *dp83640, 821 struct phy_rxts *phy_rxts) 822 { 823 struct rxts *rxts; 824 struct skb_shared_hwtstamps *shhwtstamps = NULL; 825 struct sk_buff *skb; 826 unsigned long flags; 827 u8 overflow; 828 829 overflow = (phy_rxts->ns_hi >> 14) & 0x3; 830 if (overflow) 831 pr_debug("rx timestamp queue overflow, count %d\n", overflow); 832 833 spin_lock_irqsave(&dp83640->rx_lock, flags); 834 835 prune_rx_ts(dp83640); 836 837 if (list_empty(&dp83640->rxpool)) { 838 pr_debug("rx timestamp pool is empty\n"); 839 goto out; 840 } 841 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 842 list_del_init(&rxts->list); 843 phy2rxts(phy_rxts, rxts); 844 845 spin_lock(&dp83640->rx_queue.lock); 846 skb_queue_walk(&dp83640->rx_queue, skb) { 847 struct dp83640_skb_info *skb_info; 848 849 skb_info = (struct dp83640_skb_info *)skb->cb; 850 if (match(skb, skb_info->ptp_type, rxts)) { 851 __skb_unlink(skb, &dp83640->rx_queue); 852 shhwtstamps = skb_hwtstamps(skb); 853 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 854 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 855 list_add(&rxts->list, &dp83640->rxpool); 856 break; 857 } 858 } 859 spin_unlock(&dp83640->rx_queue.lock); 860 861 if (!shhwtstamps) 862 list_add_tail(&rxts->list, &dp83640->rxts); 863 out: 864 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 865 866 if (shhwtstamps) 867 netif_rx(skb); 868 } 869 870 static void decode_txts(struct dp83640_private *dp83640, 871 struct phy_txts *phy_txts) 872 { 873 struct skb_shared_hwtstamps shhwtstamps; 874 struct dp83640_skb_info *skb_info; 875 struct sk_buff *skb; 876 u8 overflow; 877 u64 ns; 878 879 /* We must already have the skb that triggered this. */ 880 again: 881 skb = skb_dequeue(&dp83640->tx_queue); 882 if (!skb) { 883 pr_debug("have timestamp but tx_queue empty\n"); 884 return; 885 } 886 887 overflow = (phy_txts->ns_hi >> 14) & 0x3; 888 if (overflow) { 889 pr_debug("tx timestamp queue overflow, count %d\n", overflow); 890 while (skb) { 891 kfree_skb(skb); 892 skb = skb_dequeue(&dp83640->tx_queue); 893 } 894 return; 895 } 896 skb_info = (struct dp83640_skb_info *)skb->cb; 897 if (time_after(jiffies, skb_info->tmo)) { 898 kfree_skb(skb); 899 goto again; 900 } 901 902 ns = phy2txts(phy_txts); 903 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 904 shhwtstamps.hwtstamp = ns_to_ktime(ns); 905 skb_complete_tx_timestamp(skb, &shhwtstamps); 906 } 907 908 static void decode_status_frame(struct dp83640_private *dp83640, 909 struct sk_buff *skb) 910 { 911 struct phy_rxts *phy_rxts; 912 struct phy_txts *phy_txts; 913 u8 *ptr; 914 int len, size; 915 u16 ests, type; 916 917 ptr = skb->data + 2; 918 919 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 920 921 type = *(u16 *)ptr; 922 ests = type & 0x0fff; 923 type = type & 0xf000; 924 len -= sizeof(type); 925 ptr += sizeof(type); 926 927 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 928 929 phy_rxts = (struct phy_rxts *) ptr; 930 decode_rxts(dp83640, phy_rxts); 931 size = sizeof(*phy_rxts); 932 933 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 934 935 phy_txts = (struct phy_txts *) ptr; 936 decode_txts(dp83640, phy_txts); 937 size = sizeof(*phy_txts); 938 939 } else if (PSF_EVNT == type) { 940 941 size = decode_evnt(dp83640, ptr, len, ests); 942 943 } else { 944 size = 0; 945 break; 946 } 947 ptr += size; 948 } 949 } 950 951 static void dp83640_clock_init(struct dp83640_clock *clock) 952 { 953 mutex_init(&clock->extreg_lock); 954 mutex_init(&clock->clock_lock); 955 INIT_LIST_HEAD(&clock->phylist); 956 clock->caps.pin_config = clock->pin_config; 957 clock->caps.owner = THIS_MODULE; 958 sprintf(clock->caps.name, "dp83640 timer"); 959 clock->caps.max_adj = 1953124; 960 clock->caps.n_alarm = 0; 961 clock->caps.n_ext_ts = N_EXT_TS; 962 clock->caps.n_per_out = N_PER_OUT; 963 clock->caps.n_pins = DP83640_N_PINS; 964 clock->caps.pps = 0; 965 clock->caps.supported_extts_flags = PTP_RISING_EDGE | 966 PTP_FALLING_EDGE | 967 PTP_STRICT_FLAGS; 968 clock->caps.adjfine = ptp_dp83640_adjfine; 969 clock->caps.adjtime = ptp_dp83640_adjtime; 970 clock->caps.gettime64 = ptp_dp83640_gettime; 971 clock->caps.settime64 = ptp_dp83640_settime; 972 clock->caps.enable = ptp_dp83640_enable; 973 clock->caps.verify = ptp_dp83640_verify; 974 /* Initialize the runtime pin configuration from gpio_tab. */ 975 dp83640_gpio_defaults(clock->caps.pin_config); 976 } 977 978 static int choose_this_phy(struct dp83640_clock *clock, 979 struct phy_device *phydev) 980 { 981 if (chosen_phy == -1 && !clock->chosen) 982 return 1; 983 984 if (chosen_phy == phydev->mdio.addr) 985 return 1; 986 987 return 0; 988 } 989 990 static int dp83640_soft_reset(struct phy_device *phydev) 991 { 992 int ret; 993 994 ret = genphy_soft_reset(phydev); 995 if (ret < 0) 996 return ret; 997 998 /* From DP83640 datasheet: "Software driver code must wait 3 us 999 * following a software reset before allowing further serial MII 1000 * operations with the DP83640." 1001 */ 1002 udelay(10); /* Taking udelay inaccuracy into account */ 1003 1004 return 0; 1005 } 1006 1007 static int dp83640_config_init(struct phy_device *phydev) 1008 { 1009 struct dp83640_private *dp83640 = phydev->priv; 1010 struct dp83640_clock *clock = dp83640->clock; 1011 1012 if (clock->chosen && !list_empty(&clock->phylist)) 1013 recalibrate(clock); 1014 else { 1015 mutex_lock(&clock->extreg_lock); 1016 enable_broadcast(phydev, clock->page, 1); 1017 mutex_unlock(&clock->extreg_lock); 1018 } 1019 1020 enable_status_frames(phydev, true); 1021 1022 mutex_lock(&clock->extreg_lock); 1023 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1024 mutex_unlock(&clock->extreg_lock); 1025 1026 return 0; 1027 } 1028 1029 static int dp83640_ack_interrupt(struct phy_device *phydev) 1030 { 1031 int err = phy_read(phydev, MII_DP83640_MISR); 1032 1033 if (err < 0) 1034 return err; 1035 1036 return 0; 1037 } 1038 1039 static int dp83640_config_intr(struct phy_device *phydev) 1040 { 1041 int micr; 1042 int misr; 1043 int err; 1044 1045 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1046 err = dp83640_ack_interrupt(phydev); 1047 if (err) 1048 return err; 1049 1050 misr = phy_read(phydev, MII_DP83640_MISR); 1051 if (misr < 0) 1052 return misr; 1053 misr |= 1054 (MII_DP83640_MISR_ANC_INT_EN | 1055 MII_DP83640_MISR_DUP_INT_EN | 1056 MII_DP83640_MISR_SPD_INT_EN | 1057 MII_DP83640_MISR_LINK_INT_EN); 1058 err = phy_write(phydev, MII_DP83640_MISR, misr); 1059 if (err < 0) 1060 return err; 1061 1062 micr = phy_read(phydev, MII_DP83640_MICR); 1063 if (micr < 0) 1064 return micr; 1065 micr |= 1066 (MII_DP83640_MICR_OE | 1067 MII_DP83640_MICR_IE); 1068 return phy_write(phydev, MII_DP83640_MICR, micr); 1069 } else { 1070 micr = phy_read(phydev, MII_DP83640_MICR); 1071 if (micr < 0) 1072 return micr; 1073 micr &= 1074 ~(MII_DP83640_MICR_OE | 1075 MII_DP83640_MICR_IE); 1076 err = phy_write(phydev, MII_DP83640_MICR, micr); 1077 if (err < 0) 1078 return err; 1079 1080 misr = phy_read(phydev, MII_DP83640_MISR); 1081 if (misr < 0) 1082 return misr; 1083 misr &= 1084 ~(MII_DP83640_MISR_ANC_INT_EN | 1085 MII_DP83640_MISR_DUP_INT_EN | 1086 MII_DP83640_MISR_SPD_INT_EN | 1087 MII_DP83640_MISR_LINK_INT_EN); 1088 err = phy_write(phydev, MII_DP83640_MISR, misr); 1089 if (err) 1090 return err; 1091 1092 return dp83640_ack_interrupt(phydev); 1093 } 1094 } 1095 1096 static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev) 1097 { 1098 int irq_status; 1099 1100 irq_status = phy_read(phydev, MII_DP83640_MISR); 1101 if (irq_status < 0) { 1102 phy_error(phydev); 1103 return IRQ_NONE; 1104 } 1105 1106 if (!(irq_status & MII_DP83640_MISR_INT_MASK)) 1107 return IRQ_NONE; 1108 1109 phy_trigger_machine(phydev); 1110 1111 return IRQ_HANDLED; 1112 } 1113 1114 static int dp83640_hwtstamp_get(struct mii_timestamper *mii_ts, 1115 struct kernel_hwtstamp_config *cfg) 1116 { 1117 struct dp83640_private *dp83640 = 1118 container_of(mii_ts, struct dp83640_private, mii_ts); 1119 1120 cfg->rx_filter = dp83640->hwts_rx_en; 1121 cfg->tx_type = dp83640->hwts_tx_en; 1122 1123 return 0; 1124 } 1125 1126 static int dp83640_hwtstamp_set(struct mii_timestamper *mii_ts, 1127 struct kernel_hwtstamp_config *cfg, 1128 struct netlink_ext_ack *extack) 1129 { 1130 struct dp83640_private *dp83640 = 1131 container_of(mii_ts, struct dp83640_private, mii_ts); 1132 u16 txcfg0, rxcfg0; 1133 1134 if (cfg->tx_type < 0 || cfg->tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1135 return -ERANGE; 1136 1137 dp83640->hwts_tx_en = cfg->tx_type; 1138 1139 switch (cfg->rx_filter) { 1140 case HWTSTAMP_FILTER_NONE: 1141 dp83640->hwts_rx_en = 0; 1142 dp83640->layer = 0; 1143 dp83640->version = 0; 1144 break; 1145 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1146 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1147 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1148 dp83640->hwts_rx_en = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1149 dp83640->layer = PTP_CLASS_L4; 1150 dp83640->version = PTP_CLASS_V1; 1151 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1152 break; 1153 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1154 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1155 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1156 dp83640->hwts_rx_en = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1157 dp83640->layer = PTP_CLASS_L4; 1158 dp83640->version = PTP_CLASS_V2; 1159 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1160 break; 1161 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1162 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1163 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1164 dp83640->hwts_rx_en = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1165 dp83640->layer = PTP_CLASS_L2; 1166 dp83640->version = PTP_CLASS_V2; 1167 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1168 break; 1169 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1170 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1171 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1172 dp83640->hwts_rx_en = HWTSTAMP_FILTER_PTP_V2_EVENT; 1173 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 1174 dp83640->version = PTP_CLASS_V2; 1175 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1176 break; 1177 default: 1178 return -ERANGE; 1179 } 1180 1181 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1182 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1183 1184 if (dp83640->layer & PTP_CLASS_L2) { 1185 txcfg0 |= TX_L2_EN; 1186 rxcfg0 |= RX_L2_EN; 1187 } 1188 if (dp83640->layer & PTP_CLASS_L4) { 1189 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1190 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1191 } 1192 1193 if (dp83640->hwts_tx_en) 1194 txcfg0 |= TX_TS_EN; 1195 1196 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1197 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1198 1199 if (dp83640->hwts_rx_en) 1200 rxcfg0 |= RX_TS_EN; 1201 1202 mutex_lock(&dp83640->clock->extreg_lock); 1203 1204 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); 1205 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1206 1207 mutex_unlock(&dp83640->clock->extreg_lock); 1208 1209 return 0; 1210 } 1211 1212 static void rx_timestamp_work(struct work_struct *work) 1213 { 1214 struct dp83640_private *dp83640 = 1215 container_of(work, struct dp83640_private, ts_work.work); 1216 struct sk_buff *skb; 1217 1218 /* Deliver expired packets. */ 1219 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1220 struct dp83640_skb_info *skb_info; 1221 1222 skb_info = (struct dp83640_skb_info *)skb->cb; 1223 if (!time_after(jiffies, skb_info->tmo)) { 1224 skb_queue_head(&dp83640->rx_queue, skb); 1225 break; 1226 } 1227 1228 netif_rx(skb); 1229 } 1230 1231 if (!skb_queue_empty(&dp83640->rx_queue)) 1232 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1233 } 1234 1235 static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts, 1236 struct sk_buff *skb, int type) 1237 { 1238 struct dp83640_private *dp83640 = 1239 container_of(mii_ts, struct dp83640_private, mii_ts); 1240 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1241 struct list_head *this, *next; 1242 struct rxts *rxts; 1243 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1244 unsigned long flags; 1245 1246 if (is_status_frame(skb, type)) { 1247 decode_status_frame(dp83640, skb); 1248 kfree_skb(skb); 1249 return true; 1250 } 1251 1252 if (!dp83640->hwts_rx_en) 1253 return false; 1254 1255 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) 1256 return false; 1257 1258 spin_lock_irqsave(&dp83640->rx_lock, flags); 1259 prune_rx_ts(dp83640); 1260 list_for_each_safe(this, next, &dp83640->rxts) { 1261 rxts = list_entry(this, struct rxts, list); 1262 if (match(skb, type, rxts)) { 1263 shhwtstamps = skb_hwtstamps(skb); 1264 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1265 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1266 list_del_init(&rxts->list); 1267 list_add(&rxts->list, &dp83640->rxpool); 1268 break; 1269 } 1270 } 1271 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1272 1273 if (!shhwtstamps) { 1274 skb_info->ptp_type = type; 1275 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1276 skb_queue_tail(&dp83640->rx_queue, skb); 1277 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1278 } else { 1279 netif_rx(skb); 1280 } 1281 1282 return true; 1283 } 1284 1285 static void dp83640_txtstamp(struct mii_timestamper *mii_ts, 1286 struct sk_buff *skb, int type) 1287 { 1288 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1289 struct dp83640_private *dp83640 = 1290 container_of(mii_ts, struct dp83640_private, mii_ts); 1291 1292 switch (dp83640->hwts_tx_en) { 1293 1294 case HWTSTAMP_TX_ONESTEP_SYNC: 1295 if (ptp_msg_is_sync(skb, type)) { 1296 kfree_skb(skb); 1297 return; 1298 } 1299 fallthrough; 1300 case HWTSTAMP_TX_ON: 1301 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1302 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1303 skb_queue_tail(&dp83640->tx_queue, skb); 1304 break; 1305 1306 case HWTSTAMP_TX_OFF: 1307 default: 1308 kfree_skb(skb); 1309 break; 1310 } 1311 } 1312 1313 static int dp83640_ts_info(struct mii_timestamper *mii_ts, 1314 struct kernel_ethtool_ts_info *info) 1315 { 1316 struct dp83640_private *dp83640 = 1317 container_of(mii_ts, struct dp83640_private, mii_ts); 1318 1319 info->so_timestamping = 1320 SOF_TIMESTAMPING_TX_HARDWARE | 1321 SOF_TIMESTAMPING_RX_HARDWARE | 1322 SOF_TIMESTAMPING_RAW_HARDWARE; 1323 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1324 info->tx_types = 1325 (1 << HWTSTAMP_TX_OFF) | 1326 (1 << HWTSTAMP_TX_ON) | 1327 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1328 info->rx_filters = 1329 (1 << HWTSTAMP_FILTER_NONE) | 1330 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1331 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1332 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1333 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1334 return 0; 1335 } 1336 1337 static int dp83640_probe(struct phy_device *phydev) 1338 { 1339 struct dp83640_private *dp83640; 1340 struct dp83640_clock *clock; 1341 int err, i; 1342 1343 if (phydev->mdio.addr == BROADCAST_ADDR) 1344 return 0; 1345 1346 err = phy_package_join(phydev, BROADCAST_ADDR, sizeof(*clock)); 1347 if (err) 1348 return err; 1349 1350 clock = phy_package_get_priv(phydev); 1351 /* Ensure other PHY probes wait for shared clock initialization. */ 1352 phy_package_lock(phydev); 1353 if (phy_package_probe_once(phydev)) 1354 dp83640_clock_init(clock); 1355 phy_package_unlock(phydev); 1356 1357 mutex_lock(&clock->clock_lock); 1358 1359 dp83640 = kzalloc_obj(struct dp83640_private); 1360 if (!dp83640) { 1361 err = -ENOMEM; 1362 goto no_memory; 1363 } 1364 1365 dp83640->phydev = phydev; 1366 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; 1367 dp83640->mii_ts.txtstamp = dp83640_txtstamp; 1368 dp83640->mii_ts.hwtstamp_set = dp83640_hwtstamp_set; 1369 dp83640->mii_ts.hwtstamp_get = dp83640_hwtstamp_get; 1370 dp83640->mii_ts.ts_info = dp83640_ts_info; 1371 1372 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); 1373 INIT_LIST_HEAD(&dp83640->rxts); 1374 INIT_LIST_HEAD(&dp83640->rxpool); 1375 for (i = 0; i < MAX_RXTS; i++) 1376 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1377 1378 /* Timestamp selected by default to keep legacy API */ 1379 phydev->default_timestamp = true; 1380 phydev->mii_ts = &dp83640->mii_ts; 1381 phydev->priv = dp83640; 1382 1383 spin_lock_init(&dp83640->rx_lock); 1384 skb_queue_head_init(&dp83640->rx_queue); 1385 skb_queue_head_init(&dp83640->tx_queue); 1386 1387 dp83640->clock = clock; 1388 1389 if (choose_this_phy(clock, phydev)) { 1390 clock->chosen = dp83640; 1391 clock->ptp_clock = ptp_clock_register(&clock->caps, 1392 &phydev->mdio.dev); 1393 if (IS_ERR(clock->ptp_clock)) { 1394 err = PTR_ERR(clock->ptp_clock); 1395 goto no_register; 1396 } 1397 } else 1398 list_add_tail(&dp83640->list, &clock->phylist); 1399 1400 mutex_unlock(&clock->clock_lock); 1401 1402 return 0; 1403 1404 no_register: 1405 clock->chosen = NULL; 1406 clock->ptp_clock = NULL; 1407 phydev->default_timestamp = false; 1408 phydev->mii_ts = NULL; 1409 phydev->priv = NULL; 1410 kfree(dp83640); 1411 no_memory: 1412 mutex_unlock(&clock->clock_lock); 1413 phy_package_leave(phydev); 1414 return err; 1415 } 1416 1417 static void dp83640_remove(struct phy_device *phydev) 1418 { 1419 struct dp83640_clock *clock; 1420 struct list_head *this, *next; 1421 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1422 1423 if (phydev->mdio.addr == BROADCAST_ADDR) 1424 return; 1425 1426 phydev->mii_ts = NULL; 1427 1428 enable_status_frames(phydev, false); 1429 cancel_delayed_work_sync(&dp83640->ts_work); 1430 1431 skb_queue_purge(&dp83640->rx_queue); 1432 skb_queue_purge(&dp83640->tx_queue); 1433 1434 clock = dp83640->clock; 1435 mutex_lock(&clock->clock_lock); 1436 1437 if (dp83640 == clock->chosen) { 1438 ptp_clock_unregister(clock->ptp_clock); 1439 clock->chosen = NULL; 1440 } else { 1441 list_for_each_safe(this, next, &clock->phylist) { 1442 tmp = list_entry(this, struct dp83640_private, list); 1443 if (tmp == dp83640) { 1444 list_del_init(&tmp->list); 1445 break; 1446 } 1447 } 1448 } 1449 1450 mutex_unlock(&clock->clock_lock); 1451 kfree(dp83640); 1452 1453 phy_package_leave(phydev); 1454 } 1455 1456 static struct phy_driver dp83640_driver[] = { 1457 { 1458 .phy_id = DP83640_PHY_ID, 1459 .phy_id_mask = 0xfffffff0, 1460 .name = "NatSemi DP83640", 1461 /* PHY_BASIC_FEATURES */ 1462 .probe = dp83640_probe, 1463 .remove = dp83640_remove, 1464 .soft_reset = dp83640_soft_reset, 1465 .config_init = dp83640_config_init, 1466 .config_intr = dp83640_config_intr, 1467 .handle_interrupt = dp83640_handle_interrupt, 1468 }, 1469 }; 1470 1471 module_phy_driver(dp83640_driver); 1472 1473 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1474 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1475 MODULE_LICENSE("GPL"); 1476 1477 static const struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1478 { DP83640_PHY_ID, 0xfffffff0 }, 1479 { } 1480 }; 1481 1482 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1483