1 /* 2 * Driver for the National Semiconductor DP83640 PHYTER 3 * 4 * Copyright (C) 2010 OMICRON electronics GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/ethtool.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/mii.h> 27 #include <linux/module.h> 28 #include <linux/net_tstamp.h> 29 #include <linux/netdevice.h> 30 #include <linux/if_vlan.h> 31 #include <linux/phy.h> 32 #include <linux/ptp_classify.h> 33 #include <linux/ptp_clock_kernel.h> 34 35 #include "dp83640_reg.h" 36 37 #define DP83640_PHY_ID 0x20005ce1 38 #define PAGESEL 0x13 39 #define LAYER4 0x02 40 #define LAYER2 0x01 41 #define MAX_RXTS 64 42 #define N_EXT_TS 6 43 #define PSF_PTPVER 2 44 #define PSF_EVNT 0x4000 45 #define PSF_RX 0x2000 46 #define PSF_TX 0x1000 47 #define EXT_EVENT 1 48 #define CAL_EVENT 7 49 #define CAL_TRIGGER 7 50 #define PER_TRIGGER 6 51 #define DP83640_N_PINS 12 52 53 #define MII_DP83640_MICR 0x11 54 #define MII_DP83640_MISR 0x12 55 56 #define MII_DP83640_MICR_OE 0x1 57 #define MII_DP83640_MICR_IE 0x2 58 59 #define MII_DP83640_MISR_RHF_INT_EN 0x01 60 #define MII_DP83640_MISR_FHF_INT_EN 0x02 61 #define MII_DP83640_MISR_ANC_INT_EN 0x04 62 #define MII_DP83640_MISR_DUP_INT_EN 0x08 63 #define MII_DP83640_MISR_SPD_INT_EN 0x10 64 #define MII_DP83640_MISR_LINK_INT_EN 0x20 65 #define MII_DP83640_MISR_ED_INT_EN 0x40 66 #define MII_DP83640_MISR_LQ_INT_EN 0x80 67 68 /* phyter seems to miss the mark by 16 ns */ 69 #define ADJTIME_FIX 16 70 71 #if defined(__BIG_ENDIAN) 72 #define ENDIAN_FLAG 0 73 #elif defined(__LITTLE_ENDIAN) 74 #define ENDIAN_FLAG PSF_ENDIAN 75 #endif 76 77 #define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb)) 78 79 struct phy_rxts { 80 u16 ns_lo; /* ns[15:0] */ 81 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 82 u16 sec_lo; /* sec[15:0] */ 83 u16 sec_hi; /* sec[31:16] */ 84 u16 seqid; /* sequenceId[15:0] */ 85 u16 msgtype; /* messageType[3:0], hash[11:0] */ 86 }; 87 88 struct phy_txts { 89 u16 ns_lo; /* ns[15:0] */ 90 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 91 u16 sec_lo; /* sec[15:0] */ 92 u16 sec_hi; /* sec[31:16] */ 93 }; 94 95 struct rxts { 96 struct list_head list; 97 unsigned long tmo; 98 u64 ns; 99 u16 seqid; 100 u8 msgtype; 101 u16 hash; 102 }; 103 104 struct dp83640_clock; 105 106 struct dp83640_private { 107 struct list_head list; 108 struct dp83640_clock *clock; 109 struct phy_device *phydev; 110 struct work_struct ts_work; 111 int hwts_tx_en; 112 int hwts_rx_en; 113 int layer; 114 int version; 115 /* remember state of cfg0 during calibration */ 116 int cfg0; 117 /* remember the last event time stamp */ 118 struct phy_txts edata; 119 /* list of rx timestamps */ 120 struct list_head rxts; 121 struct list_head rxpool; 122 struct rxts rx_pool_data[MAX_RXTS]; 123 /* protects above three fields from concurrent access */ 124 spinlock_t rx_lock; 125 /* queues of incoming and outgoing packets */ 126 struct sk_buff_head rx_queue; 127 struct sk_buff_head tx_queue; 128 }; 129 130 struct dp83640_clock { 131 /* keeps the instance in the 'phyter_clocks' list */ 132 struct list_head list; 133 /* we create one clock instance per MII bus */ 134 struct mii_bus *bus; 135 /* protects extended registers from concurrent access */ 136 struct mutex extreg_lock; 137 /* remembers which page was last selected */ 138 int page; 139 /* our advertised capabilities */ 140 struct ptp_clock_info caps; 141 /* protects the three fields below from concurrent access */ 142 struct mutex clock_lock; 143 /* the one phyter from which we shall read */ 144 struct dp83640_private *chosen; 145 /* list of the other attached phyters, not chosen */ 146 struct list_head phylist; 147 /* reference to our PTP hardware clock */ 148 struct ptp_clock *ptp_clock; 149 }; 150 151 /* globals */ 152 153 enum { 154 CALIBRATE_GPIO, 155 PEROUT_GPIO, 156 EXTTS0_GPIO, 157 EXTTS1_GPIO, 158 EXTTS2_GPIO, 159 EXTTS3_GPIO, 160 EXTTS4_GPIO, 161 EXTTS5_GPIO, 162 GPIO_TABLE_SIZE 163 }; 164 165 static int chosen_phy = -1; 166 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 167 1, 2, 3, 4, 8, 9, 10, 11 168 }; 169 170 module_param(chosen_phy, int, 0444); 171 module_param_array(gpio_tab, ushort, NULL, 0444); 172 173 MODULE_PARM_DESC(chosen_phy, \ 174 "The address of the PHY to use for the ancillary clock features"); 175 MODULE_PARM_DESC(gpio_tab, \ 176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 177 178 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 179 { 180 int i, index; 181 182 for (i = 0; i < DP83640_N_PINS; i++) { 183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 184 pd[i].index = i; 185 } 186 187 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 190 return; 191 } 192 } 193 194 index = gpio_tab[CALIBRATE_GPIO] - 1; 195 pd[index].func = PTP_PF_PHYSYNC; 196 pd[index].chan = 0; 197 198 index = gpio_tab[PEROUT_GPIO] - 1; 199 pd[index].func = PTP_PF_PEROUT; 200 pd[index].chan = 0; 201 202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 203 index = gpio_tab[i] - 1; 204 pd[index].func = PTP_PF_EXTTS; 205 pd[index].chan = i - EXTTS0_GPIO; 206 } 207 } 208 209 /* a list of clocks and a mutex to protect it */ 210 static LIST_HEAD(phyter_clocks); 211 static DEFINE_MUTEX(phyter_clocks_lock); 212 213 static void rx_timestamp_work(struct work_struct *work); 214 215 /* extended register access functions */ 216 217 #define BROADCAST_ADDR 31 218 219 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val) 220 { 221 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val); 222 } 223 224 /* Caller must hold extreg_lock. */ 225 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 226 { 227 struct dp83640_private *dp83640 = phydev->priv; 228 int val; 229 230 if (dp83640->clock->page != page) { 231 broadcast_write(phydev->bus, PAGESEL, page); 232 dp83640->clock->page = page; 233 } 234 val = phy_read(phydev, regnum); 235 236 return val; 237 } 238 239 /* Caller must hold extreg_lock. */ 240 static void ext_write(int broadcast, struct phy_device *phydev, 241 int page, u32 regnum, u16 val) 242 { 243 struct dp83640_private *dp83640 = phydev->priv; 244 245 if (dp83640->clock->page != page) { 246 broadcast_write(phydev->bus, PAGESEL, page); 247 dp83640->clock->page = page; 248 } 249 if (broadcast) 250 broadcast_write(phydev->bus, regnum, val); 251 else 252 phy_write(phydev, regnum, val); 253 } 254 255 /* Caller must hold extreg_lock. */ 256 static int tdr_write(int bc, struct phy_device *dev, 257 const struct timespec *ts, u16 cmd) 258 { 259 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 263 264 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 265 266 return 0; 267 } 268 269 /* convert phy timestamps into driver timestamps */ 270 271 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 272 { 273 u32 sec; 274 275 sec = p->sec_lo; 276 sec |= p->sec_hi << 16; 277 278 rxts->ns = p->ns_lo; 279 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 280 rxts->ns += ((u64)sec) * 1000000000ULL; 281 rxts->seqid = p->seqid; 282 rxts->msgtype = (p->msgtype >> 12) & 0xf; 283 rxts->hash = p->msgtype & 0x0fff; 284 rxts->tmo = jiffies + 2; 285 } 286 287 static u64 phy2txts(struct phy_txts *p) 288 { 289 u64 ns; 290 u32 sec; 291 292 sec = p->sec_lo; 293 sec |= p->sec_hi << 16; 294 295 ns = p->ns_lo; 296 ns |= (p->ns_hi & 0x3fff) << 16; 297 ns += ((u64)sec) * 1000000000ULL; 298 299 return ns; 300 } 301 302 static int periodic_output(struct dp83640_clock *clock, 303 struct ptp_clock_request *clkreq, bool on) 304 { 305 struct dp83640_private *dp83640 = clock->chosen; 306 struct phy_device *phydev = dp83640->phydev; 307 u32 sec, nsec, pwidth; 308 u16 gpio, ptp_trig, trigger, val; 309 310 if (on) { 311 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 0); 312 if (gpio < 1) 313 return -EINVAL; 314 } else { 315 gpio = 0; 316 } 317 318 trigger = PER_TRIGGER; 319 320 ptp_trig = TRIG_WR | 321 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 322 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 323 TRIG_PER | 324 TRIG_PULSE; 325 326 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 327 328 if (!on) { 329 val |= TRIG_DIS; 330 mutex_lock(&clock->extreg_lock); 331 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 332 ext_write(0, phydev, PAGE4, PTP_CTL, val); 333 mutex_unlock(&clock->extreg_lock); 334 return 0; 335 } 336 337 sec = clkreq->perout.start.sec; 338 nsec = clkreq->perout.start.nsec; 339 pwidth = clkreq->perout.period.sec * 1000000000UL; 340 pwidth += clkreq->perout.period.nsec; 341 pwidth /= 2; 342 343 mutex_lock(&clock->extreg_lock); 344 345 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 346 347 /*load trigger*/ 348 val |= TRIG_LOAD; 349 ext_write(0, phydev, PAGE4, PTP_CTL, val); 350 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 352 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 353 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 354 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 356 357 /*enable trigger*/ 358 val &= ~TRIG_LOAD; 359 val |= TRIG_EN; 360 ext_write(0, phydev, PAGE4, PTP_CTL, val); 361 362 mutex_unlock(&clock->extreg_lock); 363 return 0; 364 } 365 366 /* ptp clock methods */ 367 368 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 369 { 370 struct dp83640_clock *clock = 371 container_of(ptp, struct dp83640_clock, caps); 372 struct phy_device *phydev = clock->chosen->phydev; 373 u64 rate; 374 int neg_adj = 0; 375 u16 hi, lo; 376 377 if (ppb < 0) { 378 neg_adj = 1; 379 ppb = -ppb; 380 } 381 rate = ppb; 382 rate <<= 26; 383 rate = div_u64(rate, 1953125); 384 385 hi = (rate >> 16) & PTP_RATE_HI_MASK; 386 if (neg_adj) 387 hi |= PTP_RATE_DIR; 388 389 lo = rate & 0xffff; 390 391 mutex_lock(&clock->extreg_lock); 392 393 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 394 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 395 396 mutex_unlock(&clock->extreg_lock); 397 398 return 0; 399 } 400 401 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 402 { 403 struct dp83640_clock *clock = 404 container_of(ptp, struct dp83640_clock, caps); 405 struct phy_device *phydev = clock->chosen->phydev; 406 struct timespec ts; 407 int err; 408 409 delta += ADJTIME_FIX; 410 411 ts = ns_to_timespec(delta); 412 413 mutex_lock(&clock->extreg_lock); 414 415 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 416 417 mutex_unlock(&clock->extreg_lock); 418 419 return err; 420 } 421 422 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 423 { 424 struct dp83640_clock *clock = 425 container_of(ptp, struct dp83640_clock, caps); 426 struct phy_device *phydev = clock->chosen->phydev; 427 unsigned int val[4]; 428 429 mutex_lock(&clock->extreg_lock); 430 431 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 432 433 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 434 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 435 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 436 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 437 438 mutex_unlock(&clock->extreg_lock); 439 440 ts->tv_nsec = val[0] | (val[1] << 16); 441 ts->tv_sec = val[2] | (val[3] << 16); 442 443 return 0; 444 } 445 446 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 447 const struct timespec *ts) 448 { 449 struct dp83640_clock *clock = 450 container_of(ptp, struct dp83640_clock, caps); 451 struct phy_device *phydev = clock->chosen->phydev; 452 int err; 453 454 mutex_lock(&clock->extreg_lock); 455 456 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 457 458 mutex_unlock(&clock->extreg_lock); 459 460 return err; 461 } 462 463 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 464 struct ptp_clock_request *rq, int on) 465 { 466 struct dp83640_clock *clock = 467 container_of(ptp, struct dp83640_clock, caps); 468 struct phy_device *phydev = clock->chosen->phydev; 469 unsigned int index; 470 u16 evnt, event_num, gpio_num; 471 472 switch (rq->type) { 473 case PTP_CLK_REQ_EXTTS: 474 index = rq->extts.index; 475 if (index >= N_EXT_TS) 476 return -EINVAL; 477 event_num = EXT_EVENT + index; 478 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 479 if (on) { 480 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 481 PTP_PF_EXTTS, index); 482 if (gpio_num < 1) 483 return -EINVAL; 484 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 485 if (rq->extts.flags & PTP_FALLING_EDGE) 486 evnt |= EVNT_FALL; 487 else 488 evnt |= EVNT_RISE; 489 } 490 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 491 return 0; 492 493 case PTP_CLK_REQ_PEROUT: 494 if (rq->perout.index != 0) 495 return -EINVAL; 496 return periodic_output(clock, rq, on); 497 498 default: 499 break; 500 } 501 502 return -EOPNOTSUPP; 503 } 504 505 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 506 enum ptp_pin_function func, unsigned int chan) 507 { 508 return 0; 509 } 510 511 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 512 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 513 514 static void enable_status_frames(struct phy_device *phydev, bool on) 515 { 516 u16 cfg0 = 0, ver; 517 518 if (on) 519 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 520 521 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 522 523 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 524 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 525 526 if (!phydev->attached_dev) { 527 pr_warn("expected to find an attached netdevice\n"); 528 return; 529 } 530 531 if (on) { 532 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 533 pr_warn("failed to add mc address\n"); 534 } else { 535 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 536 pr_warn("failed to delete mc address\n"); 537 } 538 } 539 540 static bool is_status_frame(struct sk_buff *skb, int type) 541 { 542 struct ethhdr *h = eth_hdr(skb); 543 544 if (PTP_CLASS_V2_L2 == type && 545 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 546 return true; 547 else 548 return false; 549 } 550 551 static int expired(struct rxts *rxts) 552 { 553 return time_after(jiffies, rxts->tmo); 554 } 555 556 /* Caller must hold rx_lock. */ 557 static void prune_rx_ts(struct dp83640_private *dp83640) 558 { 559 struct list_head *this, *next; 560 struct rxts *rxts; 561 562 list_for_each_safe(this, next, &dp83640->rxts) { 563 rxts = list_entry(this, struct rxts, list); 564 if (expired(rxts)) { 565 list_del_init(&rxts->list); 566 list_add(&rxts->list, &dp83640->rxpool); 567 } 568 } 569 } 570 571 /* synchronize the phyters so they act as one clock */ 572 573 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 574 { 575 int val; 576 phy_write(phydev, PAGESEL, 0); 577 val = phy_read(phydev, PHYCR2); 578 if (on) 579 val |= BC_WRITE; 580 else 581 val &= ~BC_WRITE; 582 phy_write(phydev, PHYCR2, val); 583 phy_write(phydev, PAGESEL, init_page); 584 } 585 586 static void recalibrate(struct dp83640_clock *clock) 587 { 588 s64 now, diff; 589 struct phy_txts event_ts; 590 struct timespec ts; 591 struct list_head *this; 592 struct dp83640_private *tmp; 593 struct phy_device *master = clock->chosen->phydev; 594 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 595 596 trigger = CAL_TRIGGER; 597 cal_gpio = gpio_tab[CALIBRATE_GPIO]; 598 599 mutex_lock(&clock->extreg_lock); 600 601 /* 602 * enable broadcast, disable status frames, enable ptp clock 603 */ 604 list_for_each(this, &clock->phylist) { 605 tmp = list_entry(this, struct dp83640_private, list); 606 enable_broadcast(tmp->phydev, clock->page, 1); 607 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 608 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 609 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 610 } 611 enable_broadcast(master, clock->page, 1); 612 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 613 ext_write(0, master, PAGE5, PSF_CFG0, 0); 614 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 615 616 /* 617 * enable an event timestamp 618 */ 619 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 620 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 621 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 622 623 list_for_each(this, &clock->phylist) { 624 tmp = list_entry(this, struct dp83640_private, list); 625 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 626 } 627 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 628 629 /* 630 * configure a trigger 631 */ 632 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 633 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 634 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 635 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 636 637 /* load trigger */ 638 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 639 val |= TRIG_LOAD; 640 ext_write(0, master, PAGE4, PTP_CTL, val); 641 642 /* enable trigger */ 643 val &= ~TRIG_LOAD; 644 val |= TRIG_EN; 645 ext_write(0, master, PAGE4, PTP_CTL, val); 646 647 /* disable trigger */ 648 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 649 val |= TRIG_DIS; 650 ext_write(0, master, PAGE4, PTP_CTL, val); 651 652 /* 653 * read out and correct offsets 654 */ 655 val = ext_read(master, PAGE4, PTP_STS); 656 pr_info("master PTP_STS 0x%04hx\n", val); 657 val = ext_read(master, PAGE4, PTP_ESTS); 658 pr_info("master PTP_ESTS 0x%04hx\n", val); 659 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 660 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 661 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 662 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 663 now = phy2txts(&event_ts); 664 665 list_for_each(this, &clock->phylist) { 666 tmp = list_entry(this, struct dp83640_private, list); 667 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 668 pr_info("slave PTP_STS 0x%04hx\n", val); 669 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 670 pr_info("slave PTP_ESTS 0x%04hx\n", val); 671 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 672 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 673 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 674 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 675 diff = now - (s64) phy2txts(&event_ts); 676 pr_info("slave offset %lld nanoseconds\n", diff); 677 diff += ADJTIME_FIX; 678 ts = ns_to_timespec(diff); 679 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 680 } 681 682 /* 683 * restore status frames 684 */ 685 list_for_each(this, &clock->phylist) { 686 tmp = list_entry(this, struct dp83640_private, list); 687 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 688 } 689 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 690 691 mutex_unlock(&clock->extreg_lock); 692 } 693 694 /* time stamping methods */ 695 696 static inline u16 exts_chan_to_edata(int ch) 697 { 698 return 1 << ((ch + EXT_EVENT) * 2); 699 } 700 701 static int decode_evnt(struct dp83640_private *dp83640, 702 void *data, u16 ests) 703 { 704 struct phy_txts *phy_txts; 705 struct ptp_clock_event event; 706 int i, parsed; 707 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 708 u16 ext_status = 0; 709 710 if (ests & MULT_EVNT) { 711 ext_status = *(u16 *) data; 712 data += sizeof(ext_status); 713 } 714 715 phy_txts = data; 716 717 switch (words) { /* fall through in every case */ 718 case 3: 719 dp83640->edata.sec_hi = phy_txts->sec_hi; 720 case 2: 721 dp83640->edata.sec_lo = phy_txts->sec_lo; 722 case 1: 723 dp83640->edata.ns_hi = phy_txts->ns_hi; 724 case 0: 725 dp83640->edata.ns_lo = phy_txts->ns_lo; 726 } 727 728 if (ext_status) { 729 parsed = words + 2; 730 } else { 731 parsed = words + 1; 732 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 733 ext_status = exts_chan_to_edata(i); 734 } 735 736 event.type = PTP_CLOCK_EXTTS; 737 event.timestamp = phy2txts(&dp83640->edata); 738 739 for (i = 0; i < N_EXT_TS; i++) { 740 if (ext_status & exts_chan_to_edata(i)) { 741 event.index = i; 742 ptp_clock_event(dp83640->clock->ptp_clock, &event); 743 } 744 } 745 746 return parsed * sizeof(u16); 747 } 748 749 static void decode_rxts(struct dp83640_private *dp83640, 750 struct phy_rxts *phy_rxts) 751 { 752 struct rxts *rxts; 753 unsigned long flags; 754 755 spin_lock_irqsave(&dp83640->rx_lock, flags); 756 757 prune_rx_ts(dp83640); 758 759 if (list_empty(&dp83640->rxpool)) { 760 pr_debug("rx timestamp pool is empty\n"); 761 goto out; 762 } 763 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 764 list_del_init(&rxts->list); 765 phy2rxts(phy_rxts, rxts); 766 list_add_tail(&rxts->list, &dp83640->rxts); 767 out: 768 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 769 } 770 771 static void decode_txts(struct dp83640_private *dp83640, 772 struct phy_txts *phy_txts) 773 { 774 struct skb_shared_hwtstamps shhwtstamps; 775 struct sk_buff *skb; 776 u64 ns; 777 778 /* We must already have the skb that triggered this. */ 779 780 skb = skb_dequeue(&dp83640->tx_queue); 781 782 if (!skb) { 783 pr_debug("have timestamp but tx_queue empty\n"); 784 return; 785 } 786 ns = phy2txts(phy_txts); 787 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 788 shhwtstamps.hwtstamp = ns_to_ktime(ns); 789 skb_complete_tx_timestamp(skb, &shhwtstamps); 790 } 791 792 static void decode_status_frame(struct dp83640_private *dp83640, 793 struct sk_buff *skb) 794 { 795 struct phy_rxts *phy_rxts; 796 struct phy_txts *phy_txts; 797 u8 *ptr; 798 int len, size; 799 u16 ests, type; 800 801 ptr = skb->data + 2; 802 803 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 804 805 type = *(u16 *)ptr; 806 ests = type & 0x0fff; 807 type = type & 0xf000; 808 len -= sizeof(type); 809 ptr += sizeof(type); 810 811 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 812 813 phy_rxts = (struct phy_rxts *) ptr; 814 decode_rxts(dp83640, phy_rxts); 815 size = sizeof(*phy_rxts); 816 817 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 818 819 phy_txts = (struct phy_txts *) ptr; 820 decode_txts(dp83640, phy_txts); 821 size = sizeof(*phy_txts); 822 823 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) { 824 825 size = decode_evnt(dp83640, ptr, ests); 826 827 } else { 828 size = 0; 829 break; 830 } 831 ptr += size; 832 } 833 } 834 835 static int is_sync(struct sk_buff *skb, int type) 836 { 837 u8 *data = skb->data, *msgtype; 838 unsigned int offset = 0; 839 840 switch (type) { 841 case PTP_CLASS_V1_IPV4: 842 case PTP_CLASS_V2_IPV4: 843 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 844 break; 845 case PTP_CLASS_V1_IPV6: 846 case PTP_CLASS_V2_IPV6: 847 offset = OFF_PTP6; 848 break; 849 case PTP_CLASS_V2_L2: 850 offset = ETH_HLEN; 851 break; 852 case PTP_CLASS_V2_VLAN: 853 offset = ETH_HLEN + VLAN_HLEN; 854 break; 855 default: 856 return 0; 857 } 858 859 if (type & PTP_CLASS_V1) 860 offset += OFF_PTP_CONTROL; 861 862 if (skb->len < offset + 1) 863 return 0; 864 865 msgtype = data + offset; 866 867 return (*msgtype & 0xf) == 0; 868 } 869 870 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 871 { 872 u16 *seqid; 873 unsigned int offset; 874 u8 *msgtype, *data = skb_mac_header(skb); 875 876 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 877 878 switch (type) { 879 case PTP_CLASS_V1_IPV4: 880 case PTP_CLASS_V2_IPV4: 881 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 882 break; 883 case PTP_CLASS_V1_IPV6: 884 case PTP_CLASS_V2_IPV6: 885 offset = OFF_PTP6; 886 break; 887 case PTP_CLASS_V2_L2: 888 offset = ETH_HLEN; 889 break; 890 case PTP_CLASS_V2_VLAN: 891 offset = ETH_HLEN + VLAN_HLEN; 892 break; 893 default: 894 return 0; 895 } 896 897 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) 898 return 0; 899 900 if (unlikely(type & PTP_CLASS_V1)) 901 msgtype = data + offset + OFF_PTP_CONTROL; 902 else 903 msgtype = data + offset; 904 905 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 906 907 return rxts->msgtype == (*msgtype & 0xf) && 908 rxts->seqid == ntohs(*seqid); 909 } 910 911 static void dp83640_free_clocks(void) 912 { 913 struct dp83640_clock *clock; 914 struct list_head *this, *next; 915 916 mutex_lock(&phyter_clocks_lock); 917 918 list_for_each_safe(this, next, &phyter_clocks) { 919 clock = list_entry(this, struct dp83640_clock, list); 920 if (!list_empty(&clock->phylist)) { 921 pr_warn("phy list non-empty while unloading\n"); 922 BUG(); 923 } 924 list_del(&clock->list); 925 mutex_destroy(&clock->extreg_lock); 926 mutex_destroy(&clock->clock_lock); 927 put_device(&clock->bus->dev); 928 kfree(clock->caps.pin_config); 929 kfree(clock); 930 } 931 932 mutex_unlock(&phyter_clocks_lock); 933 } 934 935 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 936 { 937 INIT_LIST_HEAD(&clock->list); 938 clock->bus = bus; 939 mutex_init(&clock->extreg_lock); 940 mutex_init(&clock->clock_lock); 941 INIT_LIST_HEAD(&clock->phylist); 942 clock->caps.owner = THIS_MODULE; 943 sprintf(clock->caps.name, "dp83640 timer"); 944 clock->caps.max_adj = 1953124; 945 clock->caps.n_alarm = 0; 946 clock->caps.n_ext_ts = N_EXT_TS; 947 clock->caps.n_per_out = 1; 948 clock->caps.n_pins = DP83640_N_PINS; 949 clock->caps.pps = 0; 950 clock->caps.adjfreq = ptp_dp83640_adjfreq; 951 clock->caps.adjtime = ptp_dp83640_adjtime; 952 clock->caps.gettime = ptp_dp83640_gettime; 953 clock->caps.settime = ptp_dp83640_settime; 954 clock->caps.enable = ptp_dp83640_enable; 955 clock->caps.verify = ptp_dp83640_verify; 956 /* 957 * Convert the module param defaults into a dynamic pin configuration. 958 */ 959 dp83640_gpio_defaults(clock->caps.pin_config); 960 /* 961 * Get a reference to this bus instance. 962 */ 963 get_device(&bus->dev); 964 } 965 966 static int choose_this_phy(struct dp83640_clock *clock, 967 struct phy_device *phydev) 968 { 969 if (chosen_phy == -1 && !clock->chosen) 970 return 1; 971 972 if (chosen_phy == phydev->addr) 973 return 1; 974 975 return 0; 976 } 977 978 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 979 { 980 if (clock) 981 mutex_lock(&clock->clock_lock); 982 return clock; 983 } 984 985 /* 986 * Look up and lock a clock by bus instance. 987 * If there is no clock for this bus, then create it first. 988 */ 989 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 990 { 991 struct dp83640_clock *clock = NULL, *tmp; 992 struct list_head *this; 993 994 mutex_lock(&phyter_clocks_lock); 995 996 list_for_each(this, &phyter_clocks) { 997 tmp = list_entry(this, struct dp83640_clock, list); 998 if (tmp->bus == bus) { 999 clock = tmp; 1000 break; 1001 } 1002 } 1003 if (clock) 1004 goto out; 1005 1006 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1007 if (!clock) 1008 goto out; 1009 1010 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) * 1011 DP83640_N_PINS, GFP_KERNEL); 1012 if (!clock->caps.pin_config) { 1013 kfree(clock); 1014 clock = NULL; 1015 goto out; 1016 } 1017 dp83640_clock_init(clock, bus); 1018 list_add_tail(&phyter_clocks, &clock->list); 1019 out: 1020 mutex_unlock(&phyter_clocks_lock); 1021 1022 return dp83640_clock_get(clock); 1023 } 1024 1025 static void dp83640_clock_put(struct dp83640_clock *clock) 1026 { 1027 mutex_unlock(&clock->clock_lock); 1028 } 1029 1030 static int dp83640_probe(struct phy_device *phydev) 1031 { 1032 struct dp83640_clock *clock; 1033 struct dp83640_private *dp83640; 1034 int err = -ENOMEM, i; 1035 1036 if (phydev->addr == BROADCAST_ADDR) 1037 return 0; 1038 1039 clock = dp83640_clock_get_bus(phydev->bus); 1040 if (!clock) 1041 goto no_clock; 1042 1043 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1044 if (!dp83640) 1045 goto no_memory; 1046 1047 dp83640->phydev = phydev; 1048 INIT_WORK(&dp83640->ts_work, rx_timestamp_work); 1049 1050 INIT_LIST_HEAD(&dp83640->rxts); 1051 INIT_LIST_HEAD(&dp83640->rxpool); 1052 for (i = 0; i < MAX_RXTS; i++) 1053 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1054 1055 phydev->priv = dp83640; 1056 1057 spin_lock_init(&dp83640->rx_lock); 1058 skb_queue_head_init(&dp83640->rx_queue); 1059 skb_queue_head_init(&dp83640->tx_queue); 1060 1061 dp83640->clock = clock; 1062 1063 if (choose_this_phy(clock, phydev)) { 1064 clock->chosen = dp83640; 1065 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev); 1066 if (IS_ERR(clock->ptp_clock)) { 1067 err = PTR_ERR(clock->ptp_clock); 1068 goto no_register; 1069 } 1070 } else 1071 list_add_tail(&dp83640->list, &clock->phylist); 1072 1073 dp83640_clock_put(clock); 1074 return 0; 1075 1076 no_register: 1077 clock->chosen = NULL; 1078 kfree(dp83640); 1079 no_memory: 1080 dp83640_clock_put(clock); 1081 no_clock: 1082 return err; 1083 } 1084 1085 static void dp83640_remove(struct phy_device *phydev) 1086 { 1087 struct dp83640_clock *clock; 1088 struct list_head *this, *next; 1089 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1090 struct sk_buff *skb; 1091 1092 if (phydev->addr == BROADCAST_ADDR) 1093 return; 1094 1095 enable_status_frames(phydev, false); 1096 cancel_work_sync(&dp83640->ts_work); 1097 1098 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) 1099 kfree_skb(skb); 1100 1101 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL) 1102 skb_complete_tx_timestamp(skb, NULL); 1103 1104 clock = dp83640_clock_get(dp83640->clock); 1105 1106 if (dp83640 == clock->chosen) { 1107 ptp_clock_unregister(clock->ptp_clock); 1108 clock->chosen = NULL; 1109 } else { 1110 list_for_each_safe(this, next, &clock->phylist) { 1111 tmp = list_entry(this, struct dp83640_private, list); 1112 if (tmp == dp83640) { 1113 list_del_init(&tmp->list); 1114 break; 1115 } 1116 } 1117 } 1118 1119 dp83640_clock_put(clock); 1120 kfree(dp83640); 1121 } 1122 1123 static int dp83640_config_init(struct phy_device *phydev) 1124 { 1125 struct dp83640_private *dp83640 = phydev->priv; 1126 struct dp83640_clock *clock = dp83640->clock; 1127 1128 if (clock->chosen && !list_empty(&clock->phylist)) 1129 recalibrate(clock); 1130 else 1131 enable_broadcast(phydev, clock->page, 1); 1132 1133 enable_status_frames(phydev, true); 1134 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1135 return 0; 1136 } 1137 1138 static int dp83640_ack_interrupt(struct phy_device *phydev) 1139 { 1140 int err = phy_read(phydev, MII_DP83640_MISR); 1141 1142 if (err < 0) 1143 return err; 1144 1145 return 0; 1146 } 1147 1148 static int dp83640_config_intr(struct phy_device *phydev) 1149 { 1150 int micr; 1151 int misr; 1152 int err; 1153 1154 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1155 misr = phy_read(phydev, MII_DP83640_MISR); 1156 if (misr < 0) 1157 return misr; 1158 misr |= 1159 (MII_DP83640_MISR_ANC_INT_EN | 1160 MII_DP83640_MISR_DUP_INT_EN | 1161 MII_DP83640_MISR_SPD_INT_EN | 1162 MII_DP83640_MISR_LINK_INT_EN); 1163 err = phy_write(phydev, MII_DP83640_MISR, misr); 1164 if (err < 0) 1165 return err; 1166 1167 micr = phy_read(phydev, MII_DP83640_MICR); 1168 if (micr < 0) 1169 return micr; 1170 micr |= 1171 (MII_DP83640_MICR_OE | 1172 MII_DP83640_MICR_IE); 1173 return phy_write(phydev, MII_DP83640_MICR, micr); 1174 } else { 1175 micr = phy_read(phydev, MII_DP83640_MICR); 1176 if (micr < 0) 1177 return micr; 1178 micr &= 1179 ~(MII_DP83640_MICR_OE | 1180 MII_DP83640_MICR_IE); 1181 err = phy_write(phydev, MII_DP83640_MICR, micr); 1182 if (err < 0) 1183 return err; 1184 1185 misr = phy_read(phydev, MII_DP83640_MISR); 1186 if (misr < 0) 1187 return misr; 1188 misr &= 1189 ~(MII_DP83640_MISR_ANC_INT_EN | 1190 MII_DP83640_MISR_DUP_INT_EN | 1191 MII_DP83640_MISR_SPD_INT_EN | 1192 MII_DP83640_MISR_LINK_INT_EN); 1193 return phy_write(phydev, MII_DP83640_MISR, misr); 1194 } 1195 } 1196 1197 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) 1198 { 1199 struct dp83640_private *dp83640 = phydev->priv; 1200 struct hwtstamp_config cfg; 1201 u16 txcfg0, rxcfg0; 1202 1203 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1204 return -EFAULT; 1205 1206 if (cfg.flags) /* reserved for future extensions */ 1207 return -EINVAL; 1208 1209 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1210 return -ERANGE; 1211 1212 dp83640->hwts_tx_en = cfg.tx_type; 1213 1214 switch (cfg.rx_filter) { 1215 case HWTSTAMP_FILTER_NONE: 1216 dp83640->hwts_rx_en = 0; 1217 dp83640->layer = 0; 1218 dp83640->version = 0; 1219 break; 1220 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1221 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1222 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1223 dp83640->hwts_rx_en = 1; 1224 dp83640->layer = LAYER4; 1225 dp83640->version = 1; 1226 break; 1227 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1228 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1229 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1230 dp83640->hwts_rx_en = 1; 1231 dp83640->layer = LAYER4; 1232 dp83640->version = 2; 1233 break; 1234 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1235 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1236 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1237 dp83640->hwts_rx_en = 1; 1238 dp83640->layer = LAYER2; 1239 dp83640->version = 2; 1240 break; 1241 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1242 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1243 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1244 dp83640->hwts_rx_en = 1; 1245 dp83640->layer = LAYER4|LAYER2; 1246 dp83640->version = 2; 1247 break; 1248 default: 1249 return -ERANGE; 1250 } 1251 1252 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1253 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1254 1255 if (dp83640->layer & LAYER2) { 1256 txcfg0 |= TX_L2_EN; 1257 rxcfg0 |= RX_L2_EN; 1258 } 1259 if (dp83640->layer & LAYER4) { 1260 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1261 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1262 } 1263 1264 if (dp83640->hwts_tx_en) 1265 txcfg0 |= TX_TS_EN; 1266 1267 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1268 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1269 1270 if (dp83640->hwts_rx_en) 1271 rxcfg0 |= RX_TS_EN; 1272 1273 mutex_lock(&dp83640->clock->extreg_lock); 1274 1275 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); 1276 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1277 1278 mutex_unlock(&dp83640->clock->extreg_lock); 1279 1280 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1281 } 1282 1283 static void rx_timestamp_work(struct work_struct *work) 1284 { 1285 struct dp83640_private *dp83640 = 1286 container_of(work, struct dp83640_private, ts_work); 1287 struct list_head *this, *next; 1288 struct rxts *rxts; 1289 struct skb_shared_hwtstamps *shhwtstamps; 1290 struct sk_buff *skb; 1291 unsigned int type; 1292 unsigned long flags; 1293 1294 /* Deliver each deferred packet, with or without a time stamp. */ 1295 1296 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) { 1297 type = SKB_PTP_TYPE(skb); 1298 spin_lock_irqsave(&dp83640->rx_lock, flags); 1299 list_for_each_safe(this, next, &dp83640->rxts) { 1300 rxts = list_entry(this, struct rxts, list); 1301 if (match(skb, type, rxts)) { 1302 shhwtstamps = skb_hwtstamps(skb); 1303 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1304 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1305 list_del_init(&rxts->list); 1306 list_add(&rxts->list, &dp83640->rxpool); 1307 break; 1308 } 1309 } 1310 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1311 netif_rx_ni(skb); 1312 } 1313 1314 /* Clear out expired time stamps. */ 1315 1316 spin_lock_irqsave(&dp83640->rx_lock, flags); 1317 prune_rx_ts(dp83640); 1318 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1319 } 1320 1321 static bool dp83640_rxtstamp(struct phy_device *phydev, 1322 struct sk_buff *skb, int type) 1323 { 1324 struct dp83640_private *dp83640 = phydev->priv; 1325 1326 if (!dp83640->hwts_rx_en) 1327 return false; 1328 1329 if (is_status_frame(skb, type)) { 1330 decode_status_frame(dp83640, skb); 1331 kfree_skb(skb); 1332 return true; 1333 } 1334 1335 SKB_PTP_TYPE(skb) = type; 1336 skb_queue_tail(&dp83640->rx_queue, skb); 1337 schedule_work(&dp83640->ts_work); 1338 1339 return true; 1340 } 1341 1342 static void dp83640_txtstamp(struct phy_device *phydev, 1343 struct sk_buff *skb, int type) 1344 { 1345 struct dp83640_private *dp83640 = phydev->priv; 1346 1347 switch (dp83640->hwts_tx_en) { 1348 1349 case HWTSTAMP_TX_ONESTEP_SYNC: 1350 if (is_sync(skb, type)) { 1351 skb_complete_tx_timestamp(skb, NULL); 1352 return; 1353 } 1354 /* fall through */ 1355 case HWTSTAMP_TX_ON: 1356 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1357 skb_queue_tail(&dp83640->tx_queue, skb); 1358 schedule_work(&dp83640->ts_work); 1359 break; 1360 1361 case HWTSTAMP_TX_OFF: 1362 default: 1363 skb_complete_tx_timestamp(skb, NULL); 1364 break; 1365 } 1366 } 1367 1368 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) 1369 { 1370 struct dp83640_private *dp83640 = dev->priv; 1371 1372 info->so_timestamping = 1373 SOF_TIMESTAMPING_TX_HARDWARE | 1374 SOF_TIMESTAMPING_RX_HARDWARE | 1375 SOF_TIMESTAMPING_RAW_HARDWARE; 1376 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1377 info->tx_types = 1378 (1 << HWTSTAMP_TX_OFF) | 1379 (1 << HWTSTAMP_TX_ON) | 1380 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1381 info->rx_filters = 1382 (1 << HWTSTAMP_FILTER_NONE) | 1383 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1384 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1385 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1386 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1387 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1388 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1389 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1390 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 1391 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 1392 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1393 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1394 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1395 return 0; 1396 } 1397 1398 static struct phy_driver dp83640_driver = { 1399 .phy_id = DP83640_PHY_ID, 1400 .phy_id_mask = 0xfffffff0, 1401 .name = "NatSemi DP83640", 1402 .features = PHY_BASIC_FEATURES, 1403 .flags = PHY_HAS_INTERRUPT, 1404 .probe = dp83640_probe, 1405 .remove = dp83640_remove, 1406 .config_init = dp83640_config_init, 1407 .config_aneg = genphy_config_aneg, 1408 .read_status = genphy_read_status, 1409 .ack_interrupt = dp83640_ack_interrupt, 1410 .config_intr = dp83640_config_intr, 1411 .ts_info = dp83640_ts_info, 1412 .hwtstamp = dp83640_hwtstamp, 1413 .rxtstamp = dp83640_rxtstamp, 1414 .txtstamp = dp83640_txtstamp, 1415 .driver = {.owner = THIS_MODULE,} 1416 }; 1417 1418 static int __init dp83640_init(void) 1419 { 1420 return phy_driver_register(&dp83640_driver); 1421 } 1422 1423 static void __exit dp83640_exit(void) 1424 { 1425 dp83640_free_clocks(); 1426 phy_driver_unregister(&dp83640_driver); 1427 } 1428 1429 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1430 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1431 MODULE_LICENSE("GPL"); 1432 1433 module_init(dp83640_init); 1434 module_exit(dp83640_exit); 1435 1436 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1437 { DP83640_PHY_ID, 0xfffffff0 }, 1438 { } 1439 }; 1440 1441 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1442