1 /* 2 * Driver for the National Semiconductor DP83640 PHYTER 3 * 4 * Copyright (C) 2010 OMICRON electronics GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/ethtool.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/mii.h> 27 #include <linux/module.h> 28 #include <linux/net_tstamp.h> 29 #include <linux/netdevice.h> 30 #include <linux/if_vlan.h> 31 #include <linux/phy.h> 32 #include <linux/ptp_classify.h> 33 #include <linux/ptp_clock_kernel.h> 34 35 #include "dp83640_reg.h" 36 37 #define DP83640_PHY_ID 0x20005ce1 38 #define PAGESEL 0x13 39 #define LAYER4 0x02 40 #define LAYER2 0x01 41 #define MAX_RXTS 64 42 #define N_EXT_TS 6 43 #define N_PER_OUT 7 44 #define PSF_PTPVER 2 45 #define PSF_EVNT 0x4000 46 #define PSF_RX 0x2000 47 #define PSF_TX 0x1000 48 #define EXT_EVENT 1 49 #define CAL_EVENT 7 50 #define CAL_TRIGGER 7 51 #define DP83640_N_PINS 12 52 53 #define MII_DP83640_MICR 0x11 54 #define MII_DP83640_MISR 0x12 55 56 #define MII_DP83640_MICR_OE 0x1 57 #define MII_DP83640_MICR_IE 0x2 58 59 #define MII_DP83640_MISR_RHF_INT_EN 0x01 60 #define MII_DP83640_MISR_FHF_INT_EN 0x02 61 #define MII_DP83640_MISR_ANC_INT_EN 0x04 62 #define MII_DP83640_MISR_DUP_INT_EN 0x08 63 #define MII_DP83640_MISR_SPD_INT_EN 0x10 64 #define MII_DP83640_MISR_LINK_INT_EN 0x20 65 #define MII_DP83640_MISR_ED_INT_EN 0x40 66 #define MII_DP83640_MISR_LQ_INT_EN 0x80 67 68 /* phyter seems to miss the mark by 16 ns */ 69 #define ADJTIME_FIX 16 70 71 #if defined(__BIG_ENDIAN) 72 #define ENDIAN_FLAG 0 73 #elif defined(__LITTLE_ENDIAN) 74 #define ENDIAN_FLAG PSF_ENDIAN 75 #endif 76 77 struct dp83640_skb_info { 78 int ptp_type; 79 unsigned long tmo; 80 }; 81 82 struct phy_rxts { 83 u16 ns_lo; /* ns[15:0] */ 84 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 85 u16 sec_lo; /* sec[15:0] */ 86 u16 sec_hi; /* sec[31:16] */ 87 u16 seqid; /* sequenceId[15:0] */ 88 u16 msgtype; /* messageType[3:0], hash[11:0] */ 89 }; 90 91 struct phy_txts { 92 u16 ns_lo; /* ns[15:0] */ 93 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 94 u16 sec_lo; /* sec[15:0] */ 95 u16 sec_hi; /* sec[31:16] */ 96 }; 97 98 struct rxts { 99 struct list_head list; 100 unsigned long tmo; 101 u64 ns; 102 u16 seqid; 103 u8 msgtype; 104 u16 hash; 105 }; 106 107 struct dp83640_clock; 108 109 struct dp83640_private { 110 struct list_head list; 111 struct dp83640_clock *clock; 112 struct phy_device *phydev; 113 struct work_struct ts_work; 114 int hwts_tx_en; 115 int hwts_rx_en; 116 int layer; 117 int version; 118 /* remember state of cfg0 during calibration */ 119 int cfg0; 120 /* remember the last event time stamp */ 121 struct phy_txts edata; 122 /* list of rx timestamps */ 123 struct list_head rxts; 124 struct list_head rxpool; 125 struct rxts rx_pool_data[MAX_RXTS]; 126 /* protects above three fields from concurrent access */ 127 spinlock_t rx_lock; 128 /* queues of incoming and outgoing packets */ 129 struct sk_buff_head rx_queue; 130 struct sk_buff_head tx_queue; 131 }; 132 133 struct dp83640_clock { 134 /* keeps the instance in the 'phyter_clocks' list */ 135 struct list_head list; 136 /* we create one clock instance per MII bus */ 137 struct mii_bus *bus; 138 /* protects extended registers from concurrent access */ 139 struct mutex extreg_lock; 140 /* remembers which page was last selected */ 141 int page; 142 /* our advertised capabilities */ 143 struct ptp_clock_info caps; 144 /* protects the three fields below from concurrent access */ 145 struct mutex clock_lock; 146 /* the one phyter from which we shall read */ 147 struct dp83640_private *chosen; 148 /* list of the other attached phyters, not chosen */ 149 struct list_head phylist; 150 /* reference to our PTP hardware clock */ 151 struct ptp_clock *ptp_clock; 152 }; 153 154 /* globals */ 155 156 enum { 157 CALIBRATE_GPIO, 158 PEROUT_GPIO, 159 EXTTS0_GPIO, 160 EXTTS1_GPIO, 161 EXTTS2_GPIO, 162 EXTTS3_GPIO, 163 EXTTS4_GPIO, 164 EXTTS5_GPIO, 165 GPIO_TABLE_SIZE 166 }; 167 168 static int chosen_phy = -1; 169 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 170 1, 2, 3, 4, 8, 9, 10, 11 171 }; 172 173 module_param(chosen_phy, int, 0444); 174 module_param_array(gpio_tab, ushort, NULL, 0444); 175 176 MODULE_PARM_DESC(chosen_phy, \ 177 "The address of the PHY to use for the ancillary clock features"); 178 MODULE_PARM_DESC(gpio_tab, \ 179 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 180 181 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 182 { 183 int i, index; 184 185 for (i = 0; i < DP83640_N_PINS; i++) { 186 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 187 pd[i].index = i; 188 } 189 190 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 191 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 192 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 193 return; 194 } 195 } 196 197 index = gpio_tab[CALIBRATE_GPIO] - 1; 198 pd[index].func = PTP_PF_PHYSYNC; 199 pd[index].chan = 0; 200 201 index = gpio_tab[PEROUT_GPIO] - 1; 202 pd[index].func = PTP_PF_PEROUT; 203 pd[index].chan = 0; 204 205 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 206 index = gpio_tab[i] - 1; 207 pd[index].func = PTP_PF_EXTTS; 208 pd[index].chan = i - EXTTS0_GPIO; 209 } 210 } 211 212 /* a list of clocks and a mutex to protect it */ 213 static LIST_HEAD(phyter_clocks); 214 static DEFINE_MUTEX(phyter_clocks_lock); 215 216 static void rx_timestamp_work(struct work_struct *work); 217 218 /* extended register access functions */ 219 220 #define BROADCAST_ADDR 31 221 222 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val) 223 { 224 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val); 225 } 226 227 /* Caller must hold extreg_lock. */ 228 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 229 { 230 struct dp83640_private *dp83640 = phydev->priv; 231 int val; 232 233 if (dp83640->clock->page != page) { 234 broadcast_write(phydev->bus, PAGESEL, page); 235 dp83640->clock->page = page; 236 } 237 val = phy_read(phydev, regnum); 238 239 return val; 240 } 241 242 /* Caller must hold extreg_lock. */ 243 static void ext_write(int broadcast, struct phy_device *phydev, 244 int page, u32 regnum, u16 val) 245 { 246 struct dp83640_private *dp83640 = phydev->priv; 247 248 if (dp83640->clock->page != page) { 249 broadcast_write(phydev->bus, PAGESEL, page); 250 dp83640->clock->page = page; 251 } 252 if (broadcast) 253 broadcast_write(phydev->bus, regnum, val); 254 else 255 phy_write(phydev, regnum, val); 256 } 257 258 /* Caller must hold extreg_lock. */ 259 static int tdr_write(int bc, struct phy_device *dev, 260 const struct timespec *ts, u16 cmd) 261 { 262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 264 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 266 267 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 268 269 return 0; 270 } 271 272 /* convert phy timestamps into driver timestamps */ 273 274 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 275 { 276 u32 sec; 277 278 sec = p->sec_lo; 279 sec |= p->sec_hi << 16; 280 281 rxts->ns = p->ns_lo; 282 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 283 rxts->ns += ((u64)sec) * 1000000000ULL; 284 rxts->seqid = p->seqid; 285 rxts->msgtype = (p->msgtype >> 12) & 0xf; 286 rxts->hash = p->msgtype & 0x0fff; 287 rxts->tmo = jiffies + 2; 288 } 289 290 static u64 phy2txts(struct phy_txts *p) 291 { 292 u64 ns; 293 u32 sec; 294 295 sec = p->sec_lo; 296 sec |= p->sec_hi << 16; 297 298 ns = p->ns_lo; 299 ns |= (p->ns_hi & 0x3fff) << 16; 300 ns += ((u64)sec) * 1000000000ULL; 301 302 return ns; 303 } 304 305 static int periodic_output(struct dp83640_clock *clock, 306 struct ptp_clock_request *clkreq, bool on, 307 int trigger) 308 { 309 struct dp83640_private *dp83640 = clock->chosen; 310 struct phy_device *phydev = dp83640->phydev; 311 u32 sec, nsec, pwidth; 312 u16 gpio, ptp_trig, val; 313 314 if (on) { 315 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 316 trigger); 317 if (gpio < 1) 318 return -EINVAL; 319 } else { 320 gpio = 0; 321 } 322 323 ptp_trig = TRIG_WR | 324 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 325 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 326 TRIG_PER | 327 TRIG_PULSE; 328 329 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 330 331 if (!on) { 332 val |= TRIG_DIS; 333 mutex_lock(&clock->extreg_lock); 334 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 335 ext_write(0, phydev, PAGE4, PTP_CTL, val); 336 mutex_unlock(&clock->extreg_lock); 337 return 0; 338 } 339 340 sec = clkreq->perout.start.sec; 341 nsec = clkreq->perout.start.nsec; 342 pwidth = clkreq->perout.period.sec * 1000000000UL; 343 pwidth += clkreq->perout.period.nsec; 344 pwidth /= 2; 345 346 mutex_lock(&clock->extreg_lock); 347 348 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 349 350 /*load trigger*/ 351 val |= TRIG_LOAD; 352 ext_write(0, phydev, PAGE4, PTP_CTL, val); 353 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 354 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 355 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 356 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 357 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 358 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 359 /* Triggers 0 and 1 has programmable pulsewidth2 */ 360 if (trigger < 2) { 361 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 362 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 363 } 364 365 /*enable trigger*/ 366 val &= ~TRIG_LOAD; 367 val |= TRIG_EN; 368 ext_write(0, phydev, PAGE4, PTP_CTL, val); 369 370 mutex_unlock(&clock->extreg_lock); 371 return 0; 372 } 373 374 /* ptp clock methods */ 375 376 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 377 { 378 struct dp83640_clock *clock = 379 container_of(ptp, struct dp83640_clock, caps); 380 struct phy_device *phydev = clock->chosen->phydev; 381 u64 rate; 382 int neg_adj = 0; 383 u16 hi, lo; 384 385 if (ppb < 0) { 386 neg_adj = 1; 387 ppb = -ppb; 388 } 389 rate = ppb; 390 rate <<= 26; 391 rate = div_u64(rate, 1953125); 392 393 hi = (rate >> 16) & PTP_RATE_HI_MASK; 394 if (neg_adj) 395 hi |= PTP_RATE_DIR; 396 397 lo = rate & 0xffff; 398 399 mutex_lock(&clock->extreg_lock); 400 401 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 402 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 403 404 mutex_unlock(&clock->extreg_lock); 405 406 return 0; 407 } 408 409 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 410 { 411 struct dp83640_clock *clock = 412 container_of(ptp, struct dp83640_clock, caps); 413 struct phy_device *phydev = clock->chosen->phydev; 414 struct timespec ts; 415 int err; 416 417 delta += ADJTIME_FIX; 418 419 ts = ns_to_timespec(delta); 420 421 mutex_lock(&clock->extreg_lock); 422 423 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 424 425 mutex_unlock(&clock->extreg_lock); 426 427 return err; 428 } 429 430 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 431 { 432 struct dp83640_clock *clock = 433 container_of(ptp, struct dp83640_clock, caps); 434 struct phy_device *phydev = clock->chosen->phydev; 435 unsigned int val[4]; 436 437 mutex_lock(&clock->extreg_lock); 438 439 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 440 441 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 442 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 443 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 444 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 445 446 mutex_unlock(&clock->extreg_lock); 447 448 ts->tv_nsec = val[0] | (val[1] << 16); 449 ts->tv_sec = val[2] | (val[3] << 16); 450 451 return 0; 452 } 453 454 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 455 const struct timespec *ts) 456 { 457 struct dp83640_clock *clock = 458 container_of(ptp, struct dp83640_clock, caps); 459 struct phy_device *phydev = clock->chosen->phydev; 460 int err; 461 462 mutex_lock(&clock->extreg_lock); 463 464 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 465 466 mutex_unlock(&clock->extreg_lock); 467 468 return err; 469 } 470 471 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 472 struct ptp_clock_request *rq, int on) 473 { 474 struct dp83640_clock *clock = 475 container_of(ptp, struct dp83640_clock, caps); 476 struct phy_device *phydev = clock->chosen->phydev; 477 unsigned int index; 478 u16 evnt, event_num, gpio_num; 479 480 switch (rq->type) { 481 case PTP_CLK_REQ_EXTTS: 482 index = rq->extts.index; 483 if (index >= N_EXT_TS) 484 return -EINVAL; 485 event_num = EXT_EVENT + index; 486 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 487 if (on) { 488 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 489 PTP_PF_EXTTS, index); 490 if (gpio_num < 1) 491 return -EINVAL; 492 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 493 if (rq->extts.flags & PTP_FALLING_EDGE) 494 evnt |= EVNT_FALL; 495 else 496 evnt |= EVNT_RISE; 497 } 498 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 499 return 0; 500 501 case PTP_CLK_REQ_PEROUT: 502 if (rq->perout.index >= N_PER_OUT) 503 return -EINVAL; 504 return periodic_output(clock, rq, on, rq->perout.index); 505 506 default: 507 break; 508 } 509 510 return -EOPNOTSUPP; 511 } 512 513 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 514 enum ptp_pin_function func, unsigned int chan) 515 { 516 struct dp83640_clock *clock = 517 container_of(ptp, struct dp83640_clock, caps); 518 519 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 520 !list_empty(&clock->phylist)) 521 return 1; 522 523 if (func == PTP_PF_PHYSYNC) 524 return 1; 525 526 return 0; 527 } 528 529 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 530 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 531 532 static void enable_status_frames(struct phy_device *phydev, bool on) 533 { 534 u16 cfg0 = 0, ver; 535 536 if (on) 537 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 538 539 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 540 541 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 542 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 543 544 if (!phydev->attached_dev) { 545 pr_warn("expected to find an attached netdevice\n"); 546 return; 547 } 548 549 if (on) { 550 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 551 pr_warn("failed to add mc address\n"); 552 } else { 553 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 554 pr_warn("failed to delete mc address\n"); 555 } 556 } 557 558 static bool is_status_frame(struct sk_buff *skb, int type) 559 { 560 struct ethhdr *h = eth_hdr(skb); 561 562 if (PTP_CLASS_V2_L2 == type && 563 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 564 return true; 565 else 566 return false; 567 } 568 569 static int expired(struct rxts *rxts) 570 { 571 return time_after(jiffies, rxts->tmo); 572 } 573 574 /* Caller must hold rx_lock. */ 575 static void prune_rx_ts(struct dp83640_private *dp83640) 576 { 577 struct list_head *this, *next; 578 struct rxts *rxts; 579 580 list_for_each_safe(this, next, &dp83640->rxts) { 581 rxts = list_entry(this, struct rxts, list); 582 if (expired(rxts)) { 583 list_del_init(&rxts->list); 584 list_add(&rxts->list, &dp83640->rxpool); 585 } 586 } 587 } 588 589 /* synchronize the phyters so they act as one clock */ 590 591 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 592 { 593 int val; 594 phy_write(phydev, PAGESEL, 0); 595 val = phy_read(phydev, PHYCR2); 596 if (on) 597 val |= BC_WRITE; 598 else 599 val &= ~BC_WRITE; 600 phy_write(phydev, PHYCR2, val); 601 phy_write(phydev, PAGESEL, init_page); 602 } 603 604 static void recalibrate(struct dp83640_clock *clock) 605 { 606 s64 now, diff; 607 struct phy_txts event_ts; 608 struct timespec ts; 609 struct list_head *this; 610 struct dp83640_private *tmp; 611 struct phy_device *master = clock->chosen->phydev; 612 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 613 614 trigger = CAL_TRIGGER; 615 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 616 if (cal_gpio < 1) { 617 pr_err("PHY calibration pin not avaible - PHY is not calibrated."); 618 return; 619 } 620 621 mutex_lock(&clock->extreg_lock); 622 623 /* 624 * enable broadcast, disable status frames, enable ptp clock 625 */ 626 list_for_each(this, &clock->phylist) { 627 tmp = list_entry(this, struct dp83640_private, list); 628 enable_broadcast(tmp->phydev, clock->page, 1); 629 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 630 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 631 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 632 } 633 enable_broadcast(master, clock->page, 1); 634 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 635 ext_write(0, master, PAGE5, PSF_CFG0, 0); 636 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 637 638 /* 639 * enable an event timestamp 640 */ 641 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 642 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 643 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 644 645 list_for_each(this, &clock->phylist) { 646 tmp = list_entry(this, struct dp83640_private, list); 647 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 648 } 649 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 650 651 /* 652 * configure a trigger 653 */ 654 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 655 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 656 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 657 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 658 659 /* load trigger */ 660 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 661 val |= TRIG_LOAD; 662 ext_write(0, master, PAGE4, PTP_CTL, val); 663 664 /* enable trigger */ 665 val &= ~TRIG_LOAD; 666 val |= TRIG_EN; 667 ext_write(0, master, PAGE4, PTP_CTL, val); 668 669 /* disable trigger */ 670 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 671 val |= TRIG_DIS; 672 ext_write(0, master, PAGE4, PTP_CTL, val); 673 674 /* 675 * read out and correct offsets 676 */ 677 val = ext_read(master, PAGE4, PTP_STS); 678 pr_info("master PTP_STS 0x%04hx\n", val); 679 val = ext_read(master, PAGE4, PTP_ESTS); 680 pr_info("master PTP_ESTS 0x%04hx\n", val); 681 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 682 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 683 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 684 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 685 now = phy2txts(&event_ts); 686 687 list_for_each(this, &clock->phylist) { 688 tmp = list_entry(this, struct dp83640_private, list); 689 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 690 pr_info("slave PTP_STS 0x%04hx\n", val); 691 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 692 pr_info("slave PTP_ESTS 0x%04hx\n", val); 693 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 694 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 695 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 696 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 697 diff = now - (s64) phy2txts(&event_ts); 698 pr_info("slave offset %lld nanoseconds\n", diff); 699 diff += ADJTIME_FIX; 700 ts = ns_to_timespec(diff); 701 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 702 } 703 704 /* 705 * restore status frames 706 */ 707 list_for_each(this, &clock->phylist) { 708 tmp = list_entry(this, struct dp83640_private, list); 709 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 710 } 711 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 712 713 mutex_unlock(&clock->extreg_lock); 714 } 715 716 /* time stamping methods */ 717 718 static inline u16 exts_chan_to_edata(int ch) 719 { 720 return 1 << ((ch + EXT_EVENT) * 2); 721 } 722 723 static int decode_evnt(struct dp83640_private *dp83640, 724 void *data, u16 ests) 725 { 726 struct phy_txts *phy_txts; 727 struct ptp_clock_event event; 728 int i, parsed; 729 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 730 u16 ext_status = 0; 731 732 if (ests & MULT_EVNT) { 733 ext_status = *(u16 *) data; 734 data += sizeof(ext_status); 735 } 736 737 phy_txts = data; 738 739 switch (words) { /* fall through in every case */ 740 case 3: 741 dp83640->edata.sec_hi = phy_txts->sec_hi; 742 case 2: 743 dp83640->edata.sec_lo = phy_txts->sec_lo; 744 case 1: 745 dp83640->edata.ns_hi = phy_txts->ns_hi; 746 case 0: 747 dp83640->edata.ns_lo = phy_txts->ns_lo; 748 } 749 750 if (ext_status) { 751 parsed = words + 2; 752 } else { 753 parsed = words + 1; 754 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 755 ext_status = exts_chan_to_edata(i); 756 } 757 758 event.type = PTP_CLOCK_EXTTS; 759 event.timestamp = phy2txts(&dp83640->edata); 760 761 /* Compensate for input path and synchronization delays */ 762 event.timestamp -= 35; 763 764 for (i = 0; i < N_EXT_TS; i++) { 765 if (ext_status & exts_chan_to_edata(i)) { 766 event.index = i; 767 ptp_clock_event(dp83640->clock->ptp_clock, &event); 768 } 769 } 770 771 return parsed * sizeof(u16); 772 } 773 774 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 775 { 776 u16 *seqid; 777 unsigned int offset = 0; 778 u8 *msgtype, *data = skb_mac_header(skb); 779 780 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 781 782 if (type & PTP_CLASS_VLAN) 783 offset += VLAN_HLEN; 784 785 switch (type & PTP_CLASS_PMASK) { 786 case PTP_CLASS_IPV4: 787 offset += ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 788 break; 789 case PTP_CLASS_IPV6: 790 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; 791 break; 792 case PTP_CLASS_L2: 793 offset += ETH_HLEN; 794 break; 795 default: 796 return 0; 797 } 798 799 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) 800 return 0; 801 802 if (unlikely(type & PTP_CLASS_V1)) 803 msgtype = data + offset + OFF_PTP_CONTROL; 804 else 805 msgtype = data + offset; 806 807 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 808 809 return rxts->msgtype == (*msgtype & 0xf) && 810 rxts->seqid == ntohs(*seqid); 811 } 812 813 static void decode_rxts(struct dp83640_private *dp83640, 814 struct phy_rxts *phy_rxts) 815 { 816 struct rxts *rxts; 817 struct skb_shared_hwtstamps *shhwtstamps = NULL; 818 struct sk_buff *skb; 819 unsigned long flags; 820 821 spin_lock_irqsave(&dp83640->rx_lock, flags); 822 823 prune_rx_ts(dp83640); 824 825 if (list_empty(&dp83640->rxpool)) { 826 pr_debug("rx timestamp pool is empty\n"); 827 goto out; 828 } 829 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 830 list_del_init(&rxts->list); 831 phy2rxts(phy_rxts, rxts); 832 833 spin_lock_irqsave(&dp83640->rx_queue.lock, flags); 834 skb_queue_walk(&dp83640->rx_queue, skb) { 835 struct dp83640_skb_info *skb_info; 836 837 skb_info = (struct dp83640_skb_info *)skb->cb; 838 if (match(skb, skb_info->ptp_type, rxts)) { 839 __skb_unlink(skb, &dp83640->rx_queue); 840 shhwtstamps = skb_hwtstamps(skb); 841 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 842 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 843 netif_rx_ni(skb); 844 list_add(&rxts->list, &dp83640->rxpool); 845 break; 846 } 847 } 848 spin_unlock_irqrestore(&dp83640->rx_queue.lock, flags); 849 850 if (!shhwtstamps) 851 list_add_tail(&rxts->list, &dp83640->rxts); 852 out: 853 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 854 } 855 856 static void decode_txts(struct dp83640_private *dp83640, 857 struct phy_txts *phy_txts) 858 { 859 struct skb_shared_hwtstamps shhwtstamps; 860 struct sk_buff *skb; 861 u64 ns; 862 863 /* We must already have the skb that triggered this. */ 864 865 skb = skb_dequeue(&dp83640->tx_queue); 866 867 if (!skb) { 868 pr_debug("have timestamp but tx_queue empty\n"); 869 return; 870 } 871 ns = phy2txts(phy_txts); 872 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 873 shhwtstamps.hwtstamp = ns_to_ktime(ns); 874 skb_complete_tx_timestamp(skb, &shhwtstamps); 875 } 876 877 static void decode_status_frame(struct dp83640_private *dp83640, 878 struct sk_buff *skb) 879 { 880 struct phy_rxts *phy_rxts; 881 struct phy_txts *phy_txts; 882 u8 *ptr; 883 int len, size; 884 u16 ests, type; 885 886 ptr = skb->data + 2; 887 888 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 889 890 type = *(u16 *)ptr; 891 ests = type & 0x0fff; 892 type = type & 0xf000; 893 len -= sizeof(type); 894 ptr += sizeof(type); 895 896 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 897 898 phy_rxts = (struct phy_rxts *) ptr; 899 decode_rxts(dp83640, phy_rxts); 900 size = sizeof(*phy_rxts); 901 902 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 903 904 phy_txts = (struct phy_txts *) ptr; 905 decode_txts(dp83640, phy_txts); 906 size = sizeof(*phy_txts); 907 908 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) { 909 910 size = decode_evnt(dp83640, ptr, ests); 911 912 } else { 913 size = 0; 914 break; 915 } 916 ptr += size; 917 } 918 } 919 920 static int is_sync(struct sk_buff *skb, int type) 921 { 922 u8 *data = skb->data, *msgtype; 923 unsigned int offset = 0; 924 925 if (type & PTP_CLASS_VLAN) 926 offset += VLAN_HLEN; 927 928 switch (type & PTP_CLASS_PMASK) { 929 case PTP_CLASS_IPV4: 930 offset += ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 931 break; 932 case PTP_CLASS_IPV6: 933 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; 934 break; 935 case PTP_CLASS_L2: 936 offset += ETH_HLEN; 937 break; 938 default: 939 return 0; 940 } 941 942 if (type & PTP_CLASS_V1) 943 offset += OFF_PTP_CONTROL; 944 945 if (skb->len < offset + 1) 946 return 0; 947 948 msgtype = data + offset; 949 950 return (*msgtype & 0xf) == 0; 951 } 952 953 static void dp83640_free_clocks(void) 954 { 955 struct dp83640_clock *clock; 956 struct list_head *this, *next; 957 958 mutex_lock(&phyter_clocks_lock); 959 960 list_for_each_safe(this, next, &phyter_clocks) { 961 clock = list_entry(this, struct dp83640_clock, list); 962 if (!list_empty(&clock->phylist)) { 963 pr_warn("phy list non-empty while unloading\n"); 964 BUG(); 965 } 966 list_del(&clock->list); 967 mutex_destroy(&clock->extreg_lock); 968 mutex_destroy(&clock->clock_lock); 969 put_device(&clock->bus->dev); 970 kfree(clock->caps.pin_config); 971 kfree(clock); 972 } 973 974 mutex_unlock(&phyter_clocks_lock); 975 } 976 977 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 978 { 979 INIT_LIST_HEAD(&clock->list); 980 clock->bus = bus; 981 mutex_init(&clock->extreg_lock); 982 mutex_init(&clock->clock_lock); 983 INIT_LIST_HEAD(&clock->phylist); 984 clock->caps.owner = THIS_MODULE; 985 sprintf(clock->caps.name, "dp83640 timer"); 986 clock->caps.max_adj = 1953124; 987 clock->caps.n_alarm = 0; 988 clock->caps.n_ext_ts = N_EXT_TS; 989 clock->caps.n_per_out = N_PER_OUT; 990 clock->caps.n_pins = DP83640_N_PINS; 991 clock->caps.pps = 0; 992 clock->caps.adjfreq = ptp_dp83640_adjfreq; 993 clock->caps.adjtime = ptp_dp83640_adjtime; 994 clock->caps.gettime = ptp_dp83640_gettime; 995 clock->caps.settime = ptp_dp83640_settime; 996 clock->caps.enable = ptp_dp83640_enable; 997 clock->caps.verify = ptp_dp83640_verify; 998 /* 999 * Convert the module param defaults into a dynamic pin configuration. 1000 */ 1001 dp83640_gpio_defaults(clock->caps.pin_config); 1002 /* 1003 * Get a reference to this bus instance. 1004 */ 1005 get_device(&bus->dev); 1006 } 1007 1008 static int choose_this_phy(struct dp83640_clock *clock, 1009 struct phy_device *phydev) 1010 { 1011 if (chosen_phy == -1 && !clock->chosen) 1012 return 1; 1013 1014 if (chosen_phy == phydev->addr) 1015 return 1; 1016 1017 return 0; 1018 } 1019 1020 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 1021 { 1022 if (clock) 1023 mutex_lock(&clock->clock_lock); 1024 return clock; 1025 } 1026 1027 /* 1028 * Look up and lock a clock by bus instance. 1029 * If there is no clock for this bus, then create it first. 1030 */ 1031 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 1032 { 1033 struct dp83640_clock *clock = NULL, *tmp; 1034 struct list_head *this; 1035 1036 mutex_lock(&phyter_clocks_lock); 1037 1038 list_for_each(this, &phyter_clocks) { 1039 tmp = list_entry(this, struct dp83640_clock, list); 1040 if (tmp->bus == bus) { 1041 clock = tmp; 1042 break; 1043 } 1044 } 1045 if (clock) 1046 goto out; 1047 1048 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1049 if (!clock) 1050 goto out; 1051 1052 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) * 1053 DP83640_N_PINS, GFP_KERNEL); 1054 if (!clock->caps.pin_config) { 1055 kfree(clock); 1056 clock = NULL; 1057 goto out; 1058 } 1059 dp83640_clock_init(clock, bus); 1060 list_add_tail(&phyter_clocks, &clock->list); 1061 out: 1062 mutex_unlock(&phyter_clocks_lock); 1063 1064 return dp83640_clock_get(clock); 1065 } 1066 1067 static void dp83640_clock_put(struct dp83640_clock *clock) 1068 { 1069 mutex_unlock(&clock->clock_lock); 1070 } 1071 1072 static int dp83640_probe(struct phy_device *phydev) 1073 { 1074 struct dp83640_clock *clock; 1075 struct dp83640_private *dp83640; 1076 int err = -ENOMEM, i; 1077 1078 if (phydev->addr == BROADCAST_ADDR) 1079 return 0; 1080 1081 clock = dp83640_clock_get_bus(phydev->bus); 1082 if (!clock) 1083 goto no_clock; 1084 1085 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1086 if (!dp83640) 1087 goto no_memory; 1088 1089 dp83640->phydev = phydev; 1090 INIT_WORK(&dp83640->ts_work, rx_timestamp_work); 1091 1092 INIT_LIST_HEAD(&dp83640->rxts); 1093 INIT_LIST_HEAD(&dp83640->rxpool); 1094 for (i = 0; i < MAX_RXTS; i++) 1095 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1096 1097 phydev->priv = dp83640; 1098 1099 spin_lock_init(&dp83640->rx_lock); 1100 skb_queue_head_init(&dp83640->rx_queue); 1101 skb_queue_head_init(&dp83640->tx_queue); 1102 1103 dp83640->clock = clock; 1104 1105 if (choose_this_phy(clock, phydev)) { 1106 clock->chosen = dp83640; 1107 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev); 1108 if (IS_ERR(clock->ptp_clock)) { 1109 err = PTR_ERR(clock->ptp_clock); 1110 goto no_register; 1111 } 1112 } else 1113 list_add_tail(&dp83640->list, &clock->phylist); 1114 1115 dp83640_clock_put(clock); 1116 return 0; 1117 1118 no_register: 1119 clock->chosen = NULL; 1120 kfree(dp83640); 1121 no_memory: 1122 dp83640_clock_put(clock); 1123 no_clock: 1124 return err; 1125 } 1126 1127 static void dp83640_remove(struct phy_device *phydev) 1128 { 1129 struct dp83640_clock *clock; 1130 struct list_head *this, *next; 1131 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1132 struct sk_buff *skb; 1133 1134 if (phydev->addr == BROADCAST_ADDR) 1135 return; 1136 1137 enable_status_frames(phydev, false); 1138 cancel_work_sync(&dp83640->ts_work); 1139 1140 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) 1141 kfree_skb(skb); 1142 1143 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL) 1144 skb_complete_tx_timestamp(skb, NULL); 1145 1146 clock = dp83640_clock_get(dp83640->clock); 1147 1148 if (dp83640 == clock->chosen) { 1149 ptp_clock_unregister(clock->ptp_clock); 1150 clock->chosen = NULL; 1151 } else { 1152 list_for_each_safe(this, next, &clock->phylist) { 1153 tmp = list_entry(this, struct dp83640_private, list); 1154 if (tmp == dp83640) { 1155 list_del_init(&tmp->list); 1156 break; 1157 } 1158 } 1159 } 1160 1161 dp83640_clock_put(clock); 1162 kfree(dp83640); 1163 } 1164 1165 static int dp83640_config_init(struct phy_device *phydev) 1166 { 1167 struct dp83640_private *dp83640 = phydev->priv; 1168 struct dp83640_clock *clock = dp83640->clock; 1169 1170 if (clock->chosen && !list_empty(&clock->phylist)) 1171 recalibrate(clock); 1172 else 1173 enable_broadcast(phydev, clock->page, 1); 1174 1175 enable_status_frames(phydev, true); 1176 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1177 return 0; 1178 } 1179 1180 static int dp83640_ack_interrupt(struct phy_device *phydev) 1181 { 1182 int err = phy_read(phydev, MII_DP83640_MISR); 1183 1184 if (err < 0) 1185 return err; 1186 1187 return 0; 1188 } 1189 1190 static int dp83640_config_intr(struct phy_device *phydev) 1191 { 1192 int micr; 1193 int misr; 1194 int err; 1195 1196 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1197 misr = phy_read(phydev, MII_DP83640_MISR); 1198 if (misr < 0) 1199 return misr; 1200 misr |= 1201 (MII_DP83640_MISR_ANC_INT_EN | 1202 MII_DP83640_MISR_DUP_INT_EN | 1203 MII_DP83640_MISR_SPD_INT_EN | 1204 MII_DP83640_MISR_LINK_INT_EN); 1205 err = phy_write(phydev, MII_DP83640_MISR, misr); 1206 if (err < 0) 1207 return err; 1208 1209 micr = phy_read(phydev, MII_DP83640_MICR); 1210 if (micr < 0) 1211 return micr; 1212 micr |= 1213 (MII_DP83640_MICR_OE | 1214 MII_DP83640_MICR_IE); 1215 return phy_write(phydev, MII_DP83640_MICR, micr); 1216 } else { 1217 micr = phy_read(phydev, MII_DP83640_MICR); 1218 if (micr < 0) 1219 return micr; 1220 micr &= 1221 ~(MII_DP83640_MICR_OE | 1222 MII_DP83640_MICR_IE); 1223 err = phy_write(phydev, MII_DP83640_MICR, micr); 1224 if (err < 0) 1225 return err; 1226 1227 misr = phy_read(phydev, MII_DP83640_MISR); 1228 if (misr < 0) 1229 return misr; 1230 misr &= 1231 ~(MII_DP83640_MISR_ANC_INT_EN | 1232 MII_DP83640_MISR_DUP_INT_EN | 1233 MII_DP83640_MISR_SPD_INT_EN | 1234 MII_DP83640_MISR_LINK_INT_EN); 1235 return phy_write(phydev, MII_DP83640_MISR, misr); 1236 } 1237 } 1238 1239 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) 1240 { 1241 struct dp83640_private *dp83640 = phydev->priv; 1242 struct hwtstamp_config cfg; 1243 u16 txcfg0, rxcfg0; 1244 1245 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1246 return -EFAULT; 1247 1248 if (cfg.flags) /* reserved for future extensions */ 1249 return -EINVAL; 1250 1251 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1252 return -ERANGE; 1253 1254 dp83640->hwts_tx_en = cfg.tx_type; 1255 1256 switch (cfg.rx_filter) { 1257 case HWTSTAMP_FILTER_NONE: 1258 dp83640->hwts_rx_en = 0; 1259 dp83640->layer = 0; 1260 dp83640->version = 0; 1261 break; 1262 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1263 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1264 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1265 dp83640->hwts_rx_en = 1; 1266 dp83640->layer = LAYER4; 1267 dp83640->version = 1; 1268 break; 1269 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1270 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1271 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1272 dp83640->hwts_rx_en = 1; 1273 dp83640->layer = LAYER4; 1274 dp83640->version = 2; 1275 break; 1276 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1277 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1278 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1279 dp83640->hwts_rx_en = 1; 1280 dp83640->layer = LAYER2; 1281 dp83640->version = 2; 1282 break; 1283 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1284 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1285 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1286 dp83640->hwts_rx_en = 1; 1287 dp83640->layer = LAYER4|LAYER2; 1288 dp83640->version = 2; 1289 break; 1290 default: 1291 return -ERANGE; 1292 } 1293 1294 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1295 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1296 1297 if (dp83640->layer & LAYER2) { 1298 txcfg0 |= TX_L2_EN; 1299 rxcfg0 |= RX_L2_EN; 1300 } 1301 if (dp83640->layer & LAYER4) { 1302 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1303 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1304 } 1305 1306 if (dp83640->hwts_tx_en) 1307 txcfg0 |= TX_TS_EN; 1308 1309 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1310 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1311 1312 if (dp83640->hwts_rx_en) 1313 rxcfg0 |= RX_TS_EN; 1314 1315 mutex_lock(&dp83640->clock->extreg_lock); 1316 1317 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); 1318 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1319 1320 mutex_unlock(&dp83640->clock->extreg_lock); 1321 1322 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1323 } 1324 1325 static void rx_timestamp_work(struct work_struct *work) 1326 { 1327 struct dp83640_private *dp83640 = 1328 container_of(work, struct dp83640_private, ts_work); 1329 struct sk_buff *skb; 1330 1331 /* Deliver expired packets. */ 1332 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1333 struct dp83640_skb_info *skb_info; 1334 1335 skb_info = (struct dp83640_skb_info *)skb->cb; 1336 if (!time_after(jiffies, skb_info->tmo)) { 1337 skb_queue_head(&dp83640->rx_queue, skb); 1338 break; 1339 } 1340 1341 netif_rx_ni(skb); 1342 } 1343 1344 if (!skb_queue_empty(&dp83640->rx_queue)) 1345 schedule_work(&dp83640->ts_work); 1346 } 1347 1348 static bool dp83640_rxtstamp(struct phy_device *phydev, 1349 struct sk_buff *skb, int type) 1350 { 1351 struct dp83640_private *dp83640 = phydev->priv; 1352 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1353 struct list_head *this, *next; 1354 struct rxts *rxts; 1355 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1356 unsigned long flags; 1357 1358 if (is_status_frame(skb, type)) { 1359 decode_status_frame(dp83640, skb); 1360 kfree_skb(skb); 1361 return true; 1362 } 1363 1364 if (!dp83640->hwts_rx_en) 1365 return false; 1366 1367 spin_lock_irqsave(&dp83640->rx_lock, flags); 1368 list_for_each_safe(this, next, &dp83640->rxts) { 1369 rxts = list_entry(this, struct rxts, list); 1370 if (match(skb, type, rxts)) { 1371 shhwtstamps = skb_hwtstamps(skb); 1372 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1373 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1374 netif_rx_ni(skb); 1375 list_del_init(&rxts->list); 1376 list_add(&rxts->list, &dp83640->rxpool); 1377 break; 1378 } 1379 } 1380 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1381 1382 if (!shhwtstamps) { 1383 skb_info->ptp_type = type; 1384 skb_info->tmo = jiffies + 2; 1385 skb_queue_tail(&dp83640->rx_queue, skb); 1386 schedule_work(&dp83640->ts_work); 1387 } 1388 1389 return true; 1390 } 1391 1392 static void dp83640_txtstamp(struct phy_device *phydev, 1393 struct sk_buff *skb, int type) 1394 { 1395 struct dp83640_private *dp83640 = phydev->priv; 1396 1397 switch (dp83640->hwts_tx_en) { 1398 1399 case HWTSTAMP_TX_ONESTEP_SYNC: 1400 if (is_sync(skb, type)) { 1401 skb_complete_tx_timestamp(skb, NULL); 1402 return; 1403 } 1404 /* fall through */ 1405 case HWTSTAMP_TX_ON: 1406 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1407 skb_queue_tail(&dp83640->tx_queue, skb); 1408 break; 1409 1410 case HWTSTAMP_TX_OFF: 1411 default: 1412 skb_complete_tx_timestamp(skb, NULL); 1413 break; 1414 } 1415 } 1416 1417 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) 1418 { 1419 struct dp83640_private *dp83640 = dev->priv; 1420 1421 info->so_timestamping = 1422 SOF_TIMESTAMPING_TX_HARDWARE | 1423 SOF_TIMESTAMPING_RX_HARDWARE | 1424 SOF_TIMESTAMPING_RAW_HARDWARE; 1425 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1426 info->tx_types = 1427 (1 << HWTSTAMP_TX_OFF) | 1428 (1 << HWTSTAMP_TX_ON) | 1429 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1430 info->rx_filters = 1431 (1 << HWTSTAMP_FILTER_NONE) | 1432 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1433 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1434 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1435 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1436 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1437 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1438 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1439 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 1440 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 1441 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1442 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1443 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1444 return 0; 1445 } 1446 1447 static struct phy_driver dp83640_driver = { 1448 .phy_id = DP83640_PHY_ID, 1449 .phy_id_mask = 0xfffffff0, 1450 .name = "NatSemi DP83640", 1451 .features = PHY_BASIC_FEATURES, 1452 .flags = PHY_HAS_INTERRUPT, 1453 .probe = dp83640_probe, 1454 .remove = dp83640_remove, 1455 .config_init = dp83640_config_init, 1456 .config_aneg = genphy_config_aneg, 1457 .read_status = genphy_read_status, 1458 .ack_interrupt = dp83640_ack_interrupt, 1459 .config_intr = dp83640_config_intr, 1460 .ts_info = dp83640_ts_info, 1461 .hwtstamp = dp83640_hwtstamp, 1462 .rxtstamp = dp83640_rxtstamp, 1463 .txtstamp = dp83640_txtstamp, 1464 .driver = {.owner = THIS_MODULE,} 1465 }; 1466 1467 static int __init dp83640_init(void) 1468 { 1469 return phy_driver_register(&dp83640_driver); 1470 } 1471 1472 static void __exit dp83640_exit(void) 1473 { 1474 dp83640_free_clocks(); 1475 phy_driver_unregister(&dp83640_driver); 1476 } 1477 1478 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1479 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1480 MODULE_LICENSE("GPL"); 1481 1482 module_init(dp83640_init); 1483 module_exit(dp83640_exit); 1484 1485 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1486 { DP83640_PHY_ID, 0xfffffff0 }, 1487 { } 1488 }; 1489 1490 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1491