1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/broadcom.c 4 * 5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet 6 * transceivers. 7 * 8 * Broadcom BCM54810, BCM54811 BroadR-Reach transceivers. 9 * 10 * Copyright (c) 2006 Maciej W. Rozycki 11 * 12 * Inspired by code written by Amy Fong. 13 */ 14 15 #include "bcm-phy-lib.h" 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/phy.h> 19 #include <linux/device.h> 20 #include <linux/brcmphy.h> 21 #include <linux/of.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/gpio/consumer.h> 25 26 #define BRCM_PHY_REV(phydev) \ 27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask)) 28 29 MODULE_DESCRIPTION("Broadcom PHY driver"); 30 MODULE_AUTHOR("Maciej W. Rozycki"); 31 MODULE_LICENSE("GPL"); 32 33 struct bcm54xx_phy_priv { 34 u64 *stats; 35 struct bcm_ptp_private *ptp; 36 int wake_irq; 37 bool wake_irq_enabled; 38 bool brr_mode; 39 }; 40 41 /* Link modes for BCM58411 PHY */ 42 static const int bcm54811_linkmodes[] = { 43 ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 44 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 45 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 46 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 47 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 48 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 49 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 50 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 51 ETHTOOL_LINK_MODE_10baseT_Half_BIT 52 }; 53 54 /* Long-Distance Signaling (BroadR-Reach mode aneg) relevant linkmode bits */ 55 static const int lds_br_bits[] = { 56 ETHTOOL_LINK_MODE_Autoneg_BIT, 57 ETHTOOL_LINK_MODE_Pause_BIT, 58 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 59 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 60 ETHTOOL_LINK_MODE_100baseT1_Full_BIT 61 }; 62 63 static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev) 64 { 65 struct bcm54xx_phy_priv *priv = phydev->priv; 66 67 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; 68 } 69 70 static int bcm54xx_config_clock_delay(struct phy_device *phydev) 71 { 72 int rc, val; 73 74 /* handling PHY's internal RX clock delay */ 75 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 76 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 79 /* Disable RGMII RXC-RXD skew */ 80 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 81 } 82 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 83 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 84 /* Enable RGMII RXC-RXD skew */ 85 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 86 } 87 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 88 val); 89 if (rc < 0) 90 return rc; 91 92 /* handling PHY's internal TX clock delay */ 93 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); 94 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 95 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 96 /* Disable internal TX clock delay */ 97 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; 98 } 99 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 100 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 101 /* Enable internal TX clock delay */ 102 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; 103 } 104 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); 105 if (rc < 0) 106 return rc; 107 108 return 0; 109 } 110 111 static int bcm54210e_config_init(struct phy_device *phydev) 112 { 113 int val; 114 115 bcm54xx_config_clock_delay(phydev); 116 117 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { 118 val = phy_read(phydev, MII_CTRL1000); 119 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; 120 phy_write(phydev, MII_CTRL1000, val); 121 } 122 123 return 0; 124 } 125 126 static int bcm54612e_config_init(struct phy_device *phydev) 127 { 128 int reg; 129 130 bcm54xx_config_clock_delay(phydev); 131 132 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 133 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 134 int err; 135 136 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 137 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 138 BCM54612E_LED4_CLK125OUT_EN | reg); 139 140 if (err < 0) 141 return err; 142 } 143 144 return 0; 145 } 146 147 static int bcm54616s_config_init(struct phy_device *phydev) 148 { 149 int rc, val; 150 151 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 152 phydev->interface != PHY_INTERFACE_MODE_1000BASEX) 153 return 0; 154 155 /* Ensure proper interface mode is selected. */ 156 /* Disable RGMII mode */ 157 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 158 if (val < 0) 159 return val; 160 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN; 161 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 162 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 163 val); 164 if (rc < 0) 165 return rc; 166 167 /* Select 1000BASE-X register set (primary SerDes) */ 168 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 169 if (val < 0) 170 return val; 171 val |= BCM54XX_SHD_MODE_1000BX; 172 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 173 if (rc < 0) 174 return rc; 175 176 /* Power down SerDes interface */ 177 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); 178 if (rc < 0) 179 return rc; 180 181 /* Select proper interface mode */ 182 val &= ~BCM54XX_SHD_INTF_SEL_MASK; 183 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ? 184 BCM54XX_SHD_INTF_SEL_SGMII : 185 BCM54XX_SHD_INTF_SEL_GBIC; 186 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 187 if (rc < 0) 188 return rc; 189 190 /* Power up SerDes interface */ 191 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 192 if (rc < 0) 193 return rc; 194 195 /* Select copper register set */ 196 val &= ~BCM54XX_SHD_MODE_1000BX; 197 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 198 if (rc < 0) 199 return rc; 200 201 /* Power up copper interface */ 202 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 203 } 204 205 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */ 206 static int bcm50610_a0_workaround(struct phy_device *phydev) 207 { 208 int err; 209 210 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0, 211 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN | 212 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF); 213 if (err < 0) 214 return err; 215 216 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3, 217 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ); 218 if (err < 0) 219 return err; 220 221 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, 222 MII_BCM54XX_EXP_EXP75_VDACCTRL); 223 if (err < 0) 224 return err; 225 226 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96, 227 MII_BCM54XX_EXP_EXP96_MYST); 228 if (err < 0) 229 return err; 230 231 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97, 232 MII_BCM54XX_EXP_EXP97_MYST); 233 234 return err; 235 } 236 237 static int bcm54xx_phydsp_config(struct phy_device *phydev) 238 { 239 int err, err2; 240 241 /* Enable the SMDSP clock */ 242 err = bcm54xx_auxctl_write(phydev, 243 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 244 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA | 245 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 246 if (err < 0) 247 return err; 248 249 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 250 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) { 251 /* Clear bit 9 to fix a phy interop issue. */ 252 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, 253 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ); 254 if (err < 0) 255 goto error; 256 257 if (phydev->drv->phy_id == PHY_ID_BCM50610) { 258 err = bcm50610_a0_workaround(phydev); 259 if (err < 0) 260 goto error; 261 } 262 } 263 264 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM57780)) { 265 int val; 266 267 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); 268 if (val < 0) 269 goto error; 270 271 val |= MII_BCM54XX_EXP_EXP75_CM_OSC; 272 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); 273 } 274 275 error: 276 /* Disable the SMDSP clock */ 277 err2 = bcm54xx_auxctl_write(phydev, 278 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 279 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 280 281 /* Return the first error reported. */ 282 return err ? err : err2; 283 } 284 285 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) 286 { 287 u32 orig; 288 int val; 289 bool clk125en = true; 290 291 /* Abort if we are using an untested phy. */ 292 if (!(phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM57780) || 293 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 294 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M) || 295 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54210E) || 296 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54810) || 297 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811))) 298 return; 299 300 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); 301 if (val < 0) 302 return; 303 304 orig = val; 305 306 if ((phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 307 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) && 308 BRCM_PHY_REV(phydev) >= 0x3) { 309 /* 310 * Here, bit 0 _disables_ CLK125 when set. 311 * This bit is set by default. 312 */ 313 clk125en = false; 314 } else { 315 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) { 316 if (!phy_id_compare_model(phydev->drv->phy_id, 317 PHY_ID_BCM54811)) { 318 /* Here, bit 0 _enables_ CLK125 when set */ 319 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125; 320 } 321 clk125en = false; 322 } 323 } 324 325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 326 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS; 327 else 328 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; 329 330 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) { 331 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54210E) || 332 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54810) || 333 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811)) 334 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS; 335 else 336 val |= BCM54XX_SHD_SCR3_TRDDAPD; 337 } 338 339 if (orig != val) 340 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); 341 342 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); 343 if (val < 0) 344 return; 345 346 orig = val; 347 348 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 349 val |= BCM54XX_SHD_APD_EN; 350 else 351 val &= ~BCM54XX_SHD_APD_EN; 352 353 if (orig != val) 354 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); 355 } 356 357 static void bcm54xx_ptp_stop(struct phy_device *phydev) 358 { 359 struct bcm54xx_phy_priv *priv = phydev->priv; 360 361 if (priv->ptp) 362 bcm_ptp_stop(priv->ptp); 363 } 364 365 static void bcm54xx_ptp_config_init(struct phy_device *phydev) 366 { 367 struct bcm54xx_phy_priv *priv = phydev->priv; 368 369 if (priv->ptp) 370 bcm_ptp_config_init(phydev); 371 } 372 373 static int bcm5481x_set_brrmode(struct phy_device *phydev, bool on) 374 { 375 int reg; 376 int err; 377 u16 val; 378 379 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 380 381 if (reg < 0) 382 return reg; 383 384 if (on) 385 reg |= BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 386 else 387 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 388 389 err = bcm_phy_write_exp(phydev, 390 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, reg); 391 if (err) 392 return err; 393 394 /* Ensure LRE or IEEE register set is accessed according to the brr 395 * on/off, thus set the override 396 */ 397 val = BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_EN; 398 if (!on) 399 val |= BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_OVERRIDE_VAL; 400 401 return bcm_phy_write_exp(phydev, 402 BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL, val); 403 } 404 405 static int bcm54811_config_init(struct phy_device *phydev) 406 { 407 struct bcm54xx_phy_priv *priv = phydev->priv; 408 int err, reg, exp_sync_ethernet, aux_rgmii_en; 409 410 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 411 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 412 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 413 if (reg < 0) 414 return reg; 415 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 416 BCM54612E_LED4_CLK125OUT_EN | reg); 417 if (err < 0) 418 return err; 419 } 420 421 /* With BCM54811, BroadR-Reach implies no autoneg */ 422 if (priv->brr_mode) 423 phydev->autoneg = 0; 424 425 /* Enable MII Lite (No TXER, RXER, CRS, COL) if configured */ 426 if (phydev->interface == PHY_INTERFACE_MODE_MIILITE) 427 exp_sync_ethernet = BCM_EXP_SYNC_ETHERNET_MII_LITE; 428 else 429 exp_sync_ethernet = 0; 430 431 err = bcm_phy_modify_exp(phydev, BCM_EXP_SYNC_ETHERNET, 432 BCM_EXP_SYNC_ETHERNET_MII_LITE, 433 exp_sync_ethernet); 434 if (err < 0) 435 return err; 436 437 /* Enable RGMII if configured */ 438 if (phy_interface_is_rgmii(phydev)) 439 aux_rgmii_en = MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN | 440 MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 441 else 442 aux_rgmii_en = 0; 443 444 /* Also writing Reserved bits 6:5 because the documentation requires 445 * them to be written to 0b11 446 */ 447 err = bcm54xx_auxctl_write(phydev, 448 MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 449 MII_BCM54XX_AUXCTL_MISC_WREN | 450 aux_rgmii_en | 451 MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RSVD); 452 if (err < 0) 453 return err; 454 455 return bcm5481x_set_brrmode(phydev, priv->brr_mode); 456 } 457 458 static int bcm54xx_config_init(struct phy_device *phydev) 459 { 460 int reg, err, val; 461 462 reg = phy_read(phydev, MII_BCM54XX_ECR); 463 if (reg < 0) 464 return reg; 465 466 /* Mask interrupts globally. */ 467 reg |= MII_BCM54XX_ECR_IM; 468 err = phy_write(phydev, MII_BCM54XX_ECR, reg); 469 if (err < 0) 470 return err; 471 472 /* Unmask events we are interested in. */ 473 reg = ~(MII_BCM54XX_INT_DUPLEX | 474 MII_BCM54XX_INT_SPEED | 475 MII_BCM54XX_INT_LINK); 476 err = phy_write(phydev, MII_BCM54XX_IMR, reg); 477 if (err < 0) 478 return err; 479 480 if ((phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 481 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) && 482 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) 483 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); 484 485 bcm54xx_adjust_rxrefclk(phydev); 486 487 switch (phydev->drv->phy_id & PHY_ID_MATCH_MODEL_MASK) { 488 case PHY_ID_BCM50610: 489 case PHY_ID_BCM50610M: 490 err = bcm54xx_config_clock_delay(phydev); 491 break; 492 case PHY_ID_BCM54210E: 493 err = bcm54210e_config_init(phydev); 494 break; 495 case PHY_ID_BCM54612E: 496 err = bcm54612e_config_init(phydev); 497 break; 498 case PHY_ID_BCM54616S: 499 err = bcm54616s_config_init(phydev); 500 break; 501 case PHY_ID_BCM54810: 502 /* For BCM54810, we need to disable BroadR-Reach function */ 503 val = bcm_phy_read_exp(phydev, 504 BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 505 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 506 err = bcm_phy_write_exp(phydev, 507 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 508 val); 509 break; 510 case PHY_ID_BCM54811: 511 err = bcm54811_config_init(phydev); 512 break; 513 } 514 if (err) 515 return err; 516 517 bcm54xx_phydsp_config(phydev); 518 519 /* For non-SFP setups, encode link speed into LED1 and LED3 pair 520 * (green/amber). 521 * Also flash these two LEDs on activity. This means configuring 522 * them for MULTICOLOR and encoding link/activity into them. 523 * Don't do this for devices on an SFP module, since some of these 524 * use the LED outputs to control the SFP LOS signal, and changing 525 * these settings will cause LOS to malfunction. 526 */ 527 if (!phy_on_sfp(phydev)) { 528 val = BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) | 529 BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1); 530 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val); 531 532 val = BCM_LED_MULTICOLOR_IN_PHASE | 533 BCM54XX_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) | 534 BCM54XX_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT); 535 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); 536 } 537 538 bcm54xx_ptp_config_init(phydev); 539 540 /* Acknowledge any left over interrupt and charge the device for 541 * wake-up. 542 */ 543 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 544 if (err < 0) 545 return err; 546 547 if (err) 548 pm_wakeup_event(&phydev->mdio.dev, 0); 549 550 return 0; 551 } 552 553 static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable) 554 { 555 int ret = 0; 556 557 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND)) 558 return ret; 559 560 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL); 561 if (ret < 0) 562 goto out; 563 564 if (enable) 565 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP; 566 else 567 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP); 568 569 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret); 570 out: 571 return ret; 572 } 573 574 static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state) 575 { 576 struct bcm54xx_phy_priv *priv = phydev->priv; 577 int ret = 0; 578 579 if (!bcm54xx_phy_can_wakeup(phydev)) 580 return ret; 581 582 if (priv->wake_irq_enabled != state) { 583 if (state) 584 ret = enable_irq_wake(priv->wake_irq); 585 else 586 ret = disable_irq_wake(priv->wake_irq); 587 priv->wake_irq_enabled = state; 588 } 589 590 return ret; 591 } 592 593 static int bcm54xx_suspend(struct phy_device *phydev) 594 { 595 int ret = 0; 596 597 bcm54xx_ptp_stop(phydev); 598 599 /* Acknowledge any Wake-on-LAN interrupt prior to suspend */ 600 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 601 if (ret < 0) 602 return ret; 603 604 if (phydev->wol_enabled) 605 return bcm54xx_set_wakeup_irq(phydev, true); 606 607 /* We cannot use a read/modify/write here otherwise the PHY gets into 608 * a bad state where its LEDs keep flashing, thus defeating the purpose 609 * of low power mode. 610 */ 611 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 612 if (ret < 0) 613 return ret; 614 615 return bcm54xx_iddq_set(phydev, true); 616 } 617 618 static int bcm54xx_resume(struct phy_device *phydev) 619 { 620 int ret = 0; 621 622 if (phydev->wol_enabled) { 623 ret = bcm54xx_set_wakeup_irq(phydev, false); 624 if (ret) 625 return ret; 626 } 627 628 ret = bcm54xx_iddq_set(phydev, false); 629 if (ret < 0) 630 return ret; 631 632 /* Writes to register other than BMCR would be ignored 633 * unless we clear the PDOWN bit first 634 */ 635 ret = genphy_resume(phydev); 636 if (ret < 0) 637 return ret; 638 639 /* Upon exiting power down, the PHY remains in an internal reset state 640 * for 40us 641 */ 642 fsleep(40); 643 644 /* Issue a soft reset after clearing the power down bit 645 * and before doing any other configuration. 646 */ 647 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) { 648 ret = genphy_soft_reset(phydev); 649 if (ret < 0) 650 return ret; 651 } 652 653 return bcm54xx_config_init(phydev); 654 } 655 656 static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 657 { 658 return -EOPNOTSUPP; 659 } 660 661 static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 662 u16 val) 663 { 664 return -EOPNOTSUPP; 665 } 666 667 668 /** 669 * bcm5481x_read_abilities - read PHY abilities from LRESR or Clause 22 670 * (BMSR) registers, based on whether the PHY is in BroadR-Reach or IEEE mode 671 * @phydev: target phy_device struct 672 * 673 * Description: Reads the PHY's abilities and populates phydev->supported 674 * accordingly. The register to read the abilities from is determined by 675 * the brr mode setting of the PHY as read from the device tree. 676 * Note that the LRE and IEEE sets of abilities are disjunct, in other words, 677 * not only the link modes differ, but also the auto-negotiation and 678 * master-slave setup is controlled differently. 679 * 680 * Returns: 0 on success, < 0 on failure 681 */ 682 static int bcm5481x_read_abilities(struct phy_device *phydev) 683 { 684 struct device_node *np = phydev->mdio.dev.of_node; 685 struct bcm54xx_phy_priv *priv = phydev->priv; 686 int i, val, err, aneg; 687 688 for (i = 0; i < ARRAY_SIZE(bcm54811_linkmodes); i++) 689 linkmode_clear_bit(bcm54811_linkmodes[i], phydev->supported); 690 691 priv->brr_mode = of_property_read_bool(np, "brr-mode"); 692 693 /* Set BroadR-Reach mode as configured in the DT. */ 694 err = bcm5481x_set_brrmode(phydev, priv->brr_mode); 695 if (err) 696 return err; 697 698 if (priv->brr_mode) { 699 linkmode_set_bit_array(phy_basic_ports_array, 700 ARRAY_SIZE(phy_basic_ports_array), 701 phydev->supported); 702 703 val = phy_read(phydev, MII_BCM54XX_LRESR); 704 if (val < 0) 705 return val; 706 707 /* BCM54811 is not capable of LDS but the corresponding bit 708 * in LRESR is set to 1 and marked "Ignore" in the datasheet. 709 * So we must read the bcm54811 as unable to auto-negotiate 710 * in BroadR-Reach mode. 711 */ 712 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811)) 713 aneg = 0; 714 else 715 aneg = val & LRESR_LDSABILITY; 716 717 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 718 phydev->supported, 719 aneg); 720 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 721 phydev->supported, 722 val & LRESR_100_1PAIR); 723 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 724 phydev->supported, 725 val & LRESR_10_1PAIR); 726 return 0; 727 } 728 729 return genphy_read_abilities(phydev); 730 } 731 732 static int bcm5481x_config_delay_swap(struct phy_device *phydev) 733 { 734 struct device_node *np = phydev->mdio.dev.of_node; 735 736 /* Set up the delay. */ 737 bcm54xx_config_clock_delay(phydev); 738 739 if (of_property_read_bool(np, "enet-phy-lane-swap")) { 740 /* Lane Swap - Undocumented register...magic! */ 741 int ret = bcm_phy_write_exp(phydev, 742 MII_BCM54XX_EXP_SEL_ER + 0x9, 743 0x11B); 744 if (ret < 0) 745 return ret; 746 } 747 748 return 0; 749 } 750 751 static int bcm5481_config_aneg(struct phy_device *phydev) 752 { 753 struct bcm54xx_phy_priv *priv = phydev->priv; 754 int ret; 755 756 /* Aneg firstly. */ 757 if (priv->brr_mode) 758 ret = bcm_config_lre_aneg(phydev, false); 759 else 760 ret = genphy_config_aneg(phydev); 761 762 if (ret) 763 return ret; 764 765 /* Then we can set up the delay and swap. */ 766 return bcm5481x_config_delay_swap(phydev); 767 } 768 769 static int bcm54811_config_aneg(struct phy_device *phydev) 770 { 771 struct bcm54xx_phy_priv *priv = phydev->priv; 772 int ret; 773 774 /* Aneg firstly. */ 775 if (priv->brr_mode) { 776 /* BCM54811 is only capable of autonegotiation in IEEE mode. 777 * In BroadR-Reach mode, disable the Long Distance Signaling, 778 * the BRR mode autoneg as supported in other Broadcom PHYs. 779 * This bit is marked as "Reserved" and "Default 1, must be 780 * written to 0 after every device reset" in the datasheet. 781 */ 782 ret = phy_modify(phydev, MII_BCM54XX_LRECR, LRECR_LDSEN, 0); 783 if (ret < 0) 784 return ret; 785 ret = bcm_config_lre_aneg(phydev, false); 786 } else { 787 ret = genphy_config_aneg(phydev); 788 } 789 790 if (ret) 791 return ret; 792 793 /* Then we can set up the delay and swap. */ 794 return bcm5481x_config_delay_swap(phydev); 795 } 796 797 struct bcm54616s_phy_priv { 798 bool mode_1000bx_en; 799 }; 800 801 static int bcm54616s_probe(struct phy_device *phydev) 802 { 803 struct bcm54616s_phy_priv *priv; 804 int val; 805 806 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 807 if (!priv) 808 return -ENOMEM; 809 810 phydev->priv = priv; 811 812 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 813 if (val < 0) 814 return val; 815 816 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0] 817 * is 01b, and the link between PHY and its link partner can be 818 * either 1000Base-X or 100Base-FX. 819 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX 820 * support is still missing as of now. 821 */ 822 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) { 823 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL); 824 if (val < 0) 825 return val; 826 827 /* Bit 0 of the SerDes 100-FX Control register, when set 828 * to 1, sets the MII/RGMII -> 100BASE-FX configuration. 829 * When this bit is set to 0, it sets the GMII/RGMII -> 830 * 1000BASE-X configuration. 831 */ 832 if (!(val & BCM54616S_100FX_MODE)) 833 priv->mode_1000bx_en = true; 834 835 phydev->port = PORT_FIBRE; 836 } 837 838 return 0; 839 } 840 841 static int bcm54616s_config_aneg(struct phy_device *phydev) 842 { 843 struct bcm54616s_phy_priv *priv = phydev->priv; 844 int ret; 845 846 /* Aneg firstly. */ 847 if (priv->mode_1000bx_en) 848 ret = genphy_c37_config_aneg(phydev); 849 else 850 ret = genphy_config_aneg(phydev); 851 852 /* Then we can set up the delay. */ 853 bcm54xx_config_clock_delay(phydev); 854 855 return ret; 856 } 857 858 static int bcm54616s_read_status(struct phy_device *phydev) 859 { 860 struct bcm54616s_phy_priv *priv = phydev->priv; 861 bool changed; 862 int err; 863 864 if (priv->mode_1000bx_en) 865 err = genphy_c37_read_status(phydev, &changed); 866 else 867 err = genphy_read_status(phydev); 868 869 return err; 870 } 871 872 static int brcm_fet_config_init(struct phy_device *phydev) 873 { 874 int reg, err, err2, brcmtest; 875 876 /* Reset the PHY to bring it to a known state. */ 877 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 878 if (err < 0) 879 return err; 880 881 /* The datasheet indicates the PHY needs up to 1us to complete a reset, 882 * build some slack here. 883 */ 884 usleep_range(1000, 2000); 885 886 /* The PHY requires 65 MDC clock cycles to complete a write operation 887 * and turnaround the line properly. 888 * 889 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac) 890 * may flag the lack of turn-around as a read failure. This is 891 * particularly true with this combination since the MDIO controller 892 * only used 64 MDC cycles. This is not a critical failure in this 893 * specific case and it has no functional impact otherwise, so we let 894 * that one go through. If there is a genuine bus error, the next read 895 * of MII_BRCM_FET_INTREG will error out. 896 */ 897 err = phy_read(phydev, MII_BMCR); 898 if (err < 0 && err != -EIO) 899 return err; 900 901 /* Read to clear status bits */ 902 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 903 if (reg < 0) 904 return reg; 905 906 /* Unmask events we are interested in and mask interrupts globally. */ 907 if (phydev->drv->phy_id == PHY_ID_BCM5221) 908 reg = MII_BRCM_FET_IR_ENABLE | 909 MII_BRCM_FET_IR_MASK; 910 else 911 reg = MII_BRCM_FET_IR_DUPLEX_EN | 912 MII_BRCM_FET_IR_SPEED_EN | 913 MII_BRCM_FET_IR_LINK_EN | 914 MII_BRCM_FET_IR_ENABLE | 915 MII_BRCM_FET_IR_MASK; 916 917 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 918 if (err < 0) 919 return err; 920 921 /* Enable shadow register access */ 922 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 923 if (brcmtest < 0) 924 return brcmtest; 925 926 reg = brcmtest | MII_BRCM_FET_BT_SRE; 927 928 phy_lock_mdio_bus(phydev); 929 930 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 931 if (err < 0) { 932 phy_unlock_mdio_bus(phydev); 933 return err; 934 } 935 936 if (phydev->drv->phy_id != PHY_ID_BCM5221) { 937 /* Set the LED mode */ 938 reg = __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); 939 if (reg < 0) { 940 err = reg; 941 goto done; 942 } 943 944 err = __phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4, 945 MII_BRCM_FET_SHDW_AM4_LED_MASK, 946 MII_BRCM_FET_SHDW_AM4_LED_MODE1); 947 if (err < 0) 948 goto done; 949 950 /* Enable auto MDIX */ 951 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, 952 MII_BRCM_FET_SHDW_MC_FAME); 953 if (err < 0) 954 goto done; 955 } 956 957 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { 958 /* Enable auto power down */ 959 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, 960 MII_BRCM_FET_SHDW_AS2_APDE); 961 } 962 963 done: 964 /* Disable shadow register access */ 965 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 966 if (!err) 967 err = err2; 968 969 phy_unlock_mdio_bus(phydev); 970 971 return err; 972 } 973 974 static int brcm_fet_ack_interrupt(struct phy_device *phydev) 975 { 976 int reg; 977 978 /* Clear pending interrupts. */ 979 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 980 if (reg < 0) 981 return reg; 982 983 return 0; 984 } 985 986 static int brcm_fet_config_intr(struct phy_device *phydev) 987 { 988 int reg, err; 989 990 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 991 if (reg < 0) 992 return reg; 993 994 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 995 err = brcm_fet_ack_interrupt(phydev); 996 if (err) 997 return err; 998 999 reg &= ~MII_BRCM_FET_IR_MASK; 1000 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 1001 } else { 1002 reg |= MII_BRCM_FET_IR_MASK; 1003 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 1004 if (err) 1005 return err; 1006 1007 err = brcm_fet_ack_interrupt(phydev); 1008 } 1009 1010 return err; 1011 } 1012 1013 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev) 1014 { 1015 int irq_status; 1016 1017 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG); 1018 if (irq_status < 0) { 1019 phy_error(phydev); 1020 return IRQ_NONE; 1021 } 1022 1023 if (irq_status == 0) 1024 return IRQ_NONE; 1025 1026 phy_trigger_machine(phydev); 1027 1028 return IRQ_HANDLED; 1029 } 1030 1031 static int brcm_fet_suspend(struct phy_device *phydev) 1032 { 1033 int reg, err, err2, brcmtest; 1034 1035 /* We cannot use a read/modify/write here otherwise the PHY continues 1036 * to drive LEDs which defeats the purpose of low power mode. 1037 */ 1038 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 1039 if (err < 0) 1040 return err; 1041 1042 /* Enable shadow register access */ 1043 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 1044 if (brcmtest < 0) 1045 return brcmtest; 1046 1047 reg = brcmtest | MII_BRCM_FET_BT_SRE; 1048 1049 phy_lock_mdio_bus(phydev); 1050 1051 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 1052 if (err < 0) { 1053 phy_unlock_mdio_bus(phydev); 1054 return err; 1055 } 1056 1057 if (phydev->drv->phy_id == PHY_ID_BCM5221) 1058 /* Force Low Power Mode with clock enabled */ 1059 reg = BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM; 1060 else 1061 /* Set standby mode */ 1062 reg = MII_BRCM_FET_SHDW_AM4_STANDBY; 1063 1064 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); 1065 1066 /* Disable shadow register access */ 1067 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 1068 if (!err) 1069 err = err2; 1070 1071 phy_unlock_mdio_bus(phydev); 1072 1073 return err; 1074 } 1075 1076 static int bcm5221_config_aneg(struct phy_device *phydev) 1077 { 1078 int ret, val; 1079 1080 ret = genphy_config_aneg(phydev); 1081 if (ret) 1082 return ret; 1083 1084 switch (phydev->mdix_ctrl) { 1085 case ETH_TP_MDI: 1086 val = BCM5221_AEGSR_MDIX_DIS; 1087 break; 1088 case ETH_TP_MDI_X: 1089 val = BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP; 1090 break; 1091 case ETH_TP_MDI_AUTO: 1092 val = 0; 1093 break; 1094 default: 1095 return 0; 1096 } 1097 1098 return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP | 1099 BCM5221_AEGSR_MDIX_DIS, 1100 val); 1101 } 1102 1103 static int bcm5221_read_status(struct phy_device *phydev) 1104 { 1105 int ret; 1106 1107 /* Read MDIX status */ 1108 ret = phy_read(phydev, BCM5221_AEGSR); 1109 if (ret < 0) 1110 return ret; 1111 1112 if (ret & BCM5221_AEGSR_MDIX_DIS) { 1113 if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP) 1114 phydev->mdix_ctrl = ETH_TP_MDI_X; 1115 else 1116 phydev->mdix_ctrl = ETH_TP_MDI; 1117 } else { 1118 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1119 } 1120 1121 if (ret & BCM5221_AEGSR_MDIX_STATUS) 1122 phydev->mdix = ETH_TP_MDI_X; 1123 else 1124 phydev->mdix = ETH_TP_MDI; 1125 1126 return genphy_read_status(phydev); 1127 } 1128 1129 static void bcm54xx_phy_get_wol(struct phy_device *phydev, 1130 struct ethtool_wolinfo *wol) 1131 { 1132 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 1133 * or an out of band GPIO descriptor for wake-up. Zeroing 1134 * wol->supported allows the caller (MAC driver) to play through and 1135 * offer its own Wake-on-LAN scheme if available. 1136 */ 1137 if (!bcm54xx_phy_can_wakeup(phydev)) { 1138 wol->supported = 0; 1139 return; 1140 } 1141 1142 bcm_phy_get_wol(phydev, wol); 1143 } 1144 1145 static int bcm54xx_phy_set_wol(struct phy_device *phydev, 1146 struct ethtool_wolinfo *wol) 1147 { 1148 int ret; 1149 1150 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 1151 * or an out of band GPIO descriptor for wake-up. Returning -EOPNOTSUPP 1152 * allows the caller (MAC driver) to play through and offer its own 1153 * Wake-on-LAN scheme if available. 1154 */ 1155 if (!bcm54xx_phy_can_wakeup(phydev)) 1156 return -EOPNOTSUPP; 1157 1158 ret = bcm_phy_set_wol(phydev, wol); 1159 if (ret < 0) 1160 return ret; 1161 1162 return 0; 1163 } 1164 1165 static int bcm54xx_phy_probe(struct phy_device *phydev) 1166 { 1167 struct bcm54xx_phy_priv *priv; 1168 struct gpio_desc *wakeup_gpio; 1169 int ret = 0; 1170 1171 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1172 if (!priv) 1173 return -ENOMEM; 1174 1175 priv->wake_irq = -ENXIO; 1176 1177 phydev->priv = priv; 1178 1179 priv->stats = devm_kcalloc(&phydev->mdio.dev, 1180 bcm_phy_get_sset_count(phydev), sizeof(u64), 1181 GFP_KERNEL); 1182 if (!priv->stats) 1183 return -ENOMEM; 1184 1185 priv->ptp = bcm_ptp_probe(phydev); 1186 if (IS_ERR(priv->ptp)) 1187 return PTR_ERR(priv->ptp); 1188 1189 /* We cannot utilize the _optional variant here since we want to know 1190 * whether the GPIO descriptor exists or not to advertise Wake-on-LAN 1191 * support or not. 1192 */ 1193 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN); 1194 if (PTR_ERR(wakeup_gpio) == -EPROBE_DEFER) 1195 return PTR_ERR(wakeup_gpio); 1196 1197 if (!IS_ERR(wakeup_gpio)) { 1198 priv->wake_irq = gpiod_to_irq(wakeup_gpio); 1199 1200 /* Dummy interrupt handler which is not enabled but is provided 1201 * in order for the interrupt descriptor to be fully set-up. 1202 */ 1203 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq, 1204 bcm_phy_wol_isr, 1205 IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN, 1206 dev_name(&phydev->mdio.dev), phydev); 1207 if (ret) 1208 return ret; 1209 } 1210 1211 /* If we do not have a main interrupt or a side-band wake-up interrupt, 1212 * then the device cannot be marked as wake-up capable. 1213 */ 1214 if (!bcm54xx_phy_can_wakeup(phydev)) 1215 return 0; 1216 1217 return device_init_wakeup(&phydev->mdio.dev, true); 1218 } 1219 1220 static void bcm54xx_get_stats(struct phy_device *phydev, 1221 struct ethtool_stats *stats, u64 *data) 1222 { 1223 struct bcm54xx_phy_priv *priv = phydev->priv; 1224 1225 bcm_phy_get_stats(phydev, priv->stats, stats, data); 1226 } 1227 1228 static void bcm54xx_link_change_notify(struct phy_device *phydev) 1229 { 1230 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE | 1231 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE; 1232 int ret; 1233 1234 if (phydev->state != PHY_RUNNING) 1235 return; 1236 1237 /* Don't change the DAC wake settings if auto power down 1238 * is not requested. 1239 */ 1240 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 1241 return; 1242 1243 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08); 1244 if (ret < 0) 1245 return; 1246 1247 /* Enable/disable 10BaseT auto and forced early DAC wake depending 1248 * on the negotiated speed, those settings should only be done 1249 * for 10Mbits/sec. 1250 */ 1251 if (phydev->speed == SPEED_10) 1252 ret |= mask; 1253 else 1254 ret &= ~mask; 1255 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret); 1256 } 1257 1258 static int lre_read_master_slave(struct phy_device *phydev) 1259 { 1260 int cfg = MASTER_SLAVE_CFG_UNKNOWN, state; 1261 int val; 1262 1263 /* In BroadR-Reach mode we are always capable of master-slave 1264 * and there is no preferred master or slave configuration 1265 */ 1266 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1267 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1268 1269 val = phy_read(phydev, MII_BCM54XX_LRECR); 1270 if (val < 0) 1271 return val; 1272 1273 if ((val & LRECR_LDSEN) == 0) { 1274 if (val & LRECR_MASTER) 1275 cfg = MASTER_SLAVE_CFG_MASTER_FORCE; 1276 else 1277 cfg = MASTER_SLAVE_CFG_SLAVE_FORCE; 1278 } 1279 1280 val = phy_read(phydev, MII_BCM54XX_LRELDSE); 1281 if (val < 0) 1282 return val; 1283 1284 if (val & LDSE_MASTER) 1285 state = MASTER_SLAVE_STATE_MASTER; 1286 else 1287 state = MASTER_SLAVE_STATE_SLAVE; 1288 1289 phydev->master_slave_get = cfg; 1290 phydev->master_slave_state = state; 1291 1292 return 0; 1293 } 1294 1295 /* Read LDS Link Partner Ability in BroadR-Reach mode */ 1296 static int lre_read_lpa(struct phy_device *phydev) 1297 { 1298 int i, lrelpa; 1299 1300 if (phydev->autoneg != AUTONEG_ENABLE) { 1301 if (!phydev->autoneg_complete) { 1302 /* aneg not yet done, reset all relevant bits */ 1303 for (i = 0; i < ARRAY_SIZE(lds_br_bits); i++) 1304 linkmode_clear_bit(lds_br_bits[i], 1305 phydev->lp_advertising); 1306 1307 return 0; 1308 } 1309 1310 /* Long-Distance Signaling Link Partner Ability */ 1311 lrelpa = phy_read(phydev, MII_BCM54XX_LRELPA); 1312 if (lrelpa < 0) 1313 return lrelpa; 1314 1315 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1316 phydev->lp_advertising, 1317 lrelpa & LRELPA_PAUSE_ASYM); 1318 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1319 phydev->lp_advertising, 1320 lrelpa & LRELPA_PAUSE); 1321 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 1322 phydev->lp_advertising, 1323 lrelpa & LRELPA_100_1PAIR); 1324 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 1325 phydev->lp_advertising, 1326 lrelpa & LRELPA_10_1PAIR); 1327 } else { 1328 linkmode_zero(phydev->lp_advertising); 1329 } 1330 1331 return 0; 1332 } 1333 1334 static int lre_read_status_fixed(struct phy_device *phydev) 1335 { 1336 int lrecr = phy_read(phydev, MII_BCM54XX_LRECR); 1337 1338 if (lrecr < 0) 1339 return lrecr; 1340 1341 phydev->duplex = DUPLEX_FULL; 1342 1343 if (lrecr & LRECR_SPEED100) 1344 phydev->speed = SPEED_100; 1345 else 1346 phydev->speed = SPEED_10; 1347 1348 return 0; 1349 } 1350 1351 /** 1352 * lre_update_link - update link status in @phydev 1353 * @phydev: target phy_device struct 1354 * Return: 0 on success, < 0 on error 1355 * 1356 * Description: Update the value in phydev->link to reflect the 1357 * current link value. In order to do this, we need to read 1358 * the status register twice, keeping the second value. 1359 * This is a genphy_update_link modified to work on LRE registers 1360 * of BroadR-Reach PHY 1361 */ 1362 static int lre_update_link(struct phy_device *phydev) 1363 { 1364 int status = 0, lrecr; 1365 1366 lrecr = phy_read(phydev, MII_BCM54XX_LRECR); 1367 if (lrecr < 0) 1368 return lrecr; 1369 1370 /* Autoneg is being started, therefore disregard BMSR value and 1371 * report link as down. 1372 */ 1373 if (lrecr & BMCR_ANRESTART) 1374 goto done; 1375 1376 /* The link state is latched low so that momentary link 1377 * drops can be detected. Do not double-read the status 1378 * in polling mode to detect such short link drops except 1379 * the link was already down. 1380 */ 1381 if (!phy_polling_mode(phydev) || !phydev->link) { 1382 status = phy_read(phydev, MII_BCM54XX_LRESR); 1383 if (status < 0) 1384 return status; 1385 else if (status & LRESR_LSTATUS) 1386 goto done; 1387 } 1388 1389 /* Read link and autonegotiation status */ 1390 status = phy_read(phydev, MII_BCM54XX_LRESR); 1391 if (status < 0) 1392 return status; 1393 done: 1394 phydev->link = status & LRESR_LSTATUS ? 1 : 0; 1395 phydev->autoneg_complete = status & LRESR_LDSCOMPLETE ? 1 : 0; 1396 1397 /* Consider the case that autoneg was started and "aneg complete" 1398 * bit has been reset, but "link up" bit not yet. 1399 */ 1400 if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete) 1401 phydev->link = 0; 1402 1403 return 0; 1404 } 1405 1406 /* Get the status in BroadRReach mode just like genphy_read_status does 1407 * in normal mode 1408 */ 1409 static int bcm54811_lre_read_status(struct phy_device *phydev) 1410 { 1411 int err, old_link = phydev->link; 1412 1413 /* Update the link, but return if there was an error */ 1414 err = lre_update_link(phydev); 1415 if (err) 1416 return err; 1417 1418 /* why bother the PHY if nothing can have changed */ 1419 if (phydev->autoneg == 1420 AUTONEG_ENABLE && old_link && phydev->link) 1421 return 0; 1422 1423 phydev->speed = SPEED_UNKNOWN; 1424 phydev->duplex = DUPLEX_UNKNOWN; 1425 phydev->pause = 0; 1426 phydev->asym_pause = 0; 1427 1428 err = lre_read_master_slave(phydev); 1429 if (err < 0) 1430 return err; 1431 1432 /* Read LDS Link Partner Ability */ 1433 err = lre_read_lpa(phydev); 1434 if (err < 0) 1435 return err; 1436 1437 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1438 phy_resolve_aneg_linkmode(phydev); 1439 else if (phydev->autoneg == AUTONEG_DISABLE) 1440 err = lre_read_status_fixed(phydev); 1441 1442 return err; 1443 } 1444 1445 static int bcm54811_read_status(struct phy_device *phydev) 1446 { 1447 struct bcm54xx_phy_priv *priv = phydev->priv; 1448 1449 if (priv->brr_mode) 1450 return bcm54811_lre_read_status(phydev); 1451 1452 return genphy_read_status(phydev); 1453 } 1454 1455 static struct phy_driver broadcom_drivers[] = { 1456 { 1457 PHY_ID_MATCH_MODEL(PHY_ID_BCM5411), 1458 .name = "Broadcom BCM5411", 1459 /* PHY_GBIT_FEATURES */ 1460 .get_sset_count = bcm_phy_get_sset_count, 1461 .get_strings = bcm_phy_get_strings, 1462 .get_stats = bcm54xx_get_stats, 1463 .probe = bcm54xx_phy_probe, 1464 .config_init = bcm54xx_config_init, 1465 .config_intr = bcm_phy_config_intr, 1466 .handle_interrupt = bcm_phy_handle_interrupt, 1467 .link_change_notify = bcm54xx_link_change_notify, 1468 }, { 1469 PHY_ID_MATCH_MODEL(PHY_ID_BCM5421), 1470 .name = "Broadcom BCM5421", 1471 /* PHY_GBIT_FEATURES */ 1472 .get_sset_count = bcm_phy_get_sset_count, 1473 .get_strings = bcm_phy_get_strings, 1474 .get_stats = bcm54xx_get_stats, 1475 .probe = bcm54xx_phy_probe, 1476 .config_init = bcm54xx_config_init, 1477 .config_intr = bcm_phy_config_intr, 1478 .handle_interrupt = bcm_phy_handle_interrupt, 1479 .link_change_notify = bcm54xx_link_change_notify, 1480 }, { 1481 PHY_ID_MATCH_MODEL(PHY_ID_BCM54210E), 1482 .name = "Broadcom BCM54210E", 1483 /* PHY_GBIT_FEATURES */ 1484 .flags = PHY_ALWAYS_CALL_SUSPEND, 1485 .get_sset_count = bcm_phy_get_sset_count, 1486 .get_strings = bcm_phy_get_strings, 1487 .get_stats = bcm54xx_get_stats, 1488 .probe = bcm54xx_phy_probe, 1489 .config_init = bcm54xx_config_init, 1490 .config_intr = bcm_phy_config_intr, 1491 .handle_interrupt = bcm_phy_handle_interrupt, 1492 .link_change_notify = bcm54xx_link_change_notify, 1493 .suspend = bcm54xx_suspend, 1494 .resume = bcm54xx_resume, 1495 .get_wol = bcm54xx_phy_get_wol, 1496 .set_wol = bcm54xx_phy_set_wol, 1497 .led_brightness_set = bcm_phy_led_brightness_set, 1498 }, { 1499 PHY_ID_MATCH_MODEL(PHY_ID_BCM5461), 1500 .name = "Broadcom BCM5461", 1501 /* PHY_GBIT_FEATURES */ 1502 .get_sset_count = bcm_phy_get_sset_count, 1503 .get_strings = bcm_phy_get_strings, 1504 .get_stats = bcm54xx_get_stats, 1505 .probe = bcm54xx_phy_probe, 1506 .config_init = bcm54xx_config_init, 1507 .config_intr = bcm_phy_config_intr, 1508 .handle_interrupt = bcm_phy_handle_interrupt, 1509 .link_change_notify = bcm54xx_link_change_notify, 1510 .led_brightness_set = bcm_phy_led_brightness_set, 1511 }, { 1512 PHY_ID_MATCH_MODEL(PHY_ID_BCM54612E), 1513 .name = "Broadcom BCM54612E", 1514 /* PHY_GBIT_FEATURES */ 1515 .get_sset_count = bcm_phy_get_sset_count, 1516 .get_strings = bcm_phy_get_strings, 1517 .get_stats = bcm54xx_get_stats, 1518 .probe = bcm54xx_phy_probe, 1519 .config_init = bcm54xx_config_init, 1520 .config_intr = bcm_phy_config_intr, 1521 .handle_interrupt = bcm_phy_handle_interrupt, 1522 .link_change_notify = bcm54xx_link_change_notify, 1523 .led_brightness_set = bcm_phy_led_brightness_set, 1524 .suspend = bcm54xx_suspend, 1525 .resume = bcm54xx_resume, 1526 }, { 1527 PHY_ID_MATCH_MODEL(PHY_ID_BCM54616S), 1528 .name = "Broadcom BCM54616S", 1529 /* PHY_GBIT_FEATURES */ 1530 .soft_reset = genphy_soft_reset, 1531 .config_init = bcm54xx_config_init, 1532 .config_aneg = bcm54616s_config_aneg, 1533 .config_intr = bcm_phy_config_intr, 1534 .handle_interrupt = bcm_phy_handle_interrupt, 1535 .read_status = bcm54616s_read_status, 1536 .probe = bcm54616s_probe, 1537 .link_change_notify = bcm54xx_link_change_notify, 1538 .led_brightness_set = bcm_phy_led_brightness_set, 1539 }, { 1540 PHY_ID_MATCH_MODEL(PHY_ID_BCM5464), 1541 .name = "Broadcom BCM5464", 1542 /* PHY_GBIT_FEATURES */ 1543 .get_sset_count = bcm_phy_get_sset_count, 1544 .get_strings = bcm_phy_get_strings, 1545 .get_stats = bcm54xx_get_stats, 1546 .probe = bcm54xx_phy_probe, 1547 .config_init = bcm54xx_config_init, 1548 .config_intr = bcm_phy_config_intr, 1549 .handle_interrupt = bcm_phy_handle_interrupt, 1550 .suspend = genphy_suspend, 1551 .resume = genphy_resume, 1552 .link_change_notify = bcm54xx_link_change_notify, 1553 .led_brightness_set = bcm_phy_led_brightness_set, 1554 }, { 1555 PHY_ID_MATCH_MODEL(PHY_ID_BCM5481), 1556 .name = "Broadcom BCM5481", 1557 /* PHY_GBIT_FEATURES */ 1558 .get_sset_count = bcm_phy_get_sset_count, 1559 .get_strings = bcm_phy_get_strings, 1560 .get_stats = bcm54xx_get_stats, 1561 .probe = bcm54xx_phy_probe, 1562 .config_init = bcm54xx_config_init, 1563 .config_aneg = bcm5481_config_aneg, 1564 .config_intr = bcm_phy_config_intr, 1565 .handle_interrupt = bcm_phy_handle_interrupt, 1566 .link_change_notify = bcm54xx_link_change_notify, 1567 .led_brightness_set = bcm_phy_led_brightness_set, 1568 }, { 1569 PHY_ID_MATCH_MODEL(PHY_ID_BCM54810), 1570 .name = "Broadcom BCM54810", 1571 /* PHY_GBIT_FEATURES */ 1572 .get_sset_count = bcm_phy_get_sset_count, 1573 .get_strings = bcm_phy_get_strings, 1574 .get_stats = bcm54xx_get_stats, 1575 .probe = bcm54xx_phy_probe, 1576 .read_mmd = bcm54810_read_mmd, 1577 .write_mmd = bcm54810_write_mmd, 1578 .config_init = bcm54xx_config_init, 1579 .config_aneg = bcm5481_config_aneg, 1580 .config_intr = bcm_phy_config_intr, 1581 .handle_interrupt = bcm_phy_handle_interrupt, 1582 .suspend = bcm54xx_suspend, 1583 .resume = bcm54xx_resume, 1584 .link_change_notify = bcm54xx_link_change_notify, 1585 .led_brightness_set = bcm_phy_led_brightness_set, 1586 }, { 1587 PHY_ID_MATCH_MODEL(PHY_ID_BCM54811), 1588 .name = "Broadcom BCM54811", 1589 /* PHY_GBIT_FEATURES */ 1590 .get_sset_count = bcm_phy_get_sset_count, 1591 .get_strings = bcm_phy_get_strings, 1592 .get_stats = bcm54xx_get_stats, 1593 .probe = bcm54xx_phy_probe, 1594 .config_init = bcm54xx_config_init, 1595 .config_aneg = bcm54811_config_aneg, 1596 .config_intr = bcm_phy_config_intr, 1597 .handle_interrupt = bcm_phy_handle_interrupt, 1598 .read_status = bcm54811_read_status, 1599 .get_features = bcm5481x_read_abilities, 1600 .suspend = bcm54xx_suspend, 1601 .resume = bcm54xx_resume, 1602 .link_change_notify = bcm54xx_link_change_notify, 1603 .led_brightness_set = bcm_phy_led_brightness_set, 1604 }, { 1605 PHY_ID_MATCH_MODEL(PHY_ID_BCM5482), 1606 .name = "Broadcom BCM5482", 1607 /* PHY_GBIT_FEATURES */ 1608 .get_sset_count = bcm_phy_get_sset_count, 1609 .get_strings = bcm_phy_get_strings, 1610 .get_stats = bcm54xx_get_stats, 1611 .probe = bcm54xx_phy_probe, 1612 .config_init = bcm54xx_config_init, 1613 .config_intr = bcm_phy_config_intr, 1614 .handle_interrupt = bcm_phy_handle_interrupt, 1615 .link_change_notify = bcm54xx_link_change_notify, 1616 .led_brightness_set = bcm_phy_led_brightness_set, 1617 }, { 1618 PHY_ID_MATCH_MODEL(PHY_ID_BCM50610), 1619 .name = "Broadcom BCM50610", 1620 /* PHY_GBIT_FEATURES */ 1621 .get_sset_count = bcm_phy_get_sset_count, 1622 .get_strings = bcm_phy_get_strings, 1623 .get_stats = bcm54xx_get_stats, 1624 .probe = bcm54xx_phy_probe, 1625 .config_init = bcm54xx_config_init, 1626 .config_intr = bcm_phy_config_intr, 1627 .handle_interrupt = bcm_phy_handle_interrupt, 1628 .link_change_notify = bcm54xx_link_change_notify, 1629 .suspend = bcm54xx_suspend, 1630 .resume = bcm54xx_resume, 1631 .led_brightness_set = bcm_phy_led_brightness_set, 1632 }, { 1633 PHY_ID_MATCH_MODEL(PHY_ID_BCM50610M), 1634 .name = "Broadcom BCM50610M", 1635 /* PHY_GBIT_FEATURES */ 1636 .get_sset_count = bcm_phy_get_sset_count, 1637 .get_strings = bcm_phy_get_strings, 1638 .get_stats = bcm54xx_get_stats, 1639 .probe = bcm54xx_phy_probe, 1640 .config_init = bcm54xx_config_init, 1641 .config_intr = bcm_phy_config_intr, 1642 .handle_interrupt = bcm_phy_handle_interrupt, 1643 .link_change_notify = bcm54xx_link_change_notify, 1644 .suspend = bcm54xx_suspend, 1645 .resume = bcm54xx_resume, 1646 .led_brightness_set = bcm_phy_led_brightness_set, 1647 }, { 1648 PHY_ID_MATCH_MODEL(PHY_ID_BCM57780), 1649 .name = "Broadcom BCM57780", 1650 /* PHY_GBIT_FEATURES */ 1651 .get_sset_count = bcm_phy_get_sset_count, 1652 .get_strings = bcm_phy_get_strings, 1653 .get_stats = bcm54xx_get_stats, 1654 .probe = bcm54xx_phy_probe, 1655 .config_init = bcm54xx_config_init, 1656 .config_intr = bcm_phy_config_intr, 1657 .handle_interrupt = bcm_phy_handle_interrupt, 1658 .link_change_notify = bcm54xx_link_change_notify, 1659 .led_brightness_set = bcm_phy_led_brightness_set, 1660 }, { 1661 PHY_ID_MATCH_MODEL(PHY_ID_BCMAC131), 1662 .name = "Broadcom BCMAC131", 1663 /* PHY_BASIC_FEATURES */ 1664 .config_init = brcm_fet_config_init, 1665 .config_intr = brcm_fet_config_intr, 1666 .handle_interrupt = brcm_fet_handle_interrupt, 1667 .suspend = brcm_fet_suspend, 1668 .resume = brcm_fet_config_init, 1669 }, { 1670 PHY_ID_MATCH_MODEL(PHY_ID_BCM5241), 1671 .name = "Broadcom BCM5241", 1672 /* PHY_BASIC_FEATURES */ 1673 .config_init = brcm_fet_config_init, 1674 .config_intr = brcm_fet_config_intr, 1675 .handle_interrupt = brcm_fet_handle_interrupt, 1676 .suspend = brcm_fet_suspend, 1677 .resume = brcm_fet_config_init, 1678 }, { 1679 PHY_ID_MATCH_MODEL(PHY_ID_BCM5221), 1680 .name = "Broadcom BCM5221", 1681 /* PHY_BASIC_FEATURES */ 1682 .config_init = brcm_fet_config_init, 1683 .config_intr = brcm_fet_config_intr, 1684 .handle_interrupt = brcm_fet_handle_interrupt, 1685 .suspend = brcm_fet_suspend, 1686 .resume = brcm_fet_config_init, 1687 .config_aneg = bcm5221_config_aneg, 1688 .read_status = bcm5221_read_status, 1689 }, { 1690 PHY_ID_MATCH_MODEL(PHY_ID_BCM5395), 1691 .name = "Broadcom BCM5395", 1692 .flags = PHY_IS_INTERNAL, 1693 /* PHY_GBIT_FEATURES */ 1694 .get_sset_count = bcm_phy_get_sset_count, 1695 .get_strings = bcm_phy_get_strings, 1696 .get_stats = bcm54xx_get_stats, 1697 .probe = bcm54xx_phy_probe, 1698 .link_change_notify = bcm54xx_link_change_notify, 1699 .led_brightness_set = bcm_phy_led_brightness_set, 1700 }, { 1701 PHY_ID_MATCH_MODEL(PHY_ID_BCM53125), 1702 .name = "Broadcom BCM53125", 1703 .flags = PHY_IS_INTERNAL, 1704 /* PHY_GBIT_FEATURES */ 1705 .get_sset_count = bcm_phy_get_sset_count, 1706 .get_strings = bcm_phy_get_strings, 1707 .get_stats = bcm54xx_get_stats, 1708 .probe = bcm54xx_phy_probe, 1709 .config_init = bcm54xx_config_init, 1710 .config_intr = bcm_phy_config_intr, 1711 .handle_interrupt = bcm_phy_handle_interrupt, 1712 .link_change_notify = bcm54xx_link_change_notify, 1713 .led_brightness_set = bcm_phy_led_brightness_set, 1714 }, { 1715 PHY_ID_MATCH_MODEL(PHY_ID_BCM53128), 1716 .name = "Broadcom BCM53128", 1717 .flags = PHY_IS_INTERNAL, 1718 /* PHY_GBIT_FEATURES */ 1719 .get_sset_count = bcm_phy_get_sset_count, 1720 .get_strings = bcm_phy_get_strings, 1721 .get_stats = bcm54xx_get_stats, 1722 .probe = bcm54xx_phy_probe, 1723 .config_init = bcm54xx_config_init, 1724 .config_intr = bcm_phy_config_intr, 1725 .handle_interrupt = bcm_phy_handle_interrupt, 1726 .link_change_notify = bcm54xx_link_change_notify, 1727 .led_brightness_set = bcm_phy_led_brightness_set, 1728 }, { 1729 PHY_ID_MATCH_MODEL(PHY_ID_BCM89610), 1730 .name = "Broadcom BCM89610", 1731 /* PHY_GBIT_FEATURES */ 1732 .get_sset_count = bcm_phy_get_sset_count, 1733 .get_strings = bcm_phy_get_strings, 1734 .get_stats = bcm54xx_get_stats, 1735 .probe = bcm54xx_phy_probe, 1736 .config_init = bcm54xx_config_init, 1737 .config_intr = bcm_phy_config_intr, 1738 .handle_interrupt = bcm_phy_handle_interrupt, 1739 .link_change_notify = bcm54xx_link_change_notify, 1740 } }; 1741 1742 module_phy_driver(broadcom_drivers); 1743 1744 static const struct mdio_device_id __maybe_unused broadcom_tbl[] = { 1745 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5411) }, 1746 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5421) }, 1747 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54210E) }, 1748 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5461) }, 1749 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54612E) }, 1750 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54616S) }, 1751 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5464) }, 1752 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5481) }, 1753 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54810) }, 1754 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54811) }, 1755 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5482) }, 1756 { PHY_ID_MATCH_MODEL(PHY_ID_BCM50610) }, 1757 { PHY_ID_MATCH_MODEL(PHY_ID_BCM50610M) }, 1758 { PHY_ID_MATCH_MODEL(PHY_ID_BCM57780) }, 1759 { PHY_ID_MATCH_MODEL(PHY_ID_BCMAC131) }, 1760 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5221) }, 1761 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5241) }, 1762 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5395) }, 1763 { PHY_ID_MATCH_MODEL(PHY_ID_BCM53125) }, 1764 { PHY_ID_MATCH_MODEL(PHY_ID_BCM53128) }, 1765 { PHY_ID_MATCH_MODEL(PHY_ID_BCM89610) }, 1766 { } 1767 }; 1768 1769 MODULE_DEVICE_TABLE(mdio, broadcom_tbl); 1770