1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/broadcom.c 4 * 5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet 6 * transceivers. 7 * 8 * Broadcom BCM54810, BCM54811 BroadR-Reach transceivers. 9 * 10 * Copyright (c) 2006 Maciej W. Rozycki 11 * 12 * Inspired by code written by Amy Fong. 13 */ 14 15 #include "bcm-phy-lib.h" 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/phy.h> 19 #include <linux/device.h> 20 #include <linux/brcmphy.h> 21 #include <linux/of.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/gpio/consumer.h> 25 26 #define BRCM_PHY_REV(phydev) \ 27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask)) 28 29 MODULE_DESCRIPTION("Broadcom PHY driver"); 30 MODULE_AUTHOR("Maciej W. Rozycki"); 31 MODULE_LICENSE("GPL"); 32 33 struct bcm54xx_phy_priv { 34 u64 *stats; 35 struct bcm_ptp_private *ptp; 36 int wake_irq; 37 bool wake_irq_enabled; 38 bool brr_mode; 39 }; 40 41 /* Link modes for BCM58411 PHY */ 42 static const int bcm54811_linkmodes[] = { 43 ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 44 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 45 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 46 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 47 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 48 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 49 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 50 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 51 ETHTOOL_LINK_MODE_10baseT_Half_BIT 52 }; 53 54 /* Long-Distance Signaling (BroadR-Reach mode aneg) relevant linkmode bits */ 55 static const int lds_br_bits[] = { 56 ETHTOOL_LINK_MODE_Autoneg_BIT, 57 ETHTOOL_LINK_MODE_Pause_BIT, 58 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 59 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 60 ETHTOOL_LINK_MODE_100baseT1_Full_BIT 61 }; 62 63 static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev) 64 { 65 struct bcm54xx_phy_priv *priv = phydev->priv; 66 67 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; 68 } 69 70 static int bcm54xx_config_clock_delay(struct phy_device *phydev) 71 { 72 int rc, val; 73 74 /* handling PHY's internal RX clock delay */ 75 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 76 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 79 /* Disable RGMII RXC-RXD skew */ 80 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 81 } 82 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 83 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 84 /* Enable RGMII RXC-RXD skew */ 85 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 86 } 87 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 88 val); 89 if (rc < 0) 90 return rc; 91 92 /* handling PHY's internal TX clock delay */ 93 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); 94 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 95 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 96 /* Disable internal TX clock delay */ 97 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; 98 } 99 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 100 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 101 /* Enable internal TX clock delay */ 102 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; 103 } 104 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); 105 if (rc < 0) 106 return rc; 107 108 return 0; 109 } 110 111 static int bcm54210e_config_init(struct phy_device *phydev) 112 { 113 int val; 114 115 bcm54xx_config_clock_delay(phydev); 116 117 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { 118 val = phy_read(phydev, MII_CTRL1000); 119 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; 120 phy_write(phydev, MII_CTRL1000, val); 121 } 122 123 return 0; 124 } 125 126 static int bcm54612e_config_init(struct phy_device *phydev) 127 { 128 int reg; 129 130 bcm54xx_config_clock_delay(phydev); 131 132 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 133 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 134 int err; 135 136 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 137 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 138 BCM54612E_LED4_CLK125OUT_EN | reg); 139 140 if (err < 0) 141 return err; 142 } 143 144 return 0; 145 } 146 147 static int bcm54616s_config_init(struct phy_device *phydev) 148 { 149 int rc, val; 150 151 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 152 phydev->interface != PHY_INTERFACE_MODE_1000BASEX) 153 return 0; 154 155 /* Ensure proper interface mode is selected. */ 156 /* Disable RGMII mode */ 157 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 158 if (val < 0) 159 return val; 160 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN; 161 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 162 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 163 val); 164 if (rc < 0) 165 return rc; 166 167 /* Select 1000BASE-X register set (primary SerDes) */ 168 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 169 if (val < 0) 170 return val; 171 val |= BCM54XX_SHD_MODE_1000BX; 172 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 173 if (rc < 0) 174 return rc; 175 176 /* Power down SerDes interface */ 177 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); 178 if (rc < 0) 179 return rc; 180 181 /* Select proper interface mode */ 182 val &= ~BCM54XX_SHD_INTF_SEL_MASK; 183 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ? 184 BCM54XX_SHD_INTF_SEL_SGMII : 185 BCM54XX_SHD_INTF_SEL_GBIC; 186 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 187 if (rc < 0) 188 return rc; 189 190 /* Power up SerDes interface */ 191 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 192 if (rc < 0) 193 return rc; 194 195 /* Select copper register set */ 196 val &= ~BCM54XX_SHD_MODE_1000BX; 197 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 198 if (rc < 0) 199 return rc; 200 201 /* Power up copper interface */ 202 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 203 } 204 205 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */ 206 static int bcm50610_a0_workaround(struct phy_device *phydev) 207 { 208 int err; 209 210 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0, 211 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN | 212 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF); 213 if (err < 0) 214 return err; 215 216 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3, 217 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ); 218 if (err < 0) 219 return err; 220 221 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, 222 MII_BCM54XX_EXP_EXP75_VDACCTRL); 223 if (err < 0) 224 return err; 225 226 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96, 227 MII_BCM54XX_EXP_EXP96_MYST); 228 if (err < 0) 229 return err; 230 231 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97, 232 MII_BCM54XX_EXP_EXP97_MYST); 233 234 return err; 235 } 236 237 static int bcm54xx_phydsp_config(struct phy_device *phydev) 238 { 239 int err, err2; 240 241 /* Enable the SMDSP clock */ 242 err = bcm54xx_auxctl_write(phydev, 243 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 244 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA | 245 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 246 if (err < 0) 247 return err; 248 249 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 250 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) { 251 /* Clear bit 9 to fix a phy interop issue. */ 252 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, 253 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ); 254 if (err < 0) 255 goto error; 256 257 if (phydev->drv->phy_id == PHY_ID_BCM50610) { 258 err = bcm50610_a0_workaround(phydev); 259 if (err < 0) 260 goto error; 261 } 262 } 263 264 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM57780)) { 265 int val; 266 267 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); 268 if (val < 0) 269 goto error; 270 271 val |= MII_BCM54XX_EXP_EXP75_CM_OSC; 272 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); 273 } 274 275 error: 276 /* Disable the SMDSP clock */ 277 err2 = bcm54xx_auxctl_write(phydev, 278 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 279 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 280 281 /* Return the first error reported. */ 282 return err ? err : err2; 283 } 284 285 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) 286 { 287 u32 orig; 288 int val; 289 bool clk125en = true; 290 291 /* Abort if we are using an untested phy. */ 292 if (!(phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM57780) || 293 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 294 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M) || 295 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54210E) || 296 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54810) || 297 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811))) 298 return; 299 300 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); 301 if (val < 0) 302 return; 303 304 orig = val; 305 306 if ((phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 307 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) && 308 BRCM_PHY_REV(phydev) >= 0x3) { 309 /* 310 * Here, bit 0 _disables_ CLK125 when set. 311 * This bit is set by default. 312 */ 313 clk125en = false; 314 } else { 315 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) { 316 if (!phy_id_compare_model(phydev->drv->phy_id, 317 PHY_ID_BCM54811)) { 318 /* Here, bit 0 _enables_ CLK125 when set */ 319 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125; 320 } 321 clk125en = false; 322 } 323 } 324 325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 326 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS; 327 else 328 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; 329 330 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) { 331 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54210E) || 332 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54810) || 333 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811)) 334 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS; 335 else 336 val |= BCM54XX_SHD_SCR3_TRDDAPD; 337 } 338 339 if (orig != val) 340 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); 341 342 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); 343 if (val < 0) 344 return; 345 346 orig = val; 347 348 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 349 val |= BCM54XX_SHD_APD_EN; 350 else 351 val &= ~BCM54XX_SHD_APD_EN; 352 353 if (orig != val) 354 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); 355 } 356 357 static void bcm54xx_ptp_stop(struct phy_device *phydev) 358 { 359 struct bcm54xx_phy_priv *priv = phydev->priv; 360 361 if (priv->ptp) 362 bcm_ptp_stop(priv->ptp); 363 } 364 365 static void bcm54xx_ptp_config_init(struct phy_device *phydev) 366 { 367 struct bcm54xx_phy_priv *priv = phydev->priv; 368 369 if (priv->ptp) 370 bcm_ptp_config_init(phydev); 371 } 372 373 static int bcm5481x_set_brrmode(struct phy_device *phydev, bool on) 374 { 375 int reg; 376 int err; 377 u16 val; 378 379 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 380 381 if (reg < 0) 382 return reg; 383 384 if (on) 385 reg |= BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 386 else 387 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 388 389 err = bcm_phy_write_exp(phydev, 390 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, reg); 391 if (err) 392 return err; 393 394 /* Ensure LRE or IEEE register set is accessed according to the brr 395 * on/off, thus set the override 396 */ 397 val = BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_EN; 398 if (!on) 399 val |= BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_OVERRIDE_VAL; 400 401 return bcm_phy_write_exp(phydev, 402 BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL, val); 403 } 404 405 static int bcm54811_config_init(struct phy_device *phydev) 406 { 407 struct bcm54xx_phy_priv *priv = phydev->priv; 408 int err, reg, exp_sync_ethernet, aux_rgmii_en; 409 410 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 411 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 412 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 413 if (reg < 0) 414 return reg; 415 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 416 BCM54612E_LED4_CLK125OUT_EN | reg); 417 if (err < 0) 418 return err; 419 } 420 421 /* With BCM54811, BroadR-Reach implies no autoneg */ 422 if (priv->brr_mode) 423 phydev->autoneg = 0; 424 425 /* Enable MII Lite (No TXER, RXER, CRS, COL) if configured */ 426 if (phydev->interface == PHY_INTERFACE_MODE_MIILITE) 427 exp_sync_ethernet = BCM_EXP_SYNC_ETHERNET_MII_LITE; 428 else 429 exp_sync_ethernet = 0; 430 431 err = bcm_phy_modify_exp(phydev, BCM_EXP_SYNC_ETHERNET, 432 BCM_EXP_SYNC_ETHERNET_MII_LITE, 433 exp_sync_ethernet); 434 if (err < 0) 435 return err; 436 437 /* Enable RGMII if configured */ 438 if (phy_interface_is_rgmii(phydev)) 439 aux_rgmii_en = MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN | 440 MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 441 else 442 aux_rgmii_en = 0; 443 444 /* Also writing Reserved bits 6:5 because the documentation requires 445 * them to be written to 0b11 446 */ 447 err = bcm54xx_auxctl_write(phydev, 448 MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 449 MII_BCM54XX_AUXCTL_MISC_WREN | 450 aux_rgmii_en | 451 MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RSVD); 452 if (err < 0) 453 return err; 454 455 return bcm5481x_set_brrmode(phydev, priv->brr_mode); 456 } 457 458 static int bcm54xx_config_init(struct phy_device *phydev) 459 { 460 int reg, err, val; 461 462 reg = phy_read(phydev, MII_BCM54XX_ECR); 463 if (reg < 0) 464 return reg; 465 466 /* Mask interrupts globally. */ 467 reg |= MII_BCM54XX_ECR_IM; 468 err = phy_write(phydev, MII_BCM54XX_ECR, reg); 469 if (err < 0) 470 return err; 471 472 /* Unmask events we are interested in. */ 473 reg = ~(MII_BCM54XX_INT_DUPLEX | 474 MII_BCM54XX_INT_SPEED | 475 MII_BCM54XX_INT_LINK); 476 err = phy_write(phydev, MII_BCM54XX_IMR, reg); 477 if (err < 0) 478 return err; 479 480 if ((phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 481 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) && 482 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) 483 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); 484 485 bcm54xx_adjust_rxrefclk(phydev); 486 487 switch (phydev->drv->phy_id & PHY_ID_MATCH_MODEL_MASK) { 488 case PHY_ID_BCM50610: 489 case PHY_ID_BCM50610M: 490 err = bcm54xx_config_clock_delay(phydev); 491 break; 492 case PHY_ID_BCM54210E: 493 err = bcm54210e_config_init(phydev); 494 break; 495 case PHY_ID_BCM54612E: 496 err = bcm54612e_config_init(phydev); 497 break; 498 case PHY_ID_BCM54616S: 499 err = bcm54616s_config_init(phydev); 500 break; 501 case PHY_ID_BCM54810: 502 /* For BCM54810, we need to disable BroadR-Reach function */ 503 val = bcm_phy_read_exp(phydev, 504 BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 505 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 506 err = bcm_phy_write_exp(phydev, 507 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 508 val); 509 break; 510 case PHY_ID_BCM54811: 511 err = bcm54811_config_init(phydev); 512 break; 513 } 514 if (err) 515 return err; 516 517 bcm54xx_phydsp_config(phydev); 518 519 /* For non-SFP setups, encode link speed into LED1 and LED3 pair 520 * (green/amber). 521 * Also flash these two LEDs on activity. This means configuring 522 * them for MULTICOLOR and encoding link/activity into them. 523 * Don't do this for devices on an SFP module, since some of these 524 * use the LED outputs to control the SFP LOS signal, and changing 525 * these settings will cause LOS to malfunction. 526 */ 527 if (!phy_on_sfp(phydev)) { 528 val = BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) | 529 BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1); 530 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val); 531 532 val = BCM_LED_MULTICOLOR_IN_PHASE | 533 BCM54XX_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) | 534 BCM54XX_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT); 535 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); 536 } 537 538 bcm54xx_ptp_config_init(phydev); 539 540 /* Transmit is limited to 4.5 KB without it, see the BCM54210PE 541 * datasheet section 5.4.12.14. 542 */ 543 err = bcm_phy_enable_jumbo(phydev); 544 if (err < 0) 545 return err; 546 547 /* Acknowledge any left over interrupt and charge the device for 548 * wake-up. 549 */ 550 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 551 if (err < 0) 552 return err; 553 554 if (err) 555 pm_wakeup_event(&phydev->mdio.dev, 0); 556 557 return 0; 558 } 559 560 static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable) 561 { 562 int ret = 0; 563 564 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND)) 565 return ret; 566 567 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL); 568 if (ret < 0) 569 goto out; 570 571 if (enable) 572 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP; 573 else 574 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP); 575 576 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret); 577 out: 578 return ret; 579 } 580 581 static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state) 582 { 583 struct bcm54xx_phy_priv *priv = phydev->priv; 584 int ret = 0; 585 586 if (!bcm54xx_phy_can_wakeup(phydev)) 587 return ret; 588 589 if (priv->wake_irq_enabled != state) { 590 if (state) 591 ret = enable_irq_wake(priv->wake_irq); 592 else 593 ret = disable_irq_wake(priv->wake_irq); 594 priv->wake_irq_enabled = state; 595 } 596 597 return ret; 598 } 599 600 static int bcm54xx_suspend(struct phy_device *phydev) 601 { 602 struct bcm54xx_phy_priv *priv = phydev->priv; 603 int ret = 0; 604 605 mutex_lock(&phydev->lock); 606 bcm_phy_update_stats_shadow(phydev, priv->stats); 607 mutex_unlock(&phydev->lock); 608 609 bcm54xx_ptp_stop(phydev); 610 611 /* Acknowledge any Wake-on-LAN interrupt prior to suspend */ 612 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 613 if (ret < 0) 614 return ret; 615 616 if (phydev->wol_enabled) 617 return bcm54xx_set_wakeup_irq(phydev, true); 618 619 /* We cannot use a read/modify/write here otherwise the PHY gets into 620 * a bad state where its LEDs keep flashing, thus defeating the purpose 621 * of low power mode. 622 */ 623 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 624 if (ret < 0) 625 return ret; 626 627 return bcm54xx_iddq_set(phydev, true); 628 } 629 630 static int bcm54xx_resume(struct phy_device *phydev) 631 { 632 int ret = 0; 633 634 if (phydev->wol_enabled) { 635 ret = bcm54xx_set_wakeup_irq(phydev, false); 636 if (ret) 637 return ret; 638 } 639 640 ret = bcm54xx_iddq_set(phydev, false); 641 if (ret < 0) 642 return ret; 643 644 /* Writes to register other than BMCR would be ignored 645 * unless we clear the PDOWN bit first 646 */ 647 ret = genphy_resume(phydev); 648 if (ret < 0) 649 return ret; 650 651 /* Upon exiting power down, the PHY remains in an internal reset state 652 * for 40us 653 */ 654 fsleep(40); 655 656 /* Issue a soft reset after clearing the power down bit 657 * and before doing any other configuration. 658 */ 659 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) { 660 ret = genphy_soft_reset(phydev); 661 if (ret < 0) 662 return ret; 663 } 664 665 return bcm54xx_config_init(phydev); 666 } 667 668 static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 669 { 670 return -EOPNOTSUPP; 671 } 672 673 static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 674 u16 val) 675 { 676 return -EOPNOTSUPP; 677 } 678 679 680 /** 681 * bcm5481x_read_abilities - read PHY abilities from LRESR or Clause 22 682 * (BMSR) registers, based on whether the PHY is in BroadR-Reach or IEEE mode 683 * @phydev: target phy_device struct 684 * 685 * Description: Reads the PHY's abilities and populates phydev->supported 686 * accordingly. The register to read the abilities from is determined by 687 * the brr mode setting of the PHY as read from the device tree. 688 * Note that the LRE and IEEE sets of abilities are disjunct, in other words, 689 * not only the link modes differ, but also the auto-negotiation and 690 * master-slave setup is controlled differently. 691 * 692 * Returns: 0 on success, < 0 on failure 693 */ 694 static int bcm5481x_read_abilities(struct phy_device *phydev) 695 { 696 struct device_node *np = phydev->mdio.dev.of_node; 697 struct bcm54xx_phy_priv *priv = phydev->priv; 698 int i, val, err, aneg; 699 700 for (i = 0; i < ARRAY_SIZE(bcm54811_linkmodes); i++) 701 linkmode_clear_bit(bcm54811_linkmodes[i], phydev->supported); 702 703 priv->brr_mode = of_property_read_bool(np, "brr-mode"); 704 705 /* Set BroadR-Reach mode as configured in the DT. */ 706 err = bcm5481x_set_brrmode(phydev, priv->brr_mode); 707 if (err) 708 return err; 709 710 if (priv->brr_mode) { 711 linkmode_set_bit_array(phy_basic_ports_array, 712 ARRAY_SIZE(phy_basic_ports_array), 713 phydev->supported); 714 715 val = phy_read(phydev, MII_BCM54XX_LRESR); 716 if (val < 0) 717 return val; 718 719 /* BCM54811 is not capable of LDS but the corresponding bit 720 * in LRESR is set to 1 and marked "Ignore" in the datasheet. 721 * So we must read the bcm54811 as unable to auto-negotiate 722 * in BroadR-Reach mode. 723 */ 724 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811)) 725 aneg = 0; 726 else 727 aneg = val & LRESR_LDSABILITY; 728 729 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 730 phydev->supported, 731 aneg); 732 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 733 phydev->supported, 734 val & LRESR_100_1PAIR); 735 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 736 phydev->supported, 737 val & LRESR_10_1PAIR); 738 return 0; 739 } 740 741 return genphy_read_abilities(phydev); 742 } 743 744 static int bcm5481x_config_delay_swap(struct phy_device *phydev) 745 { 746 struct device_node *np = phydev->mdio.dev.of_node; 747 748 /* Set up the delay. */ 749 bcm54xx_config_clock_delay(phydev); 750 751 if (of_property_read_bool(np, "enet-phy-lane-swap")) { 752 /* Lane Swap - Undocumented register...magic! */ 753 int ret = bcm_phy_write_exp(phydev, 754 MII_BCM54XX_EXP_SEL_ER + 0x9, 755 0x11B); 756 if (ret < 0) 757 return ret; 758 } 759 760 return 0; 761 } 762 763 static int bcm5481_config_aneg(struct phy_device *phydev) 764 { 765 struct bcm54xx_phy_priv *priv = phydev->priv; 766 int ret; 767 768 /* Aneg firstly. */ 769 if (priv->brr_mode) 770 ret = bcm_config_lre_aneg(phydev, false); 771 else 772 ret = genphy_config_aneg(phydev); 773 774 if (ret) 775 return ret; 776 777 /* Then we can set up the delay and swap. */ 778 return bcm5481x_config_delay_swap(phydev); 779 } 780 781 static int bcm54811_config_aneg(struct phy_device *phydev) 782 { 783 struct bcm54xx_phy_priv *priv = phydev->priv; 784 int ret; 785 786 /* Aneg firstly. */ 787 if (priv->brr_mode) { 788 /* BCM54811 is only capable of autonegotiation in IEEE mode. 789 * In BroadR-Reach mode, disable the Long Distance Signaling, 790 * the BRR mode autoneg as supported in other Broadcom PHYs. 791 * This bit is marked as "Reserved" and "Default 1, must be 792 * written to 0 after every device reset" in the datasheet. 793 */ 794 ret = phy_modify(phydev, MII_BCM54XX_LRECR, LRECR_LDSEN, 0); 795 if (ret < 0) 796 return ret; 797 ret = bcm_config_lre_aneg(phydev, false); 798 } else { 799 ret = genphy_config_aneg(phydev); 800 } 801 802 if (ret) 803 return ret; 804 805 /* Then we can set up the delay and swap. */ 806 return bcm5481x_config_delay_swap(phydev); 807 } 808 809 struct bcm54616s_phy_priv { 810 bool mode_1000bx_en; 811 }; 812 813 static int bcm54616s_probe(struct phy_device *phydev) 814 { 815 struct bcm54616s_phy_priv *priv; 816 int val; 817 818 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 819 if (!priv) 820 return -ENOMEM; 821 822 phydev->priv = priv; 823 824 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 825 if (val < 0) 826 return val; 827 828 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0] 829 * is 01b, and the link between PHY and its link partner can be 830 * either 1000Base-X or 100Base-FX. 831 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX 832 * support is still missing as of now. 833 */ 834 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) { 835 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL); 836 if (val < 0) 837 return val; 838 839 /* Bit 0 of the SerDes 100-FX Control register, when set 840 * to 1, sets the MII/RGMII -> 100BASE-FX configuration. 841 * When this bit is set to 0, it sets the GMII/RGMII -> 842 * 1000BASE-X configuration. 843 */ 844 if (!(val & BCM54616S_100FX_MODE)) 845 priv->mode_1000bx_en = true; 846 847 phydev->port = PORT_FIBRE; 848 } 849 850 return 0; 851 } 852 853 static int bcm54616s_config_aneg(struct phy_device *phydev) 854 { 855 struct bcm54616s_phy_priv *priv = phydev->priv; 856 int ret; 857 858 /* Aneg firstly. */ 859 if (priv->mode_1000bx_en) 860 ret = genphy_c37_config_aneg(phydev); 861 else 862 ret = genphy_config_aneg(phydev); 863 864 /* Then we can set up the delay. */ 865 bcm54xx_config_clock_delay(phydev); 866 867 return ret; 868 } 869 870 static int bcm54616s_read_status(struct phy_device *phydev) 871 { 872 struct bcm54616s_phy_priv *priv = phydev->priv; 873 bool changed; 874 int err; 875 876 if (priv->mode_1000bx_en) 877 err = genphy_c37_read_status(phydev, &changed); 878 else 879 err = genphy_read_status(phydev); 880 881 return err; 882 } 883 884 static int brcm_fet_config_init(struct phy_device *phydev) 885 { 886 int reg, err, err2, brcmtest; 887 888 /* Reset the PHY to bring it to a known state. */ 889 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 890 if (err < 0) 891 return err; 892 893 /* The datasheet indicates the PHY needs up to 1us to complete a reset, 894 * build some slack here. 895 */ 896 usleep_range(1000, 2000); 897 898 /* The PHY requires 65 MDC clock cycles to complete a write operation 899 * and turnaround the line properly. 900 * 901 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac) 902 * may flag the lack of turn-around as a read failure. This is 903 * particularly true with this combination since the MDIO controller 904 * only used 64 MDC cycles. This is not a critical failure in this 905 * specific case and it has no functional impact otherwise, so we let 906 * that one go through. If there is a genuine bus error, the next read 907 * of MII_BRCM_FET_INTREG will error out. 908 */ 909 err = phy_read(phydev, MII_BMCR); 910 if (err < 0 && err != -EIO) 911 return err; 912 913 /* Read to clear status bits */ 914 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 915 if (reg < 0) 916 return reg; 917 918 /* Unmask events we are interested in and mask interrupts globally. */ 919 if (phydev->drv->phy_id == PHY_ID_BCM5221) 920 reg = MII_BRCM_FET_IR_ENABLE | 921 MII_BRCM_FET_IR_MASK; 922 else 923 reg = MII_BRCM_FET_IR_DUPLEX_EN | 924 MII_BRCM_FET_IR_SPEED_EN | 925 MII_BRCM_FET_IR_LINK_EN | 926 MII_BRCM_FET_IR_ENABLE | 927 MII_BRCM_FET_IR_MASK; 928 929 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 930 if (err < 0) 931 return err; 932 933 /* Enable shadow register access */ 934 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 935 if (brcmtest < 0) 936 return brcmtest; 937 938 reg = brcmtest | MII_BRCM_FET_BT_SRE; 939 940 phy_lock_mdio_bus(phydev); 941 942 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 943 if (err < 0) { 944 phy_unlock_mdio_bus(phydev); 945 return err; 946 } 947 948 if (phydev->drv->phy_id != PHY_ID_BCM5221) { 949 /* Set the LED mode */ 950 reg = __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); 951 if (reg < 0) { 952 err = reg; 953 goto done; 954 } 955 956 err = __phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4, 957 MII_BRCM_FET_SHDW_AM4_LED_MASK, 958 MII_BRCM_FET_SHDW_AM4_LED_MODE1); 959 if (err < 0) 960 goto done; 961 962 /* Enable auto MDIX */ 963 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, 964 MII_BRCM_FET_SHDW_MC_FAME); 965 if (err < 0) 966 goto done; 967 } 968 969 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { 970 /* Enable auto power down */ 971 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, 972 MII_BRCM_FET_SHDW_AS2_APDE); 973 } 974 975 done: 976 /* Disable shadow register access */ 977 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 978 if (!err) 979 err = err2; 980 981 phy_unlock_mdio_bus(phydev); 982 983 return err; 984 } 985 986 static int brcm_fet_ack_interrupt(struct phy_device *phydev) 987 { 988 int reg; 989 990 /* Clear pending interrupts. */ 991 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 992 if (reg < 0) 993 return reg; 994 995 return 0; 996 } 997 998 static int brcm_fet_config_intr(struct phy_device *phydev) 999 { 1000 int reg, err; 1001 1002 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 1003 if (reg < 0) 1004 return reg; 1005 1006 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1007 err = brcm_fet_ack_interrupt(phydev); 1008 if (err) 1009 return err; 1010 1011 reg &= ~MII_BRCM_FET_IR_MASK; 1012 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 1013 } else { 1014 reg |= MII_BRCM_FET_IR_MASK; 1015 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 1016 if (err) 1017 return err; 1018 1019 err = brcm_fet_ack_interrupt(phydev); 1020 } 1021 1022 return err; 1023 } 1024 1025 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev) 1026 { 1027 int irq_status; 1028 1029 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG); 1030 if (irq_status < 0) { 1031 phy_error(phydev); 1032 return IRQ_NONE; 1033 } 1034 1035 if (irq_status == 0) 1036 return IRQ_NONE; 1037 1038 phy_trigger_machine(phydev); 1039 1040 return IRQ_HANDLED; 1041 } 1042 1043 static int brcm_fet_suspend(struct phy_device *phydev) 1044 { 1045 int reg, err, err2, brcmtest; 1046 1047 /* We cannot use a read/modify/write here otherwise the PHY continues 1048 * to drive LEDs which defeats the purpose of low power mode. 1049 */ 1050 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 1051 if (err < 0) 1052 return err; 1053 1054 /* Enable shadow register access */ 1055 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 1056 if (brcmtest < 0) 1057 return brcmtest; 1058 1059 reg = brcmtest | MII_BRCM_FET_BT_SRE; 1060 1061 phy_lock_mdio_bus(phydev); 1062 1063 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 1064 if (err < 0) { 1065 phy_unlock_mdio_bus(phydev); 1066 return err; 1067 } 1068 1069 if (phydev->drv->phy_id == PHY_ID_BCM5221) 1070 /* Force Low Power Mode with clock enabled */ 1071 reg = BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM; 1072 else 1073 /* Set standby mode */ 1074 reg = MII_BRCM_FET_SHDW_AM4_STANDBY; 1075 1076 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); 1077 1078 /* Disable shadow register access */ 1079 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 1080 if (!err) 1081 err = err2; 1082 1083 phy_unlock_mdio_bus(phydev); 1084 1085 return err; 1086 } 1087 1088 static int bcm5221_config_aneg(struct phy_device *phydev) 1089 { 1090 int ret, val; 1091 1092 ret = genphy_config_aneg(phydev); 1093 if (ret) 1094 return ret; 1095 1096 switch (phydev->mdix_ctrl) { 1097 case ETH_TP_MDI: 1098 val = BCM5221_AEGSR_MDIX_DIS; 1099 break; 1100 case ETH_TP_MDI_X: 1101 val = BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP; 1102 break; 1103 case ETH_TP_MDI_AUTO: 1104 val = 0; 1105 break; 1106 default: 1107 return 0; 1108 } 1109 1110 return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP | 1111 BCM5221_AEGSR_MDIX_DIS, 1112 val); 1113 } 1114 1115 static int bcm5221_read_status(struct phy_device *phydev) 1116 { 1117 int ret; 1118 1119 /* Read MDIX status */ 1120 ret = phy_read(phydev, BCM5221_AEGSR); 1121 if (ret < 0) 1122 return ret; 1123 1124 if (ret & BCM5221_AEGSR_MDIX_DIS) { 1125 if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP) 1126 phydev->mdix_ctrl = ETH_TP_MDI_X; 1127 else 1128 phydev->mdix_ctrl = ETH_TP_MDI; 1129 } else { 1130 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1131 } 1132 1133 if (ret & BCM5221_AEGSR_MDIX_STATUS) 1134 phydev->mdix = ETH_TP_MDI_X; 1135 else 1136 phydev->mdix = ETH_TP_MDI; 1137 1138 return genphy_read_status(phydev); 1139 } 1140 1141 static void bcm54xx_phy_get_wol(struct phy_device *phydev, 1142 struct ethtool_wolinfo *wol) 1143 { 1144 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 1145 * or an out of band GPIO descriptor for wake-up. Zeroing 1146 * wol->supported allows the caller (MAC driver) to play through and 1147 * offer its own Wake-on-LAN scheme if available. 1148 */ 1149 if (!bcm54xx_phy_can_wakeup(phydev)) { 1150 wol->supported = 0; 1151 return; 1152 } 1153 1154 bcm_phy_get_wol(phydev, wol); 1155 } 1156 1157 static int bcm54xx_phy_set_wol(struct phy_device *phydev, 1158 struct ethtool_wolinfo *wol) 1159 { 1160 int ret; 1161 1162 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 1163 * or an out of band GPIO descriptor for wake-up. Returning -EOPNOTSUPP 1164 * allows the caller (MAC driver) to play through and offer its own 1165 * Wake-on-LAN scheme if available. 1166 */ 1167 if (!bcm54xx_phy_can_wakeup(phydev)) 1168 return -EOPNOTSUPP; 1169 1170 ret = bcm_phy_set_wol(phydev, wol); 1171 if (ret < 0) 1172 return ret; 1173 1174 return 0; 1175 } 1176 1177 static int bcm54xx_phy_probe(struct phy_device *phydev) 1178 { 1179 struct bcm54xx_phy_priv *priv; 1180 struct gpio_desc *wakeup_gpio; 1181 int ret = 0; 1182 1183 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1184 if (!priv) 1185 return -ENOMEM; 1186 1187 priv->wake_irq = -ENXIO; 1188 1189 phydev->priv = priv; 1190 1191 priv->stats = devm_kcalloc(&phydev->mdio.dev, 1192 bcm_phy_get_sset_count(phydev), sizeof(u64), 1193 GFP_KERNEL); 1194 if (!priv->stats) 1195 return -ENOMEM; 1196 1197 priv->ptp = bcm_ptp_probe(phydev); 1198 if (IS_ERR(priv->ptp)) 1199 return PTR_ERR(priv->ptp); 1200 1201 /* We cannot utilize the _optional variant here since we want to know 1202 * whether the GPIO descriptor exists or not to advertise Wake-on-LAN 1203 * support or not. 1204 */ 1205 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN); 1206 if (PTR_ERR(wakeup_gpio) == -EPROBE_DEFER) 1207 return PTR_ERR(wakeup_gpio); 1208 1209 if (!IS_ERR(wakeup_gpio)) { 1210 priv->wake_irq = gpiod_to_irq(wakeup_gpio); 1211 1212 /* Dummy interrupt handler which is not enabled but is provided 1213 * in order for the interrupt descriptor to be fully set-up. 1214 */ 1215 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq, 1216 bcm_phy_wol_isr, 1217 IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN, 1218 dev_name(&phydev->mdio.dev), phydev); 1219 if (ret) 1220 return ret; 1221 } 1222 1223 /* If we do not have a main interrupt or a side-band wake-up interrupt, 1224 * then the device cannot be marked as wake-up capable. 1225 */ 1226 if (!bcm54xx_phy_can_wakeup(phydev)) 1227 return 0; 1228 1229 return device_init_wakeup(&phydev->mdio.dev, true); 1230 } 1231 1232 static void bcm54xx_get_stats(struct phy_device *phydev, 1233 struct ethtool_stats *stats, u64 *data) 1234 { 1235 struct bcm54xx_phy_priv *priv = phydev->priv; 1236 1237 bcm_phy_get_stats(phydev, priv->stats, stats, data); 1238 } 1239 1240 static void bcm54xx_link_change_notify(struct phy_device *phydev) 1241 { 1242 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE | 1243 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE; 1244 int ret; 1245 1246 if (phydev->state != PHY_RUNNING) 1247 return; 1248 1249 /* Don't change the DAC wake settings if auto power down 1250 * is not requested. 1251 */ 1252 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 1253 return; 1254 1255 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08); 1256 if (ret < 0) 1257 return; 1258 1259 /* Enable/disable 10BaseT auto and forced early DAC wake depending 1260 * on the negotiated speed, those settings should only be done 1261 * for 10Mbits/sec. 1262 */ 1263 if (phydev->speed == SPEED_10) 1264 ret |= mask; 1265 else 1266 ret &= ~mask; 1267 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret); 1268 } 1269 1270 static int lre_read_master_slave(struct phy_device *phydev) 1271 { 1272 int cfg = MASTER_SLAVE_CFG_UNKNOWN, state; 1273 int val; 1274 1275 /* In BroadR-Reach mode we are always capable of master-slave 1276 * and there is no preferred master or slave configuration 1277 */ 1278 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1279 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1280 1281 val = phy_read(phydev, MII_BCM54XX_LRECR); 1282 if (val < 0) 1283 return val; 1284 1285 if ((val & LRECR_LDSEN) == 0) { 1286 if (val & LRECR_MASTER) 1287 cfg = MASTER_SLAVE_CFG_MASTER_FORCE; 1288 else 1289 cfg = MASTER_SLAVE_CFG_SLAVE_FORCE; 1290 } 1291 1292 val = phy_read(phydev, MII_BCM54XX_LRELDSE); 1293 if (val < 0) 1294 return val; 1295 1296 if (val & LDSE_MASTER) 1297 state = MASTER_SLAVE_STATE_MASTER; 1298 else 1299 state = MASTER_SLAVE_STATE_SLAVE; 1300 1301 phydev->master_slave_get = cfg; 1302 phydev->master_slave_state = state; 1303 1304 return 0; 1305 } 1306 1307 /* Read LDS Link Partner Ability in BroadR-Reach mode */ 1308 static int lre_read_lpa(struct phy_device *phydev) 1309 { 1310 int i, lrelpa; 1311 1312 if (phydev->autoneg != AUTONEG_ENABLE) { 1313 if (!phydev->autoneg_complete) { 1314 /* aneg not yet done, reset all relevant bits */ 1315 for (i = 0; i < ARRAY_SIZE(lds_br_bits); i++) 1316 linkmode_clear_bit(lds_br_bits[i], 1317 phydev->lp_advertising); 1318 1319 return 0; 1320 } 1321 1322 /* Long-Distance Signaling Link Partner Ability */ 1323 lrelpa = phy_read(phydev, MII_BCM54XX_LRELPA); 1324 if (lrelpa < 0) 1325 return lrelpa; 1326 1327 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1328 phydev->lp_advertising, 1329 lrelpa & LRELPA_PAUSE_ASYM); 1330 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1331 phydev->lp_advertising, 1332 lrelpa & LRELPA_PAUSE); 1333 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 1334 phydev->lp_advertising, 1335 lrelpa & LRELPA_100_1PAIR); 1336 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 1337 phydev->lp_advertising, 1338 lrelpa & LRELPA_10_1PAIR); 1339 } else { 1340 linkmode_zero(phydev->lp_advertising); 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int lre_read_status_fixed(struct phy_device *phydev) 1347 { 1348 int lrecr = phy_read(phydev, MII_BCM54XX_LRECR); 1349 1350 if (lrecr < 0) 1351 return lrecr; 1352 1353 phydev->duplex = DUPLEX_FULL; 1354 1355 if (lrecr & LRECR_SPEED100) 1356 phydev->speed = SPEED_100; 1357 else 1358 phydev->speed = SPEED_10; 1359 1360 return 0; 1361 } 1362 1363 /** 1364 * lre_update_link - update link status in @phydev 1365 * @phydev: target phy_device struct 1366 * Return: 0 on success, < 0 on error 1367 * 1368 * Description: Update the value in phydev->link to reflect the 1369 * current link value. In order to do this, we need to read 1370 * the status register twice, keeping the second value. 1371 * This is a genphy_update_link modified to work on LRE registers 1372 * of BroadR-Reach PHY 1373 */ 1374 static int lre_update_link(struct phy_device *phydev) 1375 { 1376 int status = 0, lrecr; 1377 1378 lrecr = phy_read(phydev, MII_BCM54XX_LRECR); 1379 if (lrecr < 0) 1380 return lrecr; 1381 1382 /* Autoneg is being started, therefore disregard BMSR value and 1383 * report link as down. 1384 */ 1385 if (lrecr & BMCR_ANRESTART) 1386 goto done; 1387 1388 /* The link state is latched low so that momentary link 1389 * drops can be detected. Do not double-read the status 1390 * in polling mode to detect such short link drops except 1391 * the link was already down. 1392 */ 1393 if (!phy_polling_mode(phydev) || !phydev->link) { 1394 status = phy_read(phydev, MII_BCM54XX_LRESR); 1395 if (status < 0) 1396 return status; 1397 else if (status & LRESR_LSTATUS) 1398 goto done; 1399 } 1400 1401 /* Read link and autonegotiation status */ 1402 status = phy_read(phydev, MII_BCM54XX_LRESR); 1403 if (status < 0) 1404 return status; 1405 done: 1406 phydev->link = status & LRESR_LSTATUS ? 1 : 0; 1407 phydev->autoneg_complete = status & LRESR_LDSCOMPLETE ? 1 : 0; 1408 1409 /* Consider the case that autoneg was started and "aneg complete" 1410 * bit has been reset, but "link up" bit not yet. 1411 */ 1412 if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete) 1413 phydev->link = 0; 1414 1415 return 0; 1416 } 1417 1418 /* Get the status in BroadRReach mode just like genphy_read_status does 1419 * in normal mode 1420 */ 1421 static int bcm54811_lre_read_status(struct phy_device *phydev) 1422 { 1423 int err, old_link = phydev->link; 1424 1425 /* Update the link, but return if there was an error */ 1426 err = lre_update_link(phydev); 1427 if (err) 1428 return err; 1429 1430 /* why bother the PHY if nothing can have changed */ 1431 if (phydev->autoneg == 1432 AUTONEG_ENABLE && old_link && phydev->link) 1433 return 0; 1434 1435 phydev->speed = SPEED_UNKNOWN; 1436 phydev->duplex = DUPLEX_UNKNOWN; 1437 phydev->pause = 0; 1438 phydev->asym_pause = 0; 1439 1440 err = lre_read_master_slave(phydev); 1441 if (err < 0) 1442 return err; 1443 1444 /* Read LDS Link Partner Ability */ 1445 err = lre_read_lpa(phydev); 1446 if (err < 0) 1447 return err; 1448 1449 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1450 phy_resolve_aneg_linkmode(phydev); 1451 else if (phydev->autoneg == AUTONEG_DISABLE) 1452 err = lre_read_status_fixed(phydev); 1453 1454 return err; 1455 } 1456 1457 static int bcm54811_read_status(struct phy_device *phydev) 1458 { 1459 struct bcm54xx_phy_priv *priv = phydev->priv; 1460 1461 if (priv->brr_mode) 1462 return bcm54811_lre_read_status(phydev); 1463 1464 return genphy_read_status(phydev); 1465 } 1466 1467 static int bcm54xx_disable_autonomous_eee(struct phy_device *phydev) 1468 { 1469 return bcm_phy_modify_exp(phydev, BCM54XX_TOP_MISC_MII_BUF_CNTL0, 1470 BCM54XX_MII_BUF_CNTL0_AUTOGREEEN_EN, 0); 1471 } 1472 1473 static struct phy_driver broadcom_drivers[] = { 1474 { 1475 PHY_ID_MATCH_MODEL(PHY_ID_BCM5411), 1476 .name = "Broadcom BCM5411", 1477 /* PHY_GBIT_FEATURES */ 1478 .get_sset_count = bcm_phy_get_sset_count, 1479 .get_strings = bcm_phy_get_strings, 1480 .get_stats = bcm54xx_get_stats, 1481 .probe = bcm54xx_phy_probe, 1482 .config_init = bcm54xx_config_init, 1483 .config_intr = bcm_phy_config_intr, 1484 .handle_interrupt = bcm_phy_handle_interrupt, 1485 .link_change_notify = bcm54xx_link_change_notify, 1486 }, { 1487 PHY_ID_MATCH_MODEL(PHY_ID_BCM5421), 1488 .name = "Broadcom BCM5421", 1489 /* PHY_GBIT_FEATURES */ 1490 .get_sset_count = bcm_phy_get_sset_count, 1491 .get_strings = bcm_phy_get_strings, 1492 .get_stats = bcm54xx_get_stats, 1493 .probe = bcm54xx_phy_probe, 1494 .config_init = bcm54xx_config_init, 1495 .config_intr = bcm_phy_config_intr, 1496 .handle_interrupt = bcm_phy_handle_interrupt, 1497 .link_change_notify = bcm54xx_link_change_notify, 1498 }, { 1499 PHY_ID_MATCH_MODEL(PHY_ID_BCM54210E), 1500 .name = "Broadcom BCM54210E", 1501 /* PHY_GBIT_FEATURES */ 1502 .flags = PHY_ALWAYS_CALL_SUSPEND, 1503 .get_sset_count = bcm_phy_get_sset_count, 1504 .get_strings = bcm_phy_get_strings, 1505 .get_stats = bcm54xx_get_stats, 1506 .probe = bcm54xx_phy_probe, 1507 .config_init = bcm54xx_config_init, 1508 .config_intr = bcm_phy_config_intr, 1509 .handle_interrupt = bcm_phy_handle_interrupt, 1510 .link_change_notify = bcm54xx_link_change_notify, 1511 .suspend = bcm54xx_suspend, 1512 .resume = bcm54xx_resume, 1513 .get_wol = bcm54xx_phy_get_wol, 1514 .set_wol = bcm54xx_phy_set_wol, 1515 .led_brightness_set = bcm_phy_led_brightness_set, 1516 .disable_autonomous_eee = bcm54xx_disable_autonomous_eee, 1517 }, { 1518 PHY_ID_MATCH_MODEL(PHY_ID_BCM5461), 1519 .name = "Broadcom BCM5461", 1520 /* PHY_GBIT_FEATURES */ 1521 .get_sset_count = bcm_phy_get_sset_count, 1522 .get_strings = bcm_phy_get_strings, 1523 .get_stats = bcm54xx_get_stats, 1524 .probe = bcm54xx_phy_probe, 1525 .config_init = bcm54xx_config_init, 1526 .config_intr = bcm_phy_config_intr, 1527 .handle_interrupt = bcm_phy_handle_interrupt, 1528 .link_change_notify = bcm54xx_link_change_notify, 1529 .led_brightness_set = bcm_phy_led_brightness_set, 1530 }, { 1531 PHY_ID_MATCH_MODEL(PHY_ID_BCM54612E), 1532 .name = "Broadcom BCM54612E", 1533 /* PHY_GBIT_FEATURES */ 1534 .get_sset_count = bcm_phy_get_sset_count, 1535 .get_strings = bcm_phy_get_strings, 1536 .get_stats = bcm54xx_get_stats, 1537 .probe = bcm54xx_phy_probe, 1538 .config_init = bcm54xx_config_init, 1539 .config_intr = bcm_phy_config_intr, 1540 .handle_interrupt = bcm_phy_handle_interrupt, 1541 .link_change_notify = bcm54xx_link_change_notify, 1542 .led_brightness_set = bcm_phy_led_brightness_set, 1543 .suspend = bcm54xx_suspend, 1544 .resume = bcm54xx_resume, 1545 }, { 1546 PHY_ID_MATCH_MODEL(PHY_ID_BCM54616S), 1547 .name = "Broadcom BCM54616S", 1548 /* PHY_GBIT_FEATURES */ 1549 .soft_reset = genphy_soft_reset, 1550 .config_init = bcm54xx_config_init, 1551 .config_aneg = bcm54616s_config_aneg, 1552 .config_intr = bcm_phy_config_intr, 1553 .handle_interrupt = bcm_phy_handle_interrupt, 1554 .read_status = bcm54616s_read_status, 1555 .probe = bcm54616s_probe, 1556 .link_change_notify = bcm54xx_link_change_notify, 1557 .led_brightness_set = bcm_phy_led_brightness_set, 1558 }, { 1559 PHY_ID_MATCH_MODEL(PHY_ID_BCM5464), 1560 .name = "Broadcom BCM5464", 1561 /* PHY_GBIT_FEATURES */ 1562 .get_sset_count = bcm_phy_get_sset_count, 1563 .get_strings = bcm_phy_get_strings, 1564 .get_stats = bcm54xx_get_stats, 1565 .probe = bcm54xx_phy_probe, 1566 .config_init = bcm54xx_config_init, 1567 .config_intr = bcm_phy_config_intr, 1568 .handle_interrupt = bcm_phy_handle_interrupt, 1569 .suspend = genphy_suspend, 1570 .resume = genphy_resume, 1571 .link_change_notify = bcm54xx_link_change_notify, 1572 .led_brightness_set = bcm_phy_led_brightness_set, 1573 }, { 1574 PHY_ID_MATCH_MODEL(PHY_ID_BCM5481), 1575 .name = "Broadcom BCM5481", 1576 /* PHY_GBIT_FEATURES */ 1577 .get_sset_count = bcm_phy_get_sset_count, 1578 .get_strings = bcm_phy_get_strings, 1579 .get_stats = bcm54xx_get_stats, 1580 .probe = bcm54xx_phy_probe, 1581 .config_init = bcm54xx_config_init, 1582 .config_aneg = bcm5481_config_aneg, 1583 .config_intr = bcm_phy_config_intr, 1584 .handle_interrupt = bcm_phy_handle_interrupt, 1585 .link_change_notify = bcm54xx_link_change_notify, 1586 .led_brightness_set = bcm_phy_led_brightness_set, 1587 }, { 1588 PHY_ID_MATCH_MODEL(PHY_ID_BCM54810), 1589 .name = "Broadcom BCM54810", 1590 /* PHY_GBIT_FEATURES */ 1591 .get_sset_count = bcm_phy_get_sset_count, 1592 .get_strings = bcm_phy_get_strings, 1593 .get_stats = bcm54xx_get_stats, 1594 .probe = bcm54xx_phy_probe, 1595 .read_mmd = bcm54810_read_mmd, 1596 .write_mmd = bcm54810_write_mmd, 1597 .config_init = bcm54xx_config_init, 1598 .config_aneg = bcm5481_config_aneg, 1599 .config_intr = bcm_phy_config_intr, 1600 .handle_interrupt = bcm_phy_handle_interrupt, 1601 .suspend = bcm54xx_suspend, 1602 .resume = bcm54xx_resume, 1603 .link_change_notify = bcm54xx_link_change_notify, 1604 .led_brightness_set = bcm_phy_led_brightness_set, 1605 }, { 1606 PHY_ID_MATCH_MODEL(PHY_ID_BCM54811), 1607 .name = "Broadcom BCM54811", 1608 /* PHY_GBIT_FEATURES */ 1609 .get_sset_count = bcm_phy_get_sset_count, 1610 .get_strings = bcm_phy_get_strings, 1611 .get_stats = bcm54xx_get_stats, 1612 .probe = bcm54xx_phy_probe, 1613 .config_init = bcm54xx_config_init, 1614 .config_aneg = bcm54811_config_aneg, 1615 .config_intr = bcm_phy_config_intr, 1616 .handle_interrupt = bcm_phy_handle_interrupt, 1617 .read_status = bcm54811_read_status, 1618 .get_features = bcm5481x_read_abilities, 1619 .suspend = bcm54xx_suspend, 1620 .resume = bcm54xx_resume, 1621 .link_change_notify = bcm54xx_link_change_notify, 1622 .led_brightness_set = bcm_phy_led_brightness_set, 1623 }, { 1624 PHY_ID_MATCH_MODEL(PHY_ID_BCM5482), 1625 .name = "Broadcom BCM5482", 1626 /* PHY_GBIT_FEATURES */ 1627 .get_sset_count = bcm_phy_get_sset_count, 1628 .get_strings = bcm_phy_get_strings, 1629 .get_stats = bcm54xx_get_stats, 1630 .probe = bcm54xx_phy_probe, 1631 .config_init = bcm54xx_config_init, 1632 .config_intr = bcm_phy_config_intr, 1633 .handle_interrupt = bcm_phy_handle_interrupt, 1634 .link_change_notify = bcm54xx_link_change_notify, 1635 .led_brightness_set = bcm_phy_led_brightness_set, 1636 }, { 1637 PHY_ID_MATCH_MODEL(PHY_ID_BCM50610), 1638 .name = "Broadcom BCM50610", 1639 /* PHY_GBIT_FEATURES */ 1640 .get_sset_count = bcm_phy_get_sset_count, 1641 .get_strings = bcm_phy_get_strings, 1642 .get_stats = bcm54xx_get_stats, 1643 .probe = bcm54xx_phy_probe, 1644 .config_init = bcm54xx_config_init, 1645 .config_intr = bcm_phy_config_intr, 1646 .handle_interrupt = bcm_phy_handle_interrupt, 1647 .link_change_notify = bcm54xx_link_change_notify, 1648 .suspend = bcm54xx_suspend, 1649 .resume = bcm54xx_resume, 1650 .led_brightness_set = bcm_phy_led_brightness_set, 1651 }, { 1652 PHY_ID_MATCH_MODEL(PHY_ID_BCM50610M), 1653 .name = "Broadcom BCM50610M", 1654 /* PHY_GBIT_FEATURES */ 1655 .get_sset_count = bcm_phy_get_sset_count, 1656 .get_strings = bcm_phy_get_strings, 1657 .get_stats = bcm54xx_get_stats, 1658 .probe = bcm54xx_phy_probe, 1659 .config_init = bcm54xx_config_init, 1660 .config_intr = bcm_phy_config_intr, 1661 .handle_interrupt = bcm_phy_handle_interrupt, 1662 .link_change_notify = bcm54xx_link_change_notify, 1663 .suspend = bcm54xx_suspend, 1664 .resume = bcm54xx_resume, 1665 .led_brightness_set = bcm_phy_led_brightness_set, 1666 }, { 1667 PHY_ID_MATCH_MODEL(PHY_ID_BCM57780), 1668 .name = "Broadcom BCM57780", 1669 /* PHY_GBIT_FEATURES */ 1670 .get_sset_count = bcm_phy_get_sset_count, 1671 .get_strings = bcm_phy_get_strings, 1672 .get_stats = bcm54xx_get_stats, 1673 .probe = bcm54xx_phy_probe, 1674 .config_init = bcm54xx_config_init, 1675 .config_intr = bcm_phy_config_intr, 1676 .handle_interrupt = bcm_phy_handle_interrupt, 1677 .link_change_notify = bcm54xx_link_change_notify, 1678 .led_brightness_set = bcm_phy_led_brightness_set, 1679 }, { 1680 PHY_ID_MATCH_MODEL(PHY_ID_BCMAC131), 1681 .name = "Broadcom BCMAC131", 1682 /* PHY_BASIC_FEATURES */ 1683 .config_init = brcm_fet_config_init, 1684 .config_intr = brcm_fet_config_intr, 1685 .handle_interrupt = brcm_fet_handle_interrupt, 1686 .suspend = brcm_fet_suspend, 1687 .resume = brcm_fet_config_init, 1688 }, { 1689 PHY_ID_MATCH_MODEL(PHY_ID_BCM5241), 1690 .name = "Broadcom BCM5241", 1691 /* PHY_BASIC_FEATURES */ 1692 .config_init = brcm_fet_config_init, 1693 .config_intr = brcm_fet_config_intr, 1694 .handle_interrupt = brcm_fet_handle_interrupt, 1695 .suspend = brcm_fet_suspend, 1696 .resume = brcm_fet_config_init, 1697 }, { 1698 PHY_ID_MATCH_MODEL(PHY_ID_BCM5221), 1699 .name = "Broadcom BCM5221", 1700 /* PHY_BASIC_FEATURES */ 1701 .config_init = brcm_fet_config_init, 1702 .config_intr = brcm_fet_config_intr, 1703 .handle_interrupt = brcm_fet_handle_interrupt, 1704 .suspend = brcm_fet_suspend, 1705 .resume = brcm_fet_config_init, 1706 .config_aneg = bcm5221_config_aneg, 1707 .read_status = bcm5221_read_status, 1708 }, { 1709 PHY_ID_MATCH_MODEL(PHY_ID_BCM5395), 1710 .name = "Broadcom BCM5395", 1711 .flags = PHY_IS_INTERNAL, 1712 /* PHY_GBIT_FEATURES */ 1713 .get_sset_count = bcm_phy_get_sset_count, 1714 .get_strings = bcm_phy_get_strings, 1715 .get_stats = bcm54xx_get_stats, 1716 .probe = bcm54xx_phy_probe, 1717 .link_change_notify = bcm54xx_link_change_notify, 1718 .led_brightness_set = bcm_phy_led_brightness_set, 1719 }, { 1720 PHY_ID_MATCH_MODEL(PHY_ID_BCM53125), 1721 .name = "Broadcom BCM53125", 1722 .flags = PHY_IS_INTERNAL, 1723 /* PHY_GBIT_FEATURES */ 1724 .get_sset_count = bcm_phy_get_sset_count, 1725 .get_strings = bcm_phy_get_strings, 1726 .get_stats = bcm54xx_get_stats, 1727 .probe = bcm54xx_phy_probe, 1728 .config_init = bcm54xx_config_init, 1729 .config_intr = bcm_phy_config_intr, 1730 .handle_interrupt = bcm_phy_handle_interrupt, 1731 .link_change_notify = bcm54xx_link_change_notify, 1732 .led_brightness_set = bcm_phy_led_brightness_set, 1733 }, { 1734 PHY_ID_MATCH_MODEL(PHY_ID_BCM53128), 1735 .name = "Broadcom BCM53128", 1736 .flags = PHY_IS_INTERNAL, 1737 /* PHY_GBIT_FEATURES */ 1738 .get_sset_count = bcm_phy_get_sset_count, 1739 .get_strings = bcm_phy_get_strings, 1740 .get_stats = bcm54xx_get_stats, 1741 .probe = bcm54xx_phy_probe, 1742 .config_init = bcm54xx_config_init, 1743 .config_intr = bcm_phy_config_intr, 1744 .handle_interrupt = bcm_phy_handle_interrupt, 1745 .link_change_notify = bcm54xx_link_change_notify, 1746 .led_brightness_set = bcm_phy_led_brightness_set, 1747 }, { 1748 PHY_ID_MATCH_MODEL(PHY_ID_BCM89610), 1749 .name = "Broadcom BCM89610", 1750 /* PHY_GBIT_FEATURES */ 1751 .get_sset_count = bcm_phy_get_sset_count, 1752 .get_strings = bcm_phy_get_strings, 1753 .get_stats = bcm54xx_get_stats, 1754 .probe = bcm54xx_phy_probe, 1755 .config_init = bcm54xx_config_init, 1756 .config_intr = bcm_phy_config_intr, 1757 .handle_interrupt = bcm_phy_handle_interrupt, 1758 .link_change_notify = bcm54xx_link_change_notify, 1759 } }; 1760 1761 module_phy_driver(broadcom_drivers); 1762 1763 static const struct mdio_device_id __maybe_unused broadcom_tbl[] = { 1764 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5411) }, 1765 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5421) }, 1766 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54210E) }, 1767 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5461) }, 1768 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54612E) }, 1769 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54616S) }, 1770 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5464) }, 1771 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5481) }, 1772 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54810) }, 1773 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54811) }, 1774 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5482) }, 1775 { PHY_ID_MATCH_MODEL(PHY_ID_BCM50610) }, 1776 { PHY_ID_MATCH_MODEL(PHY_ID_BCM50610M) }, 1777 { PHY_ID_MATCH_MODEL(PHY_ID_BCM57780) }, 1778 { PHY_ID_MATCH_MODEL(PHY_ID_BCMAC131) }, 1779 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5221) }, 1780 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5241) }, 1781 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5395) }, 1782 { PHY_ID_MATCH_MODEL(PHY_ID_BCM53125) }, 1783 { PHY_ID_MATCH_MODEL(PHY_ID_BCM53128) }, 1784 { PHY_ID_MATCH_MODEL(PHY_ID_BCM89610) }, 1785 { } 1786 }; 1787 1788 MODULE_DEVICE_TABLE(mdio, broadcom_tbl); 1789