1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/broadcom.c 4 * 5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet 6 * transceivers. 7 * 8 * Broadcom BCM54810, BCM54811 BroadR-Reach transceivers. 9 * 10 * Copyright (c) 2006 Maciej W. Rozycki 11 * 12 * Inspired by code written by Amy Fong. 13 */ 14 15 #include "bcm-phy-lib.h" 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/phy.h> 19 #include <linux/device.h> 20 #include <linux/brcmphy.h> 21 #include <linux/of.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/gpio/consumer.h> 25 26 #define BRCM_PHY_REV(phydev) \ 27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask)) 28 29 MODULE_DESCRIPTION("Broadcom PHY driver"); 30 MODULE_AUTHOR("Maciej W. Rozycki"); 31 MODULE_LICENSE("GPL"); 32 33 struct bcm54xx_phy_priv { 34 u64 *stats; 35 struct bcm_ptp_private *ptp; 36 int wake_irq; 37 bool wake_irq_enabled; 38 bool brr_mode; 39 }; 40 41 /* Link modes for BCM58411 PHY */ 42 static const int bcm54811_linkmodes[] = { 43 ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 44 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 45 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 46 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 47 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 48 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 49 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 50 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 51 ETHTOOL_LINK_MODE_10baseT_Half_BIT 52 }; 53 54 /* Long-Distance Signaling (BroadR-Reach mode aneg) relevant linkmode bits */ 55 static const int lds_br_bits[] = { 56 ETHTOOL_LINK_MODE_Autoneg_BIT, 57 ETHTOOL_LINK_MODE_Pause_BIT, 58 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 59 ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 60 ETHTOOL_LINK_MODE_100baseT1_Full_BIT 61 }; 62 63 static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev) 64 { 65 struct bcm54xx_phy_priv *priv = phydev->priv; 66 67 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; 68 } 69 70 static int bcm54xx_config_clock_delay(struct phy_device *phydev) 71 { 72 int rc, val; 73 74 /* handling PHY's internal RX clock delay */ 75 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 76 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 79 /* Disable RGMII RXC-RXD skew */ 80 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 81 } 82 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 83 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 84 /* Enable RGMII RXC-RXD skew */ 85 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 86 } 87 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 88 val); 89 if (rc < 0) 90 return rc; 91 92 /* handling PHY's internal TX clock delay */ 93 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); 94 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 95 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 96 /* Disable internal TX clock delay */ 97 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; 98 } 99 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 100 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 101 /* Enable internal TX clock delay */ 102 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; 103 } 104 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); 105 if (rc < 0) 106 return rc; 107 108 return 0; 109 } 110 111 static int bcm54210e_config_init(struct phy_device *phydev) 112 { 113 int val; 114 115 bcm54xx_config_clock_delay(phydev); 116 117 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { 118 val = phy_read(phydev, MII_CTRL1000); 119 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; 120 phy_write(phydev, MII_CTRL1000, val); 121 } 122 123 return 0; 124 } 125 126 static int bcm54612e_config_init(struct phy_device *phydev) 127 { 128 int reg; 129 130 bcm54xx_config_clock_delay(phydev); 131 132 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 133 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 134 int err; 135 136 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 137 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 138 BCM54612E_LED4_CLK125OUT_EN | reg); 139 140 if (err < 0) 141 return err; 142 } 143 144 return 0; 145 } 146 147 static int bcm54616s_config_init(struct phy_device *phydev) 148 { 149 int rc, val; 150 151 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 152 phydev->interface != PHY_INTERFACE_MODE_1000BASEX) 153 return 0; 154 155 /* Ensure proper interface mode is selected. */ 156 /* Disable RGMII mode */ 157 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 158 if (val < 0) 159 return val; 160 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN; 161 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 162 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 163 val); 164 if (rc < 0) 165 return rc; 166 167 /* Select 1000BASE-X register set (primary SerDes) */ 168 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 169 if (val < 0) 170 return val; 171 val |= BCM54XX_SHD_MODE_1000BX; 172 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 173 if (rc < 0) 174 return rc; 175 176 /* Power down SerDes interface */ 177 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); 178 if (rc < 0) 179 return rc; 180 181 /* Select proper interface mode */ 182 val &= ~BCM54XX_SHD_INTF_SEL_MASK; 183 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ? 184 BCM54XX_SHD_INTF_SEL_SGMII : 185 BCM54XX_SHD_INTF_SEL_GBIC; 186 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 187 if (rc < 0) 188 return rc; 189 190 /* Power up SerDes interface */ 191 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 192 if (rc < 0) 193 return rc; 194 195 /* Select copper register set */ 196 val &= ~BCM54XX_SHD_MODE_1000BX; 197 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 198 if (rc < 0) 199 return rc; 200 201 /* Power up copper interface */ 202 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 203 } 204 205 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */ 206 static int bcm50610_a0_workaround(struct phy_device *phydev) 207 { 208 int err; 209 210 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0, 211 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN | 212 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF); 213 if (err < 0) 214 return err; 215 216 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3, 217 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ); 218 if (err < 0) 219 return err; 220 221 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, 222 MII_BCM54XX_EXP_EXP75_VDACCTRL); 223 if (err < 0) 224 return err; 225 226 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96, 227 MII_BCM54XX_EXP_EXP96_MYST); 228 if (err < 0) 229 return err; 230 231 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97, 232 MII_BCM54XX_EXP_EXP97_MYST); 233 234 return err; 235 } 236 237 static int bcm54xx_phydsp_config(struct phy_device *phydev) 238 { 239 int err, err2; 240 241 /* Enable the SMDSP clock */ 242 err = bcm54xx_auxctl_write(phydev, 243 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 244 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA | 245 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 246 if (err < 0) 247 return err; 248 249 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 250 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) { 251 /* Clear bit 9 to fix a phy interop issue. */ 252 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, 253 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ); 254 if (err < 0) 255 goto error; 256 257 if (phydev->drv->phy_id == PHY_ID_BCM50610) { 258 err = bcm50610_a0_workaround(phydev); 259 if (err < 0) 260 goto error; 261 } 262 } 263 264 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM57780)) { 265 int val; 266 267 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); 268 if (val < 0) 269 goto error; 270 271 val |= MII_BCM54XX_EXP_EXP75_CM_OSC; 272 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); 273 } 274 275 error: 276 /* Disable the SMDSP clock */ 277 err2 = bcm54xx_auxctl_write(phydev, 278 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 279 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 280 281 /* Return the first error reported. */ 282 return err ? err : err2; 283 } 284 285 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) 286 { 287 u32 orig; 288 int val; 289 bool clk125en = true; 290 291 /* Abort if we are using an untested phy. */ 292 if (!(phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM57780) || 293 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 294 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M) || 295 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54210E) || 296 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54810) || 297 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811))) 298 return; 299 300 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); 301 if (val < 0) 302 return; 303 304 orig = val; 305 306 if ((phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 307 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) && 308 BRCM_PHY_REV(phydev) >= 0x3) { 309 /* 310 * Here, bit 0 _disables_ CLK125 when set. 311 * This bit is set by default. 312 */ 313 clk125en = false; 314 } else { 315 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) { 316 if (!phy_id_compare_model(phydev->drv->phy_id, 317 PHY_ID_BCM54811)) { 318 /* Here, bit 0 _enables_ CLK125 when set */ 319 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125; 320 } 321 clk125en = false; 322 } 323 } 324 325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 326 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS; 327 else 328 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; 329 330 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) { 331 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54210E) || 332 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54810) || 333 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811)) 334 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS; 335 else 336 val |= BCM54XX_SHD_SCR3_TRDDAPD; 337 } 338 339 if (orig != val) 340 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); 341 342 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); 343 if (val < 0) 344 return; 345 346 orig = val; 347 348 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 349 val |= BCM54XX_SHD_APD_EN; 350 else 351 val &= ~BCM54XX_SHD_APD_EN; 352 353 if (orig != val) 354 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); 355 } 356 357 static void bcm54xx_ptp_stop(struct phy_device *phydev) 358 { 359 struct bcm54xx_phy_priv *priv = phydev->priv; 360 361 if (priv->ptp) 362 bcm_ptp_stop(priv->ptp); 363 } 364 365 static void bcm54xx_ptp_config_init(struct phy_device *phydev) 366 { 367 struct bcm54xx_phy_priv *priv = phydev->priv; 368 369 if (priv->ptp) 370 bcm_ptp_config_init(phydev); 371 } 372 373 static int bcm5481x_set_brrmode(struct phy_device *phydev, bool on) 374 { 375 int reg; 376 int err; 377 u16 val; 378 379 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 380 381 if (reg < 0) 382 return reg; 383 384 if (on) 385 reg |= BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 386 else 387 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 388 389 err = bcm_phy_write_exp(phydev, 390 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, reg); 391 if (err) 392 return err; 393 394 /* Ensure LRE or IEEE register set is accessed according to the brr 395 * on/off, thus set the override 396 */ 397 val = BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_EN; 398 if (!on) 399 val |= BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL_OVERRIDE_VAL; 400 401 return bcm_phy_write_exp(phydev, 402 BCM54811_EXP_BROADREACH_LRE_OVERLAY_CTL, val); 403 } 404 405 static int bcm54811_config_init(struct phy_device *phydev) 406 { 407 struct bcm54xx_phy_priv *priv = phydev->priv; 408 int err, reg, exp_sync_ethernet; 409 410 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 411 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 412 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 413 if (reg < 0) 414 return reg; 415 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 416 BCM54612E_LED4_CLK125OUT_EN | reg); 417 if (err < 0) 418 return err; 419 } 420 421 /* With BCM54811, BroadR-Reach implies no autoneg */ 422 if (priv->brr_mode) 423 phydev->autoneg = 0; 424 425 /* Enable MII Lite (No TXER, RXER, CRS, COL) if configured */ 426 if (phydev->interface == PHY_INTERFACE_MODE_MIILITE) 427 exp_sync_ethernet = BCM_EXP_SYNC_ETHERNET_MII_LITE; 428 else 429 exp_sync_ethernet = 0; 430 431 err = bcm_phy_modify_exp(phydev, BCM_EXP_SYNC_ETHERNET, 432 BCM_EXP_SYNC_ETHERNET_MII_LITE, 433 exp_sync_ethernet); 434 if (err < 0) 435 return err; 436 437 return bcm5481x_set_brrmode(phydev, priv->brr_mode); 438 } 439 440 static int bcm54xx_config_init(struct phy_device *phydev) 441 { 442 int reg, err, val; 443 444 reg = phy_read(phydev, MII_BCM54XX_ECR); 445 if (reg < 0) 446 return reg; 447 448 /* Mask interrupts globally. */ 449 reg |= MII_BCM54XX_ECR_IM; 450 err = phy_write(phydev, MII_BCM54XX_ECR, reg); 451 if (err < 0) 452 return err; 453 454 /* Unmask events we are interested in. */ 455 reg = ~(MII_BCM54XX_INT_DUPLEX | 456 MII_BCM54XX_INT_SPEED | 457 MII_BCM54XX_INT_LINK); 458 err = phy_write(phydev, MII_BCM54XX_IMR, reg); 459 if (err < 0) 460 return err; 461 462 if ((phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610) || 463 phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM50610M)) && 464 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) 465 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); 466 467 bcm54xx_adjust_rxrefclk(phydev); 468 469 switch (phydev->drv->phy_id & PHY_ID_MATCH_MODEL_MASK) { 470 case PHY_ID_BCM50610: 471 case PHY_ID_BCM50610M: 472 err = bcm54xx_config_clock_delay(phydev); 473 break; 474 case PHY_ID_BCM54210E: 475 err = bcm54210e_config_init(phydev); 476 break; 477 case PHY_ID_BCM54612E: 478 err = bcm54612e_config_init(phydev); 479 break; 480 case PHY_ID_BCM54616S: 481 err = bcm54616s_config_init(phydev); 482 break; 483 case PHY_ID_BCM54810: 484 /* For BCM54810, we need to disable BroadR-Reach function */ 485 val = bcm_phy_read_exp(phydev, 486 BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 487 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 488 err = bcm_phy_write_exp(phydev, 489 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 490 val); 491 break; 492 case PHY_ID_BCM54811: 493 err = bcm54811_config_init(phydev); 494 break; 495 } 496 if (err) 497 return err; 498 499 bcm54xx_phydsp_config(phydev); 500 501 /* For non-SFP setups, encode link speed into LED1 and LED3 pair 502 * (green/amber). 503 * Also flash these two LEDs on activity. This means configuring 504 * them for MULTICOLOR and encoding link/activity into them. 505 * Don't do this for devices on an SFP module, since some of these 506 * use the LED outputs to control the SFP LOS signal, and changing 507 * these settings will cause LOS to malfunction. 508 */ 509 if (!phy_on_sfp(phydev)) { 510 val = BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) | 511 BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1); 512 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val); 513 514 val = BCM_LED_MULTICOLOR_IN_PHASE | 515 BCM54XX_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) | 516 BCM54XX_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT); 517 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); 518 } 519 520 bcm54xx_ptp_config_init(phydev); 521 522 /* Acknowledge any left over interrupt and charge the device for 523 * wake-up. 524 */ 525 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 526 if (err < 0) 527 return err; 528 529 if (err) 530 pm_wakeup_event(&phydev->mdio.dev, 0); 531 532 return 0; 533 } 534 535 static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable) 536 { 537 int ret = 0; 538 539 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND)) 540 return ret; 541 542 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL); 543 if (ret < 0) 544 goto out; 545 546 if (enable) 547 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP; 548 else 549 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP); 550 551 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret); 552 out: 553 return ret; 554 } 555 556 static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state) 557 { 558 struct bcm54xx_phy_priv *priv = phydev->priv; 559 int ret = 0; 560 561 if (!bcm54xx_phy_can_wakeup(phydev)) 562 return ret; 563 564 if (priv->wake_irq_enabled != state) { 565 if (state) 566 ret = enable_irq_wake(priv->wake_irq); 567 else 568 ret = disable_irq_wake(priv->wake_irq); 569 priv->wake_irq_enabled = state; 570 } 571 572 return ret; 573 } 574 575 static int bcm54xx_suspend(struct phy_device *phydev) 576 { 577 int ret = 0; 578 579 bcm54xx_ptp_stop(phydev); 580 581 /* Acknowledge any Wake-on-LAN interrupt prior to suspend */ 582 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 583 if (ret < 0) 584 return ret; 585 586 if (phydev->wol_enabled) 587 return bcm54xx_set_wakeup_irq(phydev, true); 588 589 /* We cannot use a read/modify/write here otherwise the PHY gets into 590 * a bad state where its LEDs keep flashing, thus defeating the purpose 591 * of low power mode. 592 */ 593 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 594 if (ret < 0) 595 return ret; 596 597 return bcm54xx_iddq_set(phydev, true); 598 } 599 600 static int bcm54xx_resume(struct phy_device *phydev) 601 { 602 int ret = 0; 603 604 if (phydev->wol_enabled) { 605 ret = bcm54xx_set_wakeup_irq(phydev, false); 606 if (ret) 607 return ret; 608 } 609 610 ret = bcm54xx_iddq_set(phydev, false); 611 if (ret < 0) 612 return ret; 613 614 /* Writes to register other than BMCR would be ignored 615 * unless we clear the PDOWN bit first 616 */ 617 ret = genphy_resume(phydev); 618 if (ret < 0) 619 return ret; 620 621 /* Upon exiting power down, the PHY remains in an internal reset state 622 * for 40us 623 */ 624 fsleep(40); 625 626 /* Issue a soft reset after clearing the power down bit 627 * and before doing any other configuration. 628 */ 629 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) { 630 ret = genphy_soft_reset(phydev); 631 if (ret < 0) 632 return ret; 633 } 634 635 return bcm54xx_config_init(phydev); 636 } 637 638 static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 639 { 640 return -EOPNOTSUPP; 641 } 642 643 static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 644 u16 val) 645 { 646 return -EOPNOTSUPP; 647 } 648 649 650 /** 651 * bcm5481x_read_abilities - read PHY abilities from LRESR or Clause 22 652 * (BMSR) registers, based on whether the PHY is in BroadR-Reach or IEEE mode 653 * @phydev: target phy_device struct 654 * 655 * Description: Reads the PHY's abilities and populates phydev->supported 656 * accordingly. The register to read the abilities from is determined by 657 * the brr mode setting of the PHY as read from the device tree. 658 * Note that the LRE and IEEE sets of abilities are disjunct, in other words, 659 * not only the link modes differ, but also the auto-negotiation and 660 * master-slave setup is controlled differently. 661 * 662 * Returns: 0 on success, < 0 on failure 663 */ 664 static int bcm5481x_read_abilities(struct phy_device *phydev) 665 { 666 struct device_node *np = phydev->mdio.dev.of_node; 667 struct bcm54xx_phy_priv *priv = phydev->priv; 668 int i, val, err, aneg; 669 670 for (i = 0; i < ARRAY_SIZE(bcm54811_linkmodes); i++) 671 linkmode_clear_bit(bcm54811_linkmodes[i], phydev->supported); 672 673 priv->brr_mode = of_property_read_bool(np, "brr-mode"); 674 675 /* Set BroadR-Reach mode as configured in the DT. */ 676 err = bcm5481x_set_brrmode(phydev, priv->brr_mode); 677 if (err) 678 return err; 679 680 if (priv->brr_mode) { 681 linkmode_set_bit_array(phy_basic_ports_array, 682 ARRAY_SIZE(phy_basic_ports_array), 683 phydev->supported); 684 685 val = phy_read(phydev, MII_BCM54XX_LRESR); 686 if (val < 0) 687 return val; 688 689 /* BCM54811 is not capable of LDS but the corresponding bit 690 * in LRESR is set to 1 and marked "Ignore" in the datasheet. 691 * So we must read the bcm54811 as unable to auto-negotiate 692 * in BroadR-Reach mode. 693 */ 694 if (phy_id_compare_model(phydev->drv->phy_id, PHY_ID_BCM54811)) 695 aneg = 0; 696 else 697 aneg = val & LRESR_LDSABILITY; 698 699 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 700 phydev->supported, 701 aneg); 702 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 703 phydev->supported, 704 val & LRESR_100_1PAIR); 705 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 706 phydev->supported, 707 val & LRESR_10_1PAIR); 708 return 0; 709 } 710 711 return genphy_read_abilities(phydev); 712 } 713 714 static int bcm5481x_config_delay_swap(struct phy_device *phydev) 715 { 716 struct device_node *np = phydev->mdio.dev.of_node; 717 718 /* Set up the delay. */ 719 bcm54xx_config_clock_delay(phydev); 720 721 if (of_property_read_bool(np, "enet-phy-lane-swap")) { 722 /* Lane Swap - Undocumented register...magic! */ 723 int ret = bcm_phy_write_exp(phydev, 724 MII_BCM54XX_EXP_SEL_ER + 0x9, 725 0x11B); 726 if (ret < 0) 727 return ret; 728 } 729 730 return 0; 731 } 732 733 static int bcm5481_config_aneg(struct phy_device *phydev) 734 { 735 struct bcm54xx_phy_priv *priv = phydev->priv; 736 int ret; 737 738 /* Aneg firstly. */ 739 if (priv->brr_mode) 740 ret = bcm_config_lre_aneg(phydev, false); 741 else 742 ret = genphy_config_aneg(phydev); 743 744 if (ret) 745 return ret; 746 747 /* Then we can set up the delay and swap. */ 748 return bcm5481x_config_delay_swap(phydev); 749 } 750 751 static int bcm54811_config_aneg(struct phy_device *phydev) 752 { 753 struct bcm54xx_phy_priv *priv = phydev->priv; 754 int ret; 755 756 /* Aneg firstly. */ 757 if (priv->brr_mode) { 758 /* BCM54811 is only capable of autonegotiation in IEEE mode. 759 * In BroadR-Reach mode, disable the Long Distance Signaling, 760 * the BRR mode autoneg as supported in other Broadcom PHYs. 761 * This bit is marked as "Reserved" and "Default 1, must be 762 * written to 0 after every device reset" in the datasheet. 763 */ 764 ret = phy_modify(phydev, MII_BCM54XX_LRECR, LRECR_LDSEN, 0); 765 if (ret < 0) 766 return ret; 767 ret = bcm_config_lre_aneg(phydev, false); 768 } else { 769 ret = genphy_config_aneg(phydev); 770 } 771 772 if (ret) 773 return ret; 774 775 /* Then we can set up the delay and swap. */ 776 return bcm5481x_config_delay_swap(phydev); 777 } 778 779 struct bcm54616s_phy_priv { 780 bool mode_1000bx_en; 781 }; 782 783 static int bcm54616s_probe(struct phy_device *phydev) 784 { 785 struct bcm54616s_phy_priv *priv; 786 int val; 787 788 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 789 if (!priv) 790 return -ENOMEM; 791 792 phydev->priv = priv; 793 794 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 795 if (val < 0) 796 return val; 797 798 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0] 799 * is 01b, and the link between PHY and its link partner can be 800 * either 1000Base-X or 100Base-FX. 801 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX 802 * support is still missing as of now. 803 */ 804 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) { 805 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL); 806 if (val < 0) 807 return val; 808 809 /* Bit 0 of the SerDes 100-FX Control register, when set 810 * to 1, sets the MII/RGMII -> 100BASE-FX configuration. 811 * When this bit is set to 0, it sets the GMII/RGMII -> 812 * 1000BASE-X configuration. 813 */ 814 if (!(val & BCM54616S_100FX_MODE)) 815 priv->mode_1000bx_en = true; 816 817 phydev->port = PORT_FIBRE; 818 } 819 820 return 0; 821 } 822 823 static int bcm54616s_config_aneg(struct phy_device *phydev) 824 { 825 struct bcm54616s_phy_priv *priv = phydev->priv; 826 int ret; 827 828 /* Aneg firstly. */ 829 if (priv->mode_1000bx_en) 830 ret = genphy_c37_config_aneg(phydev); 831 else 832 ret = genphy_config_aneg(phydev); 833 834 /* Then we can set up the delay. */ 835 bcm54xx_config_clock_delay(phydev); 836 837 return ret; 838 } 839 840 static int bcm54616s_read_status(struct phy_device *phydev) 841 { 842 struct bcm54616s_phy_priv *priv = phydev->priv; 843 bool changed; 844 int err; 845 846 if (priv->mode_1000bx_en) 847 err = genphy_c37_read_status(phydev, &changed); 848 else 849 err = genphy_read_status(phydev); 850 851 return err; 852 } 853 854 static int brcm_fet_config_init(struct phy_device *phydev) 855 { 856 int reg, err, err2, brcmtest; 857 858 /* Reset the PHY to bring it to a known state. */ 859 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 860 if (err < 0) 861 return err; 862 863 /* The datasheet indicates the PHY needs up to 1us to complete a reset, 864 * build some slack here. 865 */ 866 usleep_range(1000, 2000); 867 868 /* The PHY requires 65 MDC clock cycles to complete a write operation 869 * and turnaround the line properly. 870 * 871 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac) 872 * may flag the lack of turn-around as a read failure. This is 873 * particularly true with this combination since the MDIO controller 874 * only used 64 MDC cycles. This is not a critical failure in this 875 * specific case and it has no functional impact otherwise, so we let 876 * that one go through. If there is a genuine bus error, the next read 877 * of MII_BRCM_FET_INTREG will error out. 878 */ 879 err = phy_read(phydev, MII_BMCR); 880 if (err < 0 && err != -EIO) 881 return err; 882 883 /* Read to clear status bits */ 884 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 885 if (reg < 0) 886 return reg; 887 888 /* Unmask events we are interested in and mask interrupts globally. */ 889 if (phydev->drv->phy_id == PHY_ID_BCM5221) 890 reg = MII_BRCM_FET_IR_ENABLE | 891 MII_BRCM_FET_IR_MASK; 892 else 893 reg = MII_BRCM_FET_IR_DUPLEX_EN | 894 MII_BRCM_FET_IR_SPEED_EN | 895 MII_BRCM_FET_IR_LINK_EN | 896 MII_BRCM_FET_IR_ENABLE | 897 MII_BRCM_FET_IR_MASK; 898 899 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 900 if (err < 0) 901 return err; 902 903 /* Enable shadow register access */ 904 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 905 if (brcmtest < 0) 906 return brcmtest; 907 908 reg = brcmtest | MII_BRCM_FET_BT_SRE; 909 910 phy_lock_mdio_bus(phydev); 911 912 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 913 if (err < 0) { 914 phy_unlock_mdio_bus(phydev); 915 return err; 916 } 917 918 if (phydev->drv->phy_id != PHY_ID_BCM5221) { 919 /* Set the LED mode */ 920 reg = __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); 921 if (reg < 0) { 922 err = reg; 923 goto done; 924 } 925 926 err = __phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4, 927 MII_BRCM_FET_SHDW_AM4_LED_MASK, 928 MII_BRCM_FET_SHDW_AM4_LED_MODE1); 929 if (err < 0) 930 goto done; 931 932 /* Enable auto MDIX */ 933 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, 934 MII_BRCM_FET_SHDW_MC_FAME); 935 if (err < 0) 936 goto done; 937 } 938 939 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { 940 /* Enable auto power down */ 941 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, 942 MII_BRCM_FET_SHDW_AS2_APDE); 943 } 944 945 done: 946 /* Disable shadow register access */ 947 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 948 if (!err) 949 err = err2; 950 951 phy_unlock_mdio_bus(phydev); 952 953 return err; 954 } 955 956 static int brcm_fet_ack_interrupt(struct phy_device *phydev) 957 { 958 int reg; 959 960 /* Clear pending interrupts. */ 961 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 962 if (reg < 0) 963 return reg; 964 965 return 0; 966 } 967 968 static int brcm_fet_config_intr(struct phy_device *phydev) 969 { 970 int reg, err; 971 972 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 973 if (reg < 0) 974 return reg; 975 976 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 977 err = brcm_fet_ack_interrupt(phydev); 978 if (err) 979 return err; 980 981 reg &= ~MII_BRCM_FET_IR_MASK; 982 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 983 } else { 984 reg |= MII_BRCM_FET_IR_MASK; 985 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 986 if (err) 987 return err; 988 989 err = brcm_fet_ack_interrupt(phydev); 990 } 991 992 return err; 993 } 994 995 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev) 996 { 997 int irq_status; 998 999 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG); 1000 if (irq_status < 0) { 1001 phy_error(phydev); 1002 return IRQ_NONE; 1003 } 1004 1005 if (irq_status == 0) 1006 return IRQ_NONE; 1007 1008 phy_trigger_machine(phydev); 1009 1010 return IRQ_HANDLED; 1011 } 1012 1013 static int brcm_fet_suspend(struct phy_device *phydev) 1014 { 1015 int reg, err, err2, brcmtest; 1016 1017 /* We cannot use a read/modify/write here otherwise the PHY continues 1018 * to drive LEDs which defeats the purpose of low power mode. 1019 */ 1020 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 1021 if (err < 0) 1022 return err; 1023 1024 /* Enable shadow register access */ 1025 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 1026 if (brcmtest < 0) 1027 return brcmtest; 1028 1029 reg = brcmtest | MII_BRCM_FET_BT_SRE; 1030 1031 phy_lock_mdio_bus(phydev); 1032 1033 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 1034 if (err < 0) { 1035 phy_unlock_mdio_bus(phydev); 1036 return err; 1037 } 1038 1039 if (phydev->drv->phy_id == PHY_ID_BCM5221) 1040 /* Force Low Power Mode with clock enabled */ 1041 reg = BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM; 1042 else 1043 /* Set standby mode */ 1044 reg = MII_BRCM_FET_SHDW_AM4_STANDBY; 1045 1046 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); 1047 1048 /* Disable shadow register access */ 1049 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 1050 if (!err) 1051 err = err2; 1052 1053 phy_unlock_mdio_bus(phydev); 1054 1055 return err; 1056 } 1057 1058 static int bcm5221_config_aneg(struct phy_device *phydev) 1059 { 1060 int ret, val; 1061 1062 ret = genphy_config_aneg(phydev); 1063 if (ret) 1064 return ret; 1065 1066 switch (phydev->mdix_ctrl) { 1067 case ETH_TP_MDI: 1068 val = BCM5221_AEGSR_MDIX_DIS; 1069 break; 1070 case ETH_TP_MDI_X: 1071 val = BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP; 1072 break; 1073 case ETH_TP_MDI_AUTO: 1074 val = 0; 1075 break; 1076 default: 1077 return 0; 1078 } 1079 1080 return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP | 1081 BCM5221_AEGSR_MDIX_DIS, 1082 val); 1083 } 1084 1085 static int bcm5221_read_status(struct phy_device *phydev) 1086 { 1087 int ret; 1088 1089 /* Read MDIX status */ 1090 ret = phy_read(phydev, BCM5221_AEGSR); 1091 if (ret < 0) 1092 return ret; 1093 1094 if (ret & BCM5221_AEGSR_MDIX_DIS) { 1095 if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP) 1096 phydev->mdix_ctrl = ETH_TP_MDI_X; 1097 else 1098 phydev->mdix_ctrl = ETH_TP_MDI; 1099 } else { 1100 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1101 } 1102 1103 if (ret & BCM5221_AEGSR_MDIX_STATUS) 1104 phydev->mdix = ETH_TP_MDI_X; 1105 else 1106 phydev->mdix = ETH_TP_MDI; 1107 1108 return genphy_read_status(phydev); 1109 } 1110 1111 static void bcm54xx_phy_get_wol(struct phy_device *phydev, 1112 struct ethtool_wolinfo *wol) 1113 { 1114 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 1115 * or an out of band GPIO descriptor for wake-up. Zeroing 1116 * wol->supported allows the caller (MAC driver) to play through and 1117 * offer its own Wake-on-LAN scheme if available. 1118 */ 1119 if (!bcm54xx_phy_can_wakeup(phydev)) { 1120 wol->supported = 0; 1121 return; 1122 } 1123 1124 bcm_phy_get_wol(phydev, wol); 1125 } 1126 1127 static int bcm54xx_phy_set_wol(struct phy_device *phydev, 1128 struct ethtool_wolinfo *wol) 1129 { 1130 int ret; 1131 1132 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 1133 * or an out of band GPIO descriptor for wake-up. Returning -EOPNOTSUPP 1134 * allows the caller (MAC driver) to play through and offer its own 1135 * Wake-on-LAN scheme if available. 1136 */ 1137 if (!bcm54xx_phy_can_wakeup(phydev)) 1138 return -EOPNOTSUPP; 1139 1140 ret = bcm_phy_set_wol(phydev, wol); 1141 if (ret < 0) 1142 return ret; 1143 1144 return 0; 1145 } 1146 1147 static int bcm54xx_phy_probe(struct phy_device *phydev) 1148 { 1149 struct bcm54xx_phy_priv *priv; 1150 struct gpio_desc *wakeup_gpio; 1151 int ret = 0; 1152 1153 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1154 if (!priv) 1155 return -ENOMEM; 1156 1157 priv->wake_irq = -ENXIO; 1158 1159 phydev->priv = priv; 1160 1161 priv->stats = devm_kcalloc(&phydev->mdio.dev, 1162 bcm_phy_get_sset_count(phydev), sizeof(u64), 1163 GFP_KERNEL); 1164 if (!priv->stats) 1165 return -ENOMEM; 1166 1167 priv->ptp = bcm_ptp_probe(phydev); 1168 if (IS_ERR(priv->ptp)) 1169 return PTR_ERR(priv->ptp); 1170 1171 /* We cannot utilize the _optional variant here since we want to know 1172 * whether the GPIO descriptor exists or not to advertise Wake-on-LAN 1173 * support or not. 1174 */ 1175 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN); 1176 if (PTR_ERR(wakeup_gpio) == -EPROBE_DEFER) 1177 return PTR_ERR(wakeup_gpio); 1178 1179 if (!IS_ERR(wakeup_gpio)) { 1180 priv->wake_irq = gpiod_to_irq(wakeup_gpio); 1181 1182 /* Dummy interrupt handler which is not enabled but is provided 1183 * in order for the interrupt descriptor to be fully set-up. 1184 */ 1185 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq, 1186 bcm_phy_wol_isr, 1187 IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN, 1188 dev_name(&phydev->mdio.dev), phydev); 1189 if (ret) 1190 return ret; 1191 } 1192 1193 /* If we do not have a main interrupt or a side-band wake-up interrupt, 1194 * then the device cannot be marked as wake-up capable. 1195 */ 1196 if (!bcm54xx_phy_can_wakeup(phydev)) 1197 return 0; 1198 1199 return device_init_wakeup(&phydev->mdio.dev, true); 1200 } 1201 1202 static void bcm54xx_get_stats(struct phy_device *phydev, 1203 struct ethtool_stats *stats, u64 *data) 1204 { 1205 struct bcm54xx_phy_priv *priv = phydev->priv; 1206 1207 bcm_phy_get_stats(phydev, priv->stats, stats, data); 1208 } 1209 1210 static void bcm54xx_link_change_notify(struct phy_device *phydev) 1211 { 1212 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE | 1213 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE; 1214 int ret; 1215 1216 if (phydev->state != PHY_RUNNING) 1217 return; 1218 1219 /* Don't change the DAC wake settings if auto power down 1220 * is not requested. 1221 */ 1222 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 1223 return; 1224 1225 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08); 1226 if (ret < 0) 1227 return; 1228 1229 /* Enable/disable 10BaseT auto and forced early DAC wake depending 1230 * on the negotiated speed, those settings should only be done 1231 * for 10Mbits/sec. 1232 */ 1233 if (phydev->speed == SPEED_10) 1234 ret |= mask; 1235 else 1236 ret &= ~mask; 1237 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret); 1238 } 1239 1240 static int lre_read_master_slave(struct phy_device *phydev) 1241 { 1242 int cfg = MASTER_SLAVE_CFG_UNKNOWN, state; 1243 int val; 1244 1245 /* In BroadR-Reach mode we are always capable of master-slave 1246 * and there is no preferred master or slave configuration 1247 */ 1248 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 1249 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 1250 1251 val = phy_read(phydev, MII_BCM54XX_LRECR); 1252 if (val < 0) 1253 return val; 1254 1255 if ((val & LRECR_LDSEN) == 0) { 1256 if (val & LRECR_MASTER) 1257 cfg = MASTER_SLAVE_CFG_MASTER_FORCE; 1258 else 1259 cfg = MASTER_SLAVE_CFG_SLAVE_FORCE; 1260 } 1261 1262 val = phy_read(phydev, MII_BCM54XX_LRELDSE); 1263 if (val < 0) 1264 return val; 1265 1266 if (val & LDSE_MASTER) 1267 state = MASTER_SLAVE_STATE_MASTER; 1268 else 1269 state = MASTER_SLAVE_STATE_SLAVE; 1270 1271 phydev->master_slave_get = cfg; 1272 phydev->master_slave_state = state; 1273 1274 return 0; 1275 } 1276 1277 /* Read LDS Link Partner Ability in BroadR-Reach mode */ 1278 static int lre_read_lpa(struct phy_device *phydev) 1279 { 1280 int i, lrelpa; 1281 1282 if (phydev->autoneg != AUTONEG_ENABLE) { 1283 if (!phydev->autoneg_complete) { 1284 /* aneg not yet done, reset all relevant bits */ 1285 for (i = 0; i < ARRAY_SIZE(lds_br_bits); i++) 1286 linkmode_clear_bit(lds_br_bits[i], 1287 phydev->lp_advertising); 1288 1289 return 0; 1290 } 1291 1292 /* Long-Distance Signaling Link Partner Ability */ 1293 lrelpa = phy_read(phydev, MII_BCM54XX_LRELPA); 1294 if (lrelpa < 0) 1295 return lrelpa; 1296 1297 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 1298 phydev->lp_advertising, 1299 lrelpa & LRELPA_PAUSE_ASYM); 1300 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, 1301 phydev->lp_advertising, 1302 lrelpa & LRELPA_PAUSE); 1303 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 1304 phydev->lp_advertising, 1305 lrelpa & LRELPA_100_1PAIR); 1306 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1BRR_Full_BIT, 1307 phydev->lp_advertising, 1308 lrelpa & LRELPA_10_1PAIR); 1309 } else { 1310 linkmode_zero(phydev->lp_advertising); 1311 } 1312 1313 return 0; 1314 } 1315 1316 static int lre_read_status_fixed(struct phy_device *phydev) 1317 { 1318 int lrecr = phy_read(phydev, MII_BCM54XX_LRECR); 1319 1320 if (lrecr < 0) 1321 return lrecr; 1322 1323 phydev->duplex = DUPLEX_FULL; 1324 1325 if (lrecr & LRECR_SPEED100) 1326 phydev->speed = SPEED_100; 1327 else 1328 phydev->speed = SPEED_10; 1329 1330 return 0; 1331 } 1332 1333 /** 1334 * lre_update_link - update link status in @phydev 1335 * @phydev: target phy_device struct 1336 * Return: 0 on success, < 0 on error 1337 * 1338 * Description: Update the value in phydev->link to reflect the 1339 * current link value. In order to do this, we need to read 1340 * the status register twice, keeping the second value. 1341 * This is a genphy_update_link modified to work on LRE registers 1342 * of BroadR-Reach PHY 1343 */ 1344 static int lre_update_link(struct phy_device *phydev) 1345 { 1346 int status = 0, lrecr; 1347 1348 lrecr = phy_read(phydev, MII_BCM54XX_LRECR); 1349 if (lrecr < 0) 1350 return lrecr; 1351 1352 /* Autoneg is being started, therefore disregard BMSR value and 1353 * report link as down. 1354 */ 1355 if (lrecr & BMCR_ANRESTART) 1356 goto done; 1357 1358 /* The link state is latched low so that momentary link 1359 * drops can be detected. Do not double-read the status 1360 * in polling mode to detect such short link drops except 1361 * the link was already down. 1362 */ 1363 if (!phy_polling_mode(phydev) || !phydev->link) { 1364 status = phy_read(phydev, MII_BCM54XX_LRESR); 1365 if (status < 0) 1366 return status; 1367 else if (status & LRESR_LSTATUS) 1368 goto done; 1369 } 1370 1371 /* Read link and autonegotiation status */ 1372 status = phy_read(phydev, MII_BCM54XX_LRESR); 1373 if (status < 0) 1374 return status; 1375 done: 1376 phydev->link = status & LRESR_LSTATUS ? 1 : 0; 1377 phydev->autoneg_complete = status & LRESR_LDSCOMPLETE ? 1 : 0; 1378 1379 /* Consider the case that autoneg was started and "aneg complete" 1380 * bit has been reset, but "link up" bit not yet. 1381 */ 1382 if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete) 1383 phydev->link = 0; 1384 1385 return 0; 1386 } 1387 1388 /* Get the status in BroadRReach mode just like genphy_read_status does 1389 * in normal mode 1390 */ 1391 static int bcm54811_lre_read_status(struct phy_device *phydev) 1392 { 1393 int err, old_link = phydev->link; 1394 1395 /* Update the link, but return if there was an error */ 1396 err = lre_update_link(phydev); 1397 if (err) 1398 return err; 1399 1400 /* why bother the PHY if nothing can have changed */ 1401 if (phydev->autoneg == 1402 AUTONEG_ENABLE && old_link && phydev->link) 1403 return 0; 1404 1405 phydev->speed = SPEED_UNKNOWN; 1406 phydev->duplex = DUPLEX_UNKNOWN; 1407 phydev->pause = 0; 1408 phydev->asym_pause = 0; 1409 1410 err = lre_read_master_slave(phydev); 1411 if (err < 0) 1412 return err; 1413 1414 /* Read LDS Link Partner Ability */ 1415 err = lre_read_lpa(phydev); 1416 if (err < 0) 1417 return err; 1418 1419 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1420 phy_resolve_aneg_linkmode(phydev); 1421 else if (phydev->autoneg == AUTONEG_DISABLE) 1422 err = lre_read_status_fixed(phydev); 1423 1424 return err; 1425 } 1426 1427 static int bcm54811_read_status(struct phy_device *phydev) 1428 { 1429 struct bcm54xx_phy_priv *priv = phydev->priv; 1430 1431 if (priv->brr_mode) 1432 return bcm54811_lre_read_status(phydev); 1433 1434 return genphy_read_status(phydev); 1435 } 1436 1437 static struct phy_driver broadcom_drivers[] = { 1438 { 1439 PHY_ID_MATCH_MODEL(PHY_ID_BCM5411), 1440 .name = "Broadcom BCM5411", 1441 /* PHY_GBIT_FEATURES */ 1442 .get_sset_count = bcm_phy_get_sset_count, 1443 .get_strings = bcm_phy_get_strings, 1444 .get_stats = bcm54xx_get_stats, 1445 .probe = bcm54xx_phy_probe, 1446 .config_init = bcm54xx_config_init, 1447 .config_intr = bcm_phy_config_intr, 1448 .handle_interrupt = bcm_phy_handle_interrupt, 1449 .link_change_notify = bcm54xx_link_change_notify, 1450 }, { 1451 PHY_ID_MATCH_MODEL(PHY_ID_BCM5421), 1452 .name = "Broadcom BCM5421", 1453 /* PHY_GBIT_FEATURES */ 1454 .get_sset_count = bcm_phy_get_sset_count, 1455 .get_strings = bcm_phy_get_strings, 1456 .get_stats = bcm54xx_get_stats, 1457 .probe = bcm54xx_phy_probe, 1458 .config_init = bcm54xx_config_init, 1459 .config_intr = bcm_phy_config_intr, 1460 .handle_interrupt = bcm_phy_handle_interrupt, 1461 .link_change_notify = bcm54xx_link_change_notify, 1462 }, { 1463 PHY_ID_MATCH_MODEL(PHY_ID_BCM54210E), 1464 .name = "Broadcom BCM54210E", 1465 /* PHY_GBIT_FEATURES */ 1466 .flags = PHY_ALWAYS_CALL_SUSPEND, 1467 .get_sset_count = bcm_phy_get_sset_count, 1468 .get_strings = bcm_phy_get_strings, 1469 .get_stats = bcm54xx_get_stats, 1470 .probe = bcm54xx_phy_probe, 1471 .config_init = bcm54xx_config_init, 1472 .config_intr = bcm_phy_config_intr, 1473 .handle_interrupt = bcm_phy_handle_interrupt, 1474 .link_change_notify = bcm54xx_link_change_notify, 1475 .suspend = bcm54xx_suspend, 1476 .resume = bcm54xx_resume, 1477 .get_wol = bcm54xx_phy_get_wol, 1478 .set_wol = bcm54xx_phy_set_wol, 1479 .led_brightness_set = bcm_phy_led_brightness_set, 1480 }, { 1481 PHY_ID_MATCH_MODEL(PHY_ID_BCM5461), 1482 .name = "Broadcom BCM5461", 1483 /* PHY_GBIT_FEATURES */ 1484 .get_sset_count = bcm_phy_get_sset_count, 1485 .get_strings = bcm_phy_get_strings, 1486 .get_stats = bcm54xx_get_stats, 1487 .probe = bcm54xx_phy_probe, 1488 .config_init = bcm54xx_config_init, 1489 .config_intr = bcm_phy_config_intr, 1490 .handle_interrupt = bcm_phy_handle_interrupt, 1491 .link_change_notify = bcm54xx_link_change_notify, 1492 .led_brightness_set = bcm_phy_led_brightness_set, 1493 }, { 1494 PHY_ID_MATCH_MODEL(PHY_ID_BCM54612E), 1495 .name = "Broadcom BCM54612E", 1496 /* PHY_GBIT_FEATURES */ 1497 .get_sset_count = bcm_phy_get_sset_count, 1498 .get_strings = bcm_phy_get_strings, 1499 .get_stats = bcm54xx_get_stats, 1500 .probe = bcm54xx_phy_probe, 1501 .config_init = bcm54xx_config_init, 1502 .config_intr = bcm_phy_config_intr, 1503 .handle_interrupt = bcm_phy_handle_interrupt, 1504 .link_change_notify = bcm54xx_link_change_notify, 1505 .led_brightness_set = bcm_phy_led_brightness_set, 1506 .suspend = bcm54xx_suspend, 1507 .resume = bcm54xx_resume, 1508 }, { 1509 PHY_ID_MATCH_MODEL(PHY_ID_BCM54616S), 1510 .name = "Broadcom BCM54616S", 1511 /* PHY_GBIT_FEATURES */ 1512 .soft_reset = genphy_soft_reset, 1513 .config_init = bcm54xx_config_init, 1514 .config_aneg = bcm54616s_config_aneg, 1515 .config_intr = bcm_phy_config_intr, 1516 .handle_interrupt = bcm_phy_handle_interrupt, 1517 .read_status = bcm54616s_read_status, 1518 .probe = bcm54616s_probe, 1519 .link_change_notify = bcm54xx_link_change_notify, 1520 .led_brightness_set = bcm_phy_led_brightness_set, 1521 }, { 1522 PHY_ID_MATCH_MODEL(PHY_ID_BCM5464), 1523 .name = "Broadcom BCM5464", 1524 /* PHY_GBIT_FEATURES */ 1525 .get_sset_count = bcm_phy_get_sset_count, 1526 .get_strings = bcm_phy_get_strings, 1527 .get_stats = bcm54xx_get_stats, 1528 .probe = bcm54xx_phy_probe, 1529 .config_init = bcm54xx_config_init, 1530 .config_intr = bcm_phy_config_intr, 1531 .handle_interrupt = bcm_phy_handle_interrupt, 1532 .suspend = genphy_suspend, 1533 .resume = genphy_resume, 1534 .link_change_notify = bcm54xx_link_change_notify, 1535 .led_brightness_set = bcm_phy_led_brightness_set, 1536 }, { 1537 PHY_ID_MATCH_MODEL(PHY_ID_BCM5481), 1538 .name = "Broadcom BCM5481", 1539 /* PHY_GBIT_FEATURES */ 1540 .get_sset_count = bcm_phy_get_sset_count, 1541 .get_strings = bcm_phy_get_strings, 1542 .get_stats = bcm54xx_get_stats, 1543 .probe = bcm54xx_phy_probe, 1544 .config_init = bcm54xx_config_init, 1545 .config_aneg = bcm5481_config_aneg, 1546 .config_intr = bcm_phy_config_intr, 1547 .handle_interrupt = bcm_phy_handle_interrupt, 1548 .link_change_notify = bcm54xx_link_change_notify, 1549 .led_brightness_set = bcm_phy_led_brightness_set, 1550 }, { 1551 PHY_ID_MATCH_MODEL(PHY_ID_BCM54810), 1552 .name = "Broadcom BCM54810", 1553 /* PHY_GBIT_FEATURES */ 1554 .get_sset_count = bcm_phy_get_sset_count, 1555 .get_strings = bcm_phy_get_strings, 1556 .get_stats = bcm54xx_get_stats, 1557 .probe = bcm54xx_phy_probe, 1558 .read_mmd = bcm54810_read_mmd, 1559 .write_mmd = bcm54810_write_mmd, 1560 .config_init = bcm54xx_config_init, 1561 .config_aneg = bcm5481_config_aneg, 1562 .config_intr = bcm_phy_config_intr, 1563 .handle_interrupt = bcm_phy_handle_interrupt, 1564 .suspend = bcm54xx_suspend, 1565 .resume = bcm54xx_resume, 1566 .link_change_notify = bcm54xx_link_change_notify, 1567 .led_brightness_set = bcm_phy_led_brightness_set, 1568 }, { 1569 PHY_ID_MATCH_MODEL(PHY_ID_BCM54811), 1570 .name = "Broadcom BCM54811", 1571 /* PHY_GBIT_FEATURES */ 1572 .get_sset_count = bcm_phy_get_sset_count, 1573 .get_strings = bcm_phy_get_strings, 1574 .get_stats = bcm54xx_get_stats, 1575 .probe = bcm54xx_phy_probe, 1576 .config_init = bcm54xx_config_init, 1577 .config_aneg = bcm54811_config_aneg, 1578 .config_intr = bcm_phy_config_intr, 1579 .handle_interrupt = bcm_phy_handle_interrupt, 1580 .read_status = bcm54811_read_status, 1581 .get_features = bcm5481x_read_abilities, 1582 .suspend = bcm54xx_suspend, 1583 .resume = bcm54xx_resume, 1584 .link_change_notify = bcm54xx_link_change_notify, 1585 .led_brightness_set = bcm_phy_led_brightness_set, 1586 }, { 1587 PHY_ID_MATCH_MODEL(PHY_ID_BCM5482), 1588 .name = "Broadcom BCM5482", 1589 /* PHY_GBIT_FEATURES */ 1590 .get_sset_count = bcm_phy_get_sset_count, 1591 .get_strings = bcm_phy_get_strings, 1592 .get_stats = bcm54xx_get_stats, 1593 .probe = bcm54xx_phy_probe, 1594 .config_init = bcm54xx_config_init, 1595 .config_intr = bcm_phy_config_intr, 1596 .handle_interrupt = bcm_phy_handle_interrupt, 1597 .link_change_notify = bcm54xx_link_change_notify, 1598 .led_brightness_set = bcm_phy_led_brightness_set, 1599 }, { 1600 PHY_ID_MATCH_MODEL(PHY_ID_BCM50610), 1601 .name = "Broadcom BCM50610", 1602 /* PHY_GBIT_FEATURES */ 1603 .get_sset_count = bcm_phy_get_sset_count, 1604 .get_strings = bcm_phy_get_strings, 1605 .get_stats = bcm54xx_get_stats, 1606 .probe = bcm54xx_phy_probe, 1607 .config_init = bcm54xx_config_init, 1608 .config_intr = bcm_phy_config_intr, 1609 .handle_interrupt = bcm_phy_handle_interrupt, 1610 .link_change_notify = bcm54xx_link_change_notify, 1611 .suspend = bcm54xx_suspend, 1612 .resume = bcm54xx_resume, 1613 .led_brightness_set = bcm_phy_led_brightness_set, 1614 }, { 1615 PHY_ID_MATCH_MODEL(PHY_ID_BCM50610M), 1616 .name = "Broadcom BCM50610M", 1617 /* PHY_GBIT_FEATURES */ 1618 .get_sset_count = bcm_phy_get_sset_count, 1619 .get_strings = bcm_phy_get_strings, 1620 .get_stats = bcm54xx_get_stats, 1621 .probe = bcm54xx_phy_probe, 1622 .config_init = bcm54xx_config_init, 1623 .config_intr = bcm_phy_config_intr, 1624 .handle_interrupt = bcm_phy_handle_interrupt, 1625 .link_change_notify = bcm54xx_link_change_notify, 1626 .suspend = bcm54xx_suspend, 1627 .resume = bcm54xx_resume, 1628 .led_brightness_set = bcm_phy_led_brightness_set, 1629 }, { 1630 PHY_ID_MATCH_MODEL(PHY_ID_BCM57780), 1631 .name = "Broadcom BCM57780", 1632 /* PHY_GBIT_FEATURES */ 1633 .get_sset_count = bcm_phy_get_sset_count, 1634 .get_strings = bcm_phy_get_strings, 1635 .get_stats = bcm54xx_get_stats, 1636 .probe = bcm54xx_phy_probe, 1637 .config_init = bcm54xx_config_init, 1638 .config_intr = bcm_phy_config_intr, 1639 .handle_interrupt = bcm_phy_handle_interrupt, 1640 .link_change_notify = bcm54xx_link_change_notify, 1641 .led_brightness_set = bcm_phy_led_brightness_set, 1642 }, { 1643 PHY_ID_MATCH_MODEL(PHY_ID_BCMAC131), 1644 .name = "Broadcom BCMAC131", 1645 /* PHY_BASIC_FEATURES */ 1646 .config_init = brcm_fet_config_init, 1647 .config_intr = brcm_fet_config_intr, 1648 .handle_interrupt = brcm_fet_handle_interrupt, 1649 .suspend = brcm_fet_suspend, 1650 .resume = brcm_fet_config_init, 1651 }, { 1652 PHY_ID_MATCH_MODEL(PHY_ID_BCM5241), 1653 .name = "Broadcom BCM5241", 1654 /* PHY_BASIC_FEATURES */ 1655 .config_init = brcm_fet_config_init, 1656 .config_intr = brcm_fet_config_intr, 1657 .handle_interrupt = brcm_fet_handle_interrupt, 1658 .suspend = brcm_fet_suspend, 1659 .resume = brcm_fet_config_init, 1660 }, { 1661 PHY_ID_MATCH_MODEL(PHY_ID_BCM5221), 1662 .name = "Broadcom BCM5221", 1663 /* PHY_BASIC_FEATURES */ 1664 .config_init = brcm_fet_config_init, 1665 .config_intr = brcm_fet_config_intr, 1666 .handle_interrupt = brcm_fet_handle_interrupt, 1667 .suspend = brcm_fet_suspend, 1668 .resume = brcm_fet_config_init, 1669 .config_aneg = bcm5221_config_aneg, 1670 .read_status = bcm5221_read_status, 1671 }, { 1672 PHY_ID_MATCH_MODEL(PHY_ID_BCM5395), 1673 .name = "Broadcom BCM5395", 1674 .flags = PHY_IS_INTERNAL, 1675 /* PHY_GBIT_FEATURES */ 1676 .get_sset_count = bcm_phy_get_sset_count, 1677 .get_strings = bcm_phy_get_strings, 1678 .get_stats = bcm54xx_get_stats, 1679 .probe = bcm54xx_phy_probe, 1680 .link_change_notify = bcm54xx_link_change_notify, 1681 .led_brightness_set = bcm_phy_led_brightness_set, 1682 }, { 1683 PHY_ID_MATCH_MODEL(PHY_ID_BCM53125), 1684 .name = "Broadcom BCM53125", 1685 .flags = PHY_IS_INTERNAL, 1686 /* PHY_GBIT_FEATURES */ 1687 .get_sset_count = bcm_phy_get_sset_count, 1688 .get_strings = bcm_phy_get_strings, 1689 .get_stats = bcm54xx_get_stats, 1690 .probe = bcm54xx_phy_probe, 1691 .config_init = bcm54xx_config_init, 1692 .config_intr = bcm_phy_config_intr, 1693 .handle_interrupt = bcm_phy_handle_interrupt, 1694 .link_change_notify = bcm54xx_link_change_notify, 1695 .led_brightness_set = bcm_phy_led_brightness_set, 1696 }, { 1697 PHY_ID_MATCH_MODEL(PHY_ID_BCM53128), 1698 .name = "Broadcom BCM53128", 1699 .flags = PHY_IS_INTERNAL, 1700 /* PHY_GBIT_FEATURES */ 1701 .get_sset_count = bcm_phy_get_sset_count, 1702 .get_strings = bcm_phy_get_strings, 1703 .get_stats = bcm54xx_get_stats, 1704 .probe = bcm54xx_phy_probe, 1705 .config_init = bcm54xx_config_init, 1706 .config_intr = bcm_phy_config_intr, 1707 .handle_interrupt = bcm_phy_handle_interrupt, 1708 .link_change_notify = bcm54xx_link_change_notify, 1709 .led_brightness_set = bcm_phy_led_brightness_set, 1710 }, { 1711 PHY_ID_MATCH_MODEL(PHY_ID_BCM89610), 1712 .name = "Broadcom BCM89610", 1713 /* PHY_GBIT_FEATURES */ 1714 .get_sset_count = bcm_phy_get_sset_count, 1715 .get_strings = bcm_phy_get_strings, 1716 .get_stats = bcm54xx_get_stats, 1717 .probe = bcm54xx_phy_probe, 1718 .config_init = bcm54xx_config_init, 1719 .config_intr = bcm_phy_config_intr, 1720 .handle_interrupt = bcm_phy_handle_interrupt, 1721 .link_change_notify = bcm54xx_link_change_notify, 1722 } }; 1723 1724 module_phy_driver(broadcom_drivers); 1725 1726 static const struct mdio_device_id __maybe_unused broadcom_tbl[] = { 1727 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5411) }, 1728 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5421) }, 1729 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54210E) }, 1730 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5461) }, 1731 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54612E) }, 1732 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54616S) }, 1733 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5464) }, 1734 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5481) }, 1735 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54810) }, 1736 { PHY_ID_MATCH_MODEL(PHY_ID_BCM54811) }, 1737 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5482) }, 1738 { PHY_ID_MATCH_MODEL(PHY_ID_BCM50610) }, 1739 { PHY_ID_MATCH_MODEL(PHY_ID_BCM50610M) }, 1740 { PHY_ID_MATCH_MODEL(PHY_ID_BCM57780) }, 1741 { PHY_ID_MATCH_MODEL(PHY_ID_BCMAC131) }, 1742 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5221) }, 1743 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5241) }, 1744 { PHY_ID_MATCH_MODEL(PHY_ID_BCM5395) }, 1745 { PHY_ID_MATCH_MODEL(PHY_ID_BCM53125) }, 1746 { PHY_ID_MATCH_MODEL(PHY_ID_BCM53128) }, 1747 { PHY_ID_MATCH_MODEL(PHY_ID_BCM89610) }, 1748 { } 1749 }; 1750 1751 MODULE_DEVICE_TABLE(mdio, broadcom_tbl); 1752