1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2011 - 2012 Cavium, Inc. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/phy.h> 8 #include <linux/of.h> 9 10 #define PHY_ID_BCM8706 0x0143bdc1 11 #define PHY_ID_BCM8727 0x0143bff0 12 13 #define BCM87XX_PMD_RX_SIGNAL_DETECT (MII_ADDR_C45 | 0x1000a) 14 #define BCM87XX_10GBASER_PCS_STATUS (MII_ADDR_C45 | 0x30020) 15 #define BCM87XX_XGXS_LANE_STATUS (MII_ADDR_C45 | 0x40018) 16 17 #define BCM87XX_LASI_CONTROL (MII_ADDR_C45 | 0x39002) 18 #define BCM87XX_LASI_STATUS (MII_ADDR_C45 | 0x39005) 19 20 #if IS_ENABLED(CONFIG_OF_MDIO) 21 /* Set and/or override some configuration registers based on the 22 * broadcom,c45-reg-init property stored in the of_node for the phydev. 23 * 24 * broadcom,c45-reg-init = <devid reg mask value>,...; 25 * 26 * There may be one or more sets of <devid reg mask value>: 27 * 28 * devid: which sub-device to use. 29 * reg: the register. 30 * mask: if non-zero, ANDed with existing register value. 31 * value: ORed with the masked value and written to the regiser. 32 * 33 */ 34 static int bcm87xx_of_reg_init(struct phy_device *phydev) 35 { 36 const __be32 *paddr; 37 const __be32 *paddr_end; 38 int len, ret; 39 40 if (!phydev->mdio.dev.of_node) 41 return 0; 42 43 paddr = of_get_property(phydev->mdio.dev.of_node, 44 "broadcom,c45-reg-init", &len); 45 if (!paddr) 46 return 0; 47 48 paddr_end = paddr + (len /= sizeof(*paddr)); 49 50 ret = 0; 51 52 while (paddr + 3 < paddr_end) { 53 u16 devid = be32_to_cpup(paddr++); 54 u16 reg = be32_to_cpup(paddr++); 55 u16 mask = be32_to_cpup(paddr++); 56 u16 val_bits = be32_to_cpup(paddr++); 57 u32 regnum = mdiobus_c45_addr(devid, reg); 58 int val = 0; 59 60 if (mask) { 61 val = phy_read(phydev, regnum); 62 if (val < 0) { 63 ret = val; 64 goto err; 65 } 66 val &= mask; 67 } 68 val |= val_bits; 69 70 ret = phy_write(phydev, regnum, val); 71 if (ret < 0) 72 goto err; 73 } 74 err: 75 return ret; 76 } 77 #else 78 static int bcm87xx_of_reg_init(struct phy_device *phydev) 79 { 80 return 0; 81 } 82 #endif /* CONFIG_OF_MDIO */ 83 84 static int bcm87xx_get_features(struct phy_device *phydev) 85 { 86 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 87 phydev->supported); 88 return 0; 89 } 90 91 static int bcm87xx_config_init(struct phy_device *phydev) 92 { 93 return bcm87xx_of_reg_init(phydev); 94 } 95 96 static int bcm87xx_config_aneg(struct phy_device *phydev) 97 { 98 return -EINVAL; 99 } 100 101 static int bcm87xx_read_status(struct phy_device *phydev) 102 { 103 int rx_signal_detect; 104 int pcs_status; 105 int xgxs_lane_status; 106 107 rx_signal_detect = phy_read(phydev, BCM87XX_PMD_RX_SIGNAL_DETECT); 108 if (rx_signal_detect < 0) 109 return rx_signal_detect; 110 111 if ((rx_signal_detect & 1) == 0) 112 goto no_link; 113 114 pcs_status = phy_read(phydev, BCM87XX_10GBASER_PCS_STATUS); 115 if (pcs_status < 0) 116 return pcs_status; 117 118 if ((pcs_status & 1) == 0) 119 goto no_link; 120 121 xgxs_lane_status = phy_read(phydev, BCM87XX_XGXS_LANE_STATUS); 122 if (xgxs_lane_status < 0) 123 return xgxs_lane_status; 124 125 if ((xgxs_lane_status & 0x1000) == 0) 126 goto no_link; 127 128 phydev->speed = 10000; 129 phydev->link = 1; 130 phydev->duplex = 1; 131 return 0; 132 133 no_link: 134 phydev->link = 0; 135 return 0; 136 } 137 138 static int bcm87xx_config_intr(struct phy_device *phydev) 139 { 140 int reg, err; 141 142 reg = phy_read(phydev, BCM87XX_LASI_CONTROL); 143 144 if (reg < 0) 145 return reg; 146 147 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 148 err = phy_read(phydev, BCM87XX_LASI_STATUS); 149 if (err) 150 return err; 151 152 reg |= 1; 153 err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg); 154 } else { 155 reg &= ~1; 156 err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg); 157 if (err) 158 return err; 159 160 err = phy_read(phydev, BCM87XX_LASI_STATUS); 161 } 162 163 return err; 164 } 165 166 static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev) 167 { 168 int irq_status; 169 170 irq_status = phy_read(phydev, BCM87XX_LASI_STATUS); 171 if (irq_status < 0) { 172 phy_error(phydev); 173 return IRQ_NONE; 174 } 175 176 if (irq_status == 0) 177 return IRQ_NONE; 178 179 phy_trigger_machine(phydev); 180 181 return IRQ_HANDLED; 182 } 183 184 static int bcm8706_match_phy_device(struct phy_device *phydev) 185 { 186 return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706; 187 } 188 189 static int bcm8727_match_phy_device(struct phy_device *phydev) 190 { 191 return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727; 192 } 193 194 static struct phy_driver bcm87xx_driver[] = { 195 { 196 .phy_id = PHY_ID_BCM8706, 197 .phy_id_mask = 0xffffffff, 198 .name = "Broadcom BCM8706", 199 .get_features = bcm87xx_get_features, 200 .config_init = bcm87xx_config_init, 201 .config_aneg = bcm87xx_config_aneg, 202 .read_status = bcm87xx_read_status, 203 .config_intr = bcm87xx_config_intr, 204 .handle_interrupt = bcm87xx_handle_interrupt, 205 .match_phy_device = bcm8706_match_phy_device, 206 }, { 207 .phy_id = PHY_ID_BCM8727, 208 .phy_id_mask = 0xffffffff, 209 .name = "Broadcom BCM8727", 210 .get_features = bcm87xx_get_features, 211 .config_init = bcm87xx_config_init, 212 .config_aneg = bcm87xx_config_aneg, 213 .read_status = bcm87xx_read_status, 214 .config_intr = bcm87xx_config_intr, 215 .handle_interrupt = bcm87xx_handle_interrupt, 216 .match_phy_device = bcm8727_match_phy_device, 217 } }; 218 219 module_phy_driver(bcm87xx_driver); 220 221 MODULE_LICENSE("GPL v2"); 222