1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY 3 * 4 * Copyright (c) 2020 Michael Walle <michael@walle.cc> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/brcmphy.h> 9 #include <linux/hwmon.h> 10 #include <linux/module.h> 11 #include <linux/phy.h> 12 13 #include "bcm-phy-lib.h" 14 15 /* RDB per-port registers 16 */ 17 #define BCM54140_RDB_ISR 0x00a /* interrupt status */ 18 #define BCM54140_RDB_IMR 0x00b /* interrupt mask */ 19 #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */ 20 #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */ 21 #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */ 22 #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */ 23 #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */ 24 #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */ 25 #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */ 26 #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */ 27 #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */ 28 #define BCM54140_RDB_SPARE3_BIT0 BIT(0) 29 #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */ 30 #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4) 31 #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8) 32 #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */ 33 #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */ 34 #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */ 35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */ 36 #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */ 37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */ 38 #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5) 39 #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */ 40 #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */ 41 #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */ 42 #define BCM54140_RDB_C_PWR 0x02a /* copper power control */ 43 #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */ 44 #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */ 45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */ 46 47 /* RDB global registers 48 */ 49 #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */ 50 #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4) 51 #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5) 52 #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6) 53 #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7) 54 #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */ 55 #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */ 56 #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1) 57 #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */ 58 #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */ 59 #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */ 60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */ 61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */ 62 #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */ 63 #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */ 64 #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */ 65 #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0) 66 #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */ 67 #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */ 68 #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */ 69 #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0) 70 #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */ 71 #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */ 72 #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */ 73 #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0) 74 #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */ 75 #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */ 76 #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */ 77 #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */ 78 79 /* According to the datasheet the formula is: 80 * T = 413.35 - (0.49055 * bits[9:0]) 81 */ 82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491) 83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491) 84 85 /* According to the datasheet the formula is: 86 * U = bits[11:0] / 1024 * 220 / 0.2 87 * 88 * Normalized: 89 * U = bits[11:0] / 4096 * 2514 90 */ 91 #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11) 92 #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514) 93 94 /* According to the datasheet the formula is: 95 * U = bits[10:0] / 1024 * 880 / 0.7 96 * 97 * Normalized: 98 * U = bits[10:0] / 2048 * 4400 99 */ 100 #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12) 101 #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400) 102 103 #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \ 104 : BCM54140_HWMON_TO_IN_1V0(v)) 105 #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \ 106 : BCM54140_HWMON_FROM_IN_1V0(v)) 107 #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \ 108 : BCM54140_RDB_MON_1V0_DATA_MASK) 109 #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \ 110 : BCM54140_RDB_MON_1V0_VAL) 111 #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \ 112 : BCM54140_RDB_MON_1V0_MIN) 113 #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \ 114 : BCM54140_RDB_MON_1V0_MAX) 115 #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \ 116 : BCM54140_RDB_MON_ISR_1V0) 117 118 /* This PHY has two different PHY IDs depening on its MODE_SEL pin. This 119 * pin choses between 4x SGMII and QSGMII mode: 120 * AE02_5009 4x SGMII 121 * AE02_5019 QSGMII 122 */ 123 #define BCM54140_PHY_ID_MASK 0xffffffe8 124 125 #define BCM54140_PHY_ID_REV(phy_id) ((phy_id) & 0x7) 126 #define BCM54140_REV_B0 1 127 128 #define BCM54140_DEFAULT_DOWNSHIFT 5 129 #define BCM54140_MAX_DOWNSHIFT 9 130 131 struct bcm54140_priv { 132 int port; 133 int base_addr; 134 #if IS_ENABLED(CONFIG_HWMON) 135 bool pkg_init; 136 /* protect the alarm bits */ 137 struct mutex alarm_lock; 138 u16 alarm; 139 #endif 140 }; 141 142 #if IS_ENABLED(CONFIG_HWMON) 143 static umode_t bcm54140_hwmon_is_visible(const void *data, 144 enum hwmon_sensor_types type, 145 u32 attr, int channel) 146 { 147 switch (type) { 148 case hwmon_in: 149 switch (attr) { 150 case hwmon_in_min: 151 case hwmon_in_max: 152 return 0644; 153 case hwmon_in_label: 154 case hwmon_in_input: 155 case hwmon_in_alarm: 156 return 0444; 157 default: 158 return 0; 159 } 160 case hwmon_temp: 161 switch (attr) { 162 case hwmon_temp_min: 163 case hwmon_temp_max: 164 return 0644; 165 case hwmon_temp_input: 166 case hwmon_temp_alarm: 167 return 0444; 168 default: 169 return 0; 170 } 171 default: 172 return 0; 173 } 174 } 175 176 static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit, 177 long *val) 178 { 179 struct phy_device *phydev = dev_get_drvdata(dev); 180 struct bcm54140_priv *priv = phydev->priv; 181 int tmp, ret = 0; 182 183 mutex_lock(&priv->alarm_lock); 184 185 /* latch any alarm bits */ 186 tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR); 187 if (tmp < 0) { 188 ret = tmp; 189 goto out; 190 } 191 priv->alarm |= tmp; 192 193 *val = !!(priv->alarm & bit); 194 priv->alarm &= ~bit; 195 196 out: 197 mutex_unlock(&priv->alarm_lock); 198 return ret; 199 } 200 201 static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val) 202 { 203 struct phy_device *phydev = dev_get_drvdata(dev); 204 u16 reg; 205 int tmp; 206 207 switch (attr) { 208 case hwmon_temp_input: 209 reg = BCM54140_RDB_MON_TEMP_VAL; 210 break; 211 case hwmon_temp_min: 212 reg = BCM54140_RDB_MON_TEMP_MIN; 213 break; 214 case hwmon_temp_max: 215 reg = BCM54140_RDB_MON_TEMP_MAX; 216 break; 217 case hwmon_temp_alarm: 218 return bcm54140_hwmon_read_alarm(dev, 219 BCM54140_RDB_MON_ISR_TEMP, 220 val); 221 default: 222 return -EOPNOTSUPP; 223 } 224 225 tmp = bcm_phy_read_rdb(phydev, reg); 226 if (tmp < 0) 227 return tmp; 228 229 *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK); 230 231 return 0; 232 } 233 234 static int bcm54140_hwmon_read_in(struct device *dev, u32 attr, 235 int channel, long *val) 236 { 237 struct phy_device *phydev = dev_get_drvdata(dev); 238 u16 bit, reg; 239 int tmp; 240 241 switch (attr) { 242 case hwmon_in_input: 243 reg = BCM54140_HWMON_IN_VAL_REG(channel); 244 break; 245 case hwmon_in_min: 246 reg = BCM54140_HWMON_IN_MIN_REG(channel); 247 break; 248 case hwmon_in_max: 249 reg = BCM54140_HWMON_IN_MAX_REG(channel); 250 break; 251 case hwmon_in_alarm: 252 bit = BCM54140_HWMON_IN_ALARM_BIT(channel); 253 return bcm54140_hwmon_read_alarm(dev, bit, val); 254 default: 255 return -EOPNOTSUPP; 256 } 257 258 tmp = bcm_phy_read_rdb(phydev, reg); 259 if (tmp < 0) 260 return tmp; 261 262 tmp &= BCM54140_HWMON_IN_MASK(channel); 263 *val = BCM54140_HWMON_TO_IN(channel, tmp); 264 265 return 0; 266 } 267 268 static int bcm54140_hwmon_read(struct device *dev, 269 enum hwmon_sensor_types type, u32 attr, 270 int channel, long *val) 271 { 272 switch (type) { 273 case hwmon_temp: 274 return bcm54140_hwmon_read_temp(dev, attr, val); 275 case hwmon_in: 276 return bcm54140_hwmon_read_in(dev, attr, channel, val); 277 default: 278 return -EOPNOTSUPP; 279 } 280 } 281 282 static const char *const bcm54140_hwmon_in_labels[] = { 283 "AVDDL", 284 "AVDDH", 285 }; 286 287 static int bcm54140_hwmon_read_string(struct device *dev, 288 enum hwmon_sensor_types type, u32 attr, 289 int channel, const char **str) 290 { 291 switch (type) { 292 case hwmon_in: 293 switch (attr) { 294 case hwmon_in_label: 295 *str = bcm54140_hwmon_in_labels[channel]; 296 return 0; 297 default: 298 return -EOPNOTSUPP; 299 } 300 default: 301 return -EOPNOTSUPP; 302 } 303 } 304 305 static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr, 306 int channel, long val) 307 { 308 struct phy_device *phydev = dev_get_drvdata(dev); 309 u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK; 310 u16 reg; 311 312 val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask), 313 BCM54140_HWMON_TO_TEMP(0)); 314 315 switch (attr) { 316 case hwmon_temp_min: 317 reg = BCM54140_RDB_MON_TEMP_MIN; 318 break; 319 case hwmon_temp_max: 320 reg = BCM54140_RDB_MON_TEMP_MAX; 321 break; 322 default: 323 return -EOPNOTSUPP; 324 } 325 326 return bcm_phy_modify_rdb(phydev, reg, mask, 327 BCM54140_HWMON_FROM_TEMP(val)); 328 } 329 330 static int bcm54140_hwmon_write_in(struct device *dev, u32 attr, 331 int channel, long val) 332 { 333 struct phy_device *phydev = dev_get_drvdata(dev); 334 u16 mask = BCM54140_HWMON_IN_MASK(channel); 335 u16 reg; 336 337 val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask)); 338 339 switch (attr) { 340 case hwmon_in_min: 341 reg = BCM54140_HWMON_IN_MIN_REG(channel); 342 break; 343 case hwmon_in_max: 344 reg = BCM54140_HWMON_IN_MAX_REG(channel); 345 break; 346 default: 347 return -EOPNOTSUPP; 348 } 349 350 return bcm_phy_modify_rdb(phydev, reg, mask, 351 BCM54140_HWMON_FROM_IN(channel, val)); 352 } 353 354 static int bcm54140_hwmon_write(struct device *dev, 355 enum hwmon_sensor_types type, u32 attr, 356 int channel, long val) 357 { 358 switch (type) { 359 case hwmon_temp: 360 return bcm54140_hwmon_write_temp(dev, attr, channel, val); 361 case hwmon_in: 362 return bcm54140_hwmon_write_in(dev, attr, channel, val); 363 default: 364 return -EOPNOTSUPP; 365 } 366 } 367 368 static const struct hwmon_channel_info *bcm54140_hwmon_info[] = { 369 HWMON_CHANNEL_INFO(temp, 370 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | 371 HWMON_T_ALARM), 372 HWMON_CHANNEL_INFO(in, 373 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 374 HWMON_I_ALARM | HWMON_I_LABEL, 375 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 376 HWMON_I_ALARM | HWMON_I_LABEL), 377 NULL 378 }; 379 380 static const struct hwmon_ops bcm54140_hwmon_ops = { 381 .is_visible = bcm54140_hwmon_is_visible, 382 .read = bcm54140_hwmon_read, 383 .read_string = bcm54140_hwmon_read_string, 384 .write = bcm54140_hwmon_write, 385 }; 386 387 static const struct hwmon_chip_info bcm54140_chip_info = { 388 .ops = &bcm54140_hwmon_ops, 389 .info = bcm54140_hwmon_info, 390 }; 391 392 static int bcm54140_enable_monitoring(struct phy_device *phydev) 393 { 394 u16 mask, set; 395 396 /* 3.3V voltage mode */ 397 set = BCM54140_RDB_MON_CTRL_V_MODE; 398 399 /* select round-robin */ 400 mask = BCM54140_RDB_MON_CTRL_SEL_MASK; 401 set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK, 402 BCM54140_RDB_MON_CTRL_SEL_RR); 403 404 /* remove power-down bit */ 405 mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN; 406 407 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set); 408 } 409 410 /* Check if one PHY has already done the init of the parts common to all PHYs 411 * in the Quad PHY package. 412 */ 413 static bool bcm54140_is_pkg_init(struct phy_device *phydev) 414 { 415 struct bcm54140_priv *priv = phydev->priv; 416 struct mii_bus *bus = phydev->mdio.bus; 417 int base_addr = priv->base_addr; 418 struct phy_device *phy; 419 int i; 420 421 /* Quad PHY */ 422 for (i = 0; i < 4; i++) { 423 phy = mdiobus_get_phy(bus, base_addr + i); 424 if (!phy) 425 continue; 426 427 if ((phy->phy_id & phydev->drv->phy_id_mask) != 428 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) 429 continue; 430 431 priv = phy->priv; 432 433 if (priv && priv->pkg_init) 434 return true; 435 } 436 437 return false; 438 } 439 440 static int bcm54140_probe_once(struct phy_device *phydev) 441 { 442 struct device *hwmon; 443 int ret; 444 445 /* enable hardware monitoring */ 446 ret = bcm54140_enable_monitoring(phydev); 447 if (ret) 448 return ret; 449 450 hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev, 451 "BCM54140", phydev, 452 &bcm54140_chip_info, 453 NULL); 454 return PTR_ERR_OR_ZERO(hwmon); 455 } 456 #endif 457 458 static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb) 459 { 460 struct bcm54140_priv *priv = phydev->priv; 461 struct mii_bus *bus = phydev->mdio.bus; 462 int ret; 463 464 mutex_lock(&bus->mdio_lock); 465 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 466 if (ret < 0) 467 goto out; 468 469 ret = __mdiobus_read(bus, priv->base_addr, MII_BCM54XX_RDB_DATA); 470 471 out: 472 mutex_unlock(&bus->mdio_lock); 473 return ret; 474 } 475 476 static int bcm54140_base_write_rdb(struct phy_device *phydev, 477 u16 rdb, u16 val) 478 { 479 struct bcm54140_priv *priv = phydev->priv; 480 struct mii_bus *bus = phydev->mdio.bus; 481 int ret; 482 483 mutex_lock(&bus->mdio_lock); 484 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 485 if (ret < 0) 486 goto out; 487 488 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_DATA, val); 489 490 out: 491 mutex_unlock(&bus->mdio_lock); 492 return ret; 493 } 494 495 /* Under some circumstances a core PLL may not lock, this will then prevent 496 * a successful link establishment. Restart the PLL after the voltages are 497 * stable to workaround this issue. 498 */ 499 static int bcm54140_b0_workaround(struct phy_device *phydev) 500 { 501 int spare3; 502 int ret; 503 504 spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3); 505 if (spare3 < 0) 506 return spare3; 507 508 spare3 &= ~BCM54140_RDB_SPARE3_BIT0; 509 510 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 511 if (ret) 512 return ret; 513 514 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 515 if (ret) 516 return ret; 517 518 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 519 if (ret) 520 return ret; 521 522 spare3 |= BCM54140_RDB_SPARE3_BIT0; 523 524 return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 525 } 526 527 /* The BCM54140 is a quad PHY where only the first port has access to the 528 * global register. Thus we need to find out its PHY address. 529 * 530 */ 531 static int bcm54140_get_base_addr_and_port(struct phy_device *phydev) 532 { 533 struct bcm54140_priv *priv = phydev->priv; 534 struct mii_bus *bus = phydev->mdio.bus; 535 int addr, min_addr, max_addr; 536 int step = 1; 537 u32 phy_id; 538 int tmp; 539 540 min_addr = phydev->mdio.addr; 541 max_addr = phydev->mdio.addr; 542 addr = phydev->mdio.addr; 543 544 /* We scan forward and backwards and look for PHYs which have the 545 * same phy_id like we do. Step 1 will scan forward, step 2 546 * backwards. Once we are finished, we have a min_addr and 547 * max_addr which resembles the range of PHY addresses of the same 548 * type of PHY. There is one caveat; there may be many PHYs of 549 * the same type, but we know that each PHY takes exactly 4 550 * consecutive addresses. Therefore we can deduce our offset 551 * to the base address of this quad PHY. 552 */ 553 554 while (1) { 555 if (step == 3) { 556 break; 557 } else if (step == 1) { 558 max_addr = addr; 559 addr++; 560 } else { 561 min_addr = addr; 562 addr--; 563 } 564 565 if (addr < 0 || addr >= PHY_MAX_ADDR) { 566 addr = phydev->mdio.addr; 567 step++; 568 continue; 569 } 570 571 /* read the PHY id */ 572 tmp = mdiobus_read(bus, addr, MII_PHYSID1); 573 if (tmp < 0) 574 return tmp; 575 phy_id = tmp << 16; 576 tmp = mdiobus_read(bus, addr, MII_PHYSID2); 577 if (tmp < 0) 578 return tmp; 579 phy_id |= tmp; 580 581 /* see if it is still the same PHY */ 582 if ((phy_id & phydev->drv->phy_id_mask) != 583 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) { 584 addr = phydev->mdio.addr; 585 step++; 586 } 587 } 588 589 /* The range we get should be a multiple of four. Please note that both 590 * the min_addr and max_addr are inclusive. So we have to add one if we 591 * subtract them. 592 */ 593 if ((max_addr - min_addr + 1) % 4) { 594 dev_err(&phydev->mdio.dev, 595 "Detected Quad PHY IDs %d..%d doesn't make sense.\n", 596 min_addr, max_addr); 597 return -EINVAL; 598 } 599 600 priv->port = (phydev->mdio.addr - min_addr) % 4; 601 priv->base_addr = phydev->mdio.addr - priv->port; 602 603 return 0; 604 } 605 606 static int bcm54140_probe(struct phy_device *phydev) 607 { 608 struct bcm54140_priv *priv; 609 int ret; 610 611 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 612 if (!priv) 613 return -ENOMEM; 614 615 phydev->priv = priv; 616 617 ret = bcm54140_get_base_addr_and_port(phydev); 618 if (ret) 619 return ret; 620 621 #if IS_ENABLED(CONFIG_HWMON) 622 mutex_init(&priv->alarm_lock); 623 624 if (!bcm54140_is_pkg_init(phydev)) { 625 ret = bcm54140_probe_once(phydev); 626 if (ret) 627 return ret; 628 } 629 630 priv->pkg_init = true; 631 #endif 632 633 phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n", 634 priv->port, priv->base_addr); 635 636 return 0; 637 } 638 639 static int bcm54140_config_init(struct phy_device *phydev) 640 { 641 u16 reg = 0xffff; 642 int ret; 643 644 /* Apply hardware errata */ 645 if (BCM54140_PHY_ID_REV(phydev->phy_id) == BCM54140_REV_B0) { 646 ret = bcm54140_b0_workaround(phydev); 647 if (ret) 648 return ret; 649 } 650 651 /* Unmask events we are interested in. */ 652 reg &= ~(BCM54140_RDB_INT_DUPLEX | 653 BCM54140_RDB_INT_SPEED | 654 BCM54140_RDB_INT_LINK); 655 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg); 656 if (ret) 657 return ret; 658 659 /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */ 660 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1, 661 0, BCM54140_RDB_SPARE1_LSLM); 662 if (ret) 663 return ret; 664 665 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL, 666 0, BCM54140_RDB_LED_CTRL_ACTLINK0); 667 if (ret) 668 return ret; 669 670 /* disable super isolate mode */ 671 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR, 672 BCM54140_RDB_C_PWR_ISOLATE, 0); 673 } 674 675 static int bcm54140_did_interrupt(struct phy_device *phydev) 676 { 677 int ret; 678 679 ret = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 680 681 return (ret < 0) ? 0 : ret; 682 } 683 684 static int bcm54140_ack_intr(struct phy_device *phydev) 685 { 686 int reg; 687 688 /* clear pending interrupts */ 689 reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 690 if (reg < 0) 691 return reg; 692 693 return 0; 694 } 695 696 static int bcm54140_config_intr(struct phy_device *phydev) 697 { 698 struct bcm54140_priv *priv = phydev->priv; 699 static const u16 port_to_imr_bit[] = { 700 BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1, 701 BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3, 702 }; 703 int reg; 704 705 if (priv->port >= ARRAY_SIZE(port_to_imr_bit)) 706 return -EINVAL; 707 708 reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR); 709 if (reg < 0) 710 return reg; 711 712 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 713 reg &= ~port_to_imr_bit[priv->port]; 714 else 715 reg |= port_to_imr_bit[priv->port]; 716 717 return bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg); 718 } 719 720 static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data) 721 { 722 int val; 723 724 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL); 725 if (val < 0) 726 return val; 727 728 if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) { 729 *data = DOWNSHIFT_DEV_DISABLE; 730 return 0; 731 } 732 733 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2); 734 if (val < 0) 735 return val; 736 737 if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS) 738 *data = 1; 739 else 740 *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2; 741 742 return 0; 743 } 744 745 static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt) 746 { 747 u16 mask, set; 748 int ret; 749 750 if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT) 751 return -EINVAL; 752 753 if (!cnt) 754 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 755 BCM54140_RDB_C_MISC_CTRL_WS_EN, 0); 756 757 if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT) 758 cnt = BCM54140_DEFAULT_DOWNSHIFT; 759 760 if (cnt == 1) { 761 mask = 0; 762 set = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 763 } else { 764 mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 765 mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT; 766 set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2); 767 } 768 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2, 769 mask, set); 770 if (ret) 771 return ret; 772 773 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 774 0, BCM54140_RDB_C_MISC_CTRL_WS_EN); 775 } 776 777 static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval) 778 { 779 int val; 780 781 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR); 782 if (val < 0) 783 return val; 784 785 switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) { 786 case BCM54140_RDB_C_APWR_APD_MODE_DIS: 787 case BCM54140_RDB_C_APWR_APD_MODE_DIS2: 788 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE; 789 break; 790 case BCM54140_RDB_C_APWR_APD_MODE_EN: 791 case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG: 792 switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) { 793 case BCM54140_RDB_C_APWR_SLP_TIM_2_7: 794 *tx_interval = 2700; 795 break; 796 case BCM54140_RDB_C_APWR_SLP_TIM_5_4: 797 *tx_interval = 5400; 798 break; 799 } 800 } 801 802 return 0; 803 } 804 805 static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval) 806 { 807 u16 mask, set; 808 809 mask = BCM54140_RDB_C_APWR_APD_MODE_MASK; 810 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE) 811 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 812 BCM54140_RDB_C_APWR_APD_MODE_DIS); 813 else 814 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 815 BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG); 816 817 /* enable single pulse mode */ 818 set |= BCM54140_RDB_C_APWR_SINGLE_PULSE; 819 820 /* set sleep timer */ 821 mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK; 822 switch (tx_interval) { 823 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 824 case ETHTOOL_PHY_EDPD_DISABLE: 825 case 2700: 826 set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7; 827 break; 828 case 5400: 829 set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4; 830 break; 831 default: 832 return -EINVAL; 833 } 834 835 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set); 836 } 837 838 static int bcm54140_get_tunable(struct phy_device *phydev, 839 struct ethtool_tunable *tuna, void *data) 840 { 841 switch (tuna->id) { 842 case ETHTOOL_PHY_DOWNSHIFT: 843 return bcm54140_get_downshift(phydev, data); 844 case ETHTOOL_PHY_EDPD: 845 return bcm54140_get_edpd(phydev, data); 846 default: 847 return -EOPNOTSUPP; 848 } 849 } 850 851 static int bcm54140_set_tunable(struct phy_device *phydev, 852 struct ethtool_tunable *tuna, const void *data) 853 { 854 switch (tuna->id) { 855 case ETHTOOL_PHY_DOWNSHIFT: 856 return bcm54140_set_downshift(phydev, *(const u8 *)data); 857 case ETHTOOL_PHY_EDPD: 858 return bcm54140_set_edpd(phydev, *(const u16 *)data); 859 default: 860 return -EOPNOTSUPP; 861 } 862 } 863 864 static struct phy_driver bcm54140_drivers[] = { 865 { 866 .phy_id = PHY_ID_BCM54140, 867 .phy_id_mask = BCM54140_PHY_ID_MASK, 868 .name = "Broadcom BCM54140", 869 .features = PHY_GBIT_FEATURES, 870 .config_init = bcm54140_config_init, 871 .did_interrupt = bcm54140_did_interrupt, 872 .ack_interrupt = bcm54140_ack_intr, 873 .config_intr = bcm54140_config_intr, 874 .probe = bcm54140_probe, 875 .suspend = genphy_suspend, 876 .resume = genphy_resume, 877 .soft_reset = genphy_soft_reset, 878 .get_tunable = bcm54140_get_tunable, 879 .set_tunable = bcm54140_set_tunable, 880 }, 881 }; 882 module_phy_driver(bcm54140_drivers); 883 884 static struct mdio_device_id __maybe_unused bcm54140_tbl[] = { 885 { PHY_ID_BCM54140, BCM54140_PHY_ID_MASK }, 886 { } 887 }; 888 889 MODULE_AUTHOR("Michael Walle"); 890 MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver"); 891 MODULE_DEVICE_TABLE(mdio, bcm54140_tbl); 892 MODULE_LICENSE("GPL"); 893