1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY 3 * 4 * Copyright (c) 2020 Michael Walle <michael@walle.cc> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/brcmphy.h> 9 #include <linux/hwmon.h> 10 #include <linux/module.h> 11 #include <linux/phy.h> 12 13 #include "bcm-phy-lib.h" 14 15 /* RDB per-port registers 16 */ 17 #define BCM54140_RDB_ISR 0x00a /* interrupt status */ 18 #define BCM54140_RDB_IMR 0x00b /* interrupt mask */ 19 #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */ 20 #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */ 21 #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */ 22 #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */ 23 #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */ 24 #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */ 25 #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */ 26 #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */ 27 #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */ 28 #define BCM54140_RDB_SPARE3_BIT0 BIT(0) 29 #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */ 30 #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4) 31 #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8) 32 #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */ 33 #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */ 34 #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */ 35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */ 36 #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */ 37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */ 38 #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5) 39 #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */ 40 #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */ 41 #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */ 42 #define BCM54140_RDB_C_PWR 0x02a /* copper power control */ 43 #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */ 44 #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */ 45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */ 46 47 /* RDB global registers 48 */ 49 #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */ 50 #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4) 51 #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5) 52 #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6) 53 #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7) 54 #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */ 55 #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */ 56 #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1) 57 #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */ 58 #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */ 59 #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */ 60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */ 61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */ 62 #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */ 63 #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */ 64 #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */ 65 #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0) 66 #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */ 67 #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */ 68 #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */ 69 #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0) 70 #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */ 71 #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */ 72 #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */ 73 #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0) 74 #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */ 75 #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */ 76 #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */ 77 #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */ 78 79 /* According to the datasheet the formula is: 80 * T = 413.35 - (0.49055 * bits[9:0]) 81 */ 82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491) 83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491) 84 85 /* According to the datasheet the formula is: 86 * U = bits[11:0] / 1024 * 220 / 0.2 87 * 88 * Normalized: 89 * U = bits[11:0] / 4096 * 2514 90 */ 91 #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11) 92 #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514) 93 94 /* According to the datasheet the formula is: 95 * U = bits[10:0] / 1024 * 880 / 0.7 96 * 97 * Normalized: 98 * U = bits[10:0] / 2048 * 4400 99 */ 100 #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12) 101 #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400) 102 103 #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \ 104 : BCM54140_HWMON_TO_IN_1V0(v)) 105 #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \ 106 : BCM54140_HWMON_FROM_IN_1V0(v)) 107 #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \ 108 : BCM54140_RDB_MON_1V0_DATA_MASK) 109 #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \ 110 : BCM54140_RDB_MON_1V0_VAL) 111 #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \ 112 : BCM54140_RDB_MON_1V0_MIN) 113 #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \ 114 : BCM54140_RDB_MON_1V0_MAX) 115 #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \ 116 : BCM54140_RDB_MON_ISR_1V0) 117 118 #define BCM54140_DEFAULT_DOWNSHIFT 5 119 #define BCM54140_MAX_DOWNSHIFT 9 120 121 struct bcm54140_priv { 122 int port; 123 int base_addr; 124 #if IS_ENABLED(CONFIG_HWMON) 125 bool pkg_init; 126 /* protect the alarm bits */ 127 struct mutex alarm_lock; 128 u16 alarm; 129 #endif 130 }; 131 132 #if IS_ENABLED(CONFIG_HWMON) 133 static umode_t bcm54140_hwmon_is_visible(const void *data, 134 enum hwmon_sensor_types type, 135 u32 attr, int channel) 136 { 137 switch (type) { 138 case hwmon_in: 139 switch (attr) { 140 case hwmon_in_min: 141 case hwmon_in_max: 142 return 0644; 143 case hwmon_in_label: 144 case hwmon_in_input: 145 case hwmon_in_alarm: 146 return 0444; 147 default: 148 return 0; 149 } 150 case hwmon_temp: 151 switch (attr) { 152 case hwmon_temp_min: 153 case hwmon_temp_max: 154 return 0644; 155 case hwmon_temp_input: 156 case hwmon_temp_alarm: 157 return 0444; 158 default: 159 return 0; 160 } 161 default: 162 return 0; 163 } 164 } 165 166 static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit, 167 long *val) 168 { 169 struct phy_device *phydev = dev_get_drvdata(dev); 170 struct bcm54140_priv *priv = phydev->priv; 171 int tmp, ret = 0; 172 173 mutex_lock(&priv->alarm_lock); 174 175 /* latch any alarm bits */ 176 tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR); 177 if (tmp < 0) { 178 ret = tmp; 179 goto out; 180 } 181 priv->alarm |= tmp; 182 183 *val = !!(priv->alarm & bit); 184 priv->alarm &= ~bit; 185 186 out: 187 mutex_unlock(&priv->alarm_lock); 188 return ret; 189 } 190 191 static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val) 192 { 193 struct phy_device *phydev = dev_get_drvdata(dev); 194 u16 reg; 195 int tmp; 196 197 switch (attr) { 198 case hwmon_temp_input: 199 reg = BCM54140_RDB_MON_TEMP_VAL; 200 break; 201 case hwmon_temp_min: 202 reg = BCM54140_RDB_MON_TEMP_MIN; 203 break; 204 case hwmon_temp_max: 205 reg = BCM54140_RDB_MON_TEMP_MAX; 206 break; 207 case hwmon_temp_alarm: 208 return bcm54140_hwmon_read_alarm(dev, 209 BCM54140_RDB_MON_ISR_TEMP, 210 val); 211 default: 212 return -EOPNOTSUPP; 213 } 214 215 tmp = bcm_phy_read_rdb(phydev, reg); 216 if (tmp < 0) 217 return tmp; 218 219 *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK); 220 221 return 0; 222 } 223 224 static int bcm54140_hwmon_read_in(struct device *dev, u32 attr, 225 int channel, long *val) 226 { 227 struct phy_device *phydev = dev_get_drvdata(dev); 228 u16 bit, reg; 229 int tmp; 230 231 switch (attr) { 232 case hwmon_in_input: 233 reg = BCM54140_HWMON_IN_VAL_REG(channel); 234 break; 235 case hwmon_in_min: 236 reg = BCM54140_HWMON_IN_MIN_REG(channel); 237 break; 238 case hwmon_in_max: 239 reg = BCM54140_HWMON_IN_MAX_REG(channel); 240 break; 241 case hwmon_in_alarm: 242 bit = BCM54140_HWMON_IN_ALARM_BIT(channel); 243 return bcm54140_hwmon_read_alarm(dev, bit, val); 244 default: 245 return -EOPNOTSUPP; 246 } 247 248 tmp = bcm_phy_read_rdb(phydev, reg); 249 if (tmp < 0) 250 return tmp; 251 252 tmp &= BCM54140_HWMON_IN_MASK(channel); 253 *val = BCM54140_HWMON_TO_IN(channel, tmp); 254 255 return 0; 256 } 257 258 static int bcm54140_hwmon_read(struct device *dev, 259 enum hwmon_sensor_types type, u32 attr, 260 int channel, long *val) 261 { 262 switch (type) { 263 case hwmon_temp: 264 return bcm54140_hwmon_read_temp(dev, attr, val); 265 case hwmon_in: 266 return bcm54140_hwmon_read_in(dev, attr, channel, val); 267 default: 268 return -EOPNOTSUPP; 269 } 270 } 271 272 static const char *const bcm54140_hwmon_in_labels[] = { 273 "AVDDL", 274 "AVDDH", 275 }; 276 277 static int bcm54140_hwmon_read_string(struct device *dev, 278 enum hwmon_sensor_types type, u32 attr, 279 int channel, const char **str) 280 { 281 switch (type) { 282 case hwmon_in: 283 switch (attr) { 284 case hwmon_in_label: 285 *str = bcm54140_hwmon_in_labels[channel]; 286 return 0; 287 default: 288 return -EOPNOTSUPP; 289 } 290 default: 291 return -EOPNOTSUPP; 292 } 293 } 294 295 static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr, 296 int channel, long val) 297 { 298 struct phy_device *phydev = dev_get_drvdata(dev); 299 u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK; 300 u16 reg; 301 302 val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask), 303 BCM54140_HWMON_TO_TEMP(0)); 304 305 switch (attr) { 306 case hwmon_temp_min: 307 reg = BCM54140_RDB_MON_TEMP_MIN; 308 break; 309 case hwmon_temp_max: 310 reg = BCM54140_RDB_MON_TEMP_MAX; 311 break; 312 default: 313 return -EOPNOTSUPP; 314 } 315 316 return bcm_phy_modify_rdb(phydev, reg, mask, 317 BCM54140_HWMON_FROM_TEMP(val)); 318 } 319 320 static int bcm54140_hwmon_write_in(struct device *dev, u32 attr, 321 int channel, long val) 322 { 323 struct phy_device *phydev = dev_get_drvdata(dev); 324 u16 mask = BCM54140_HWMON_IN_MASK(channel); 325 u16 reg; 326 327 val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask)); 328 329 switch (attr) { 330 case hwmon_in_min: 331 reg = BCM54140_HWMON_IN_MIN_REG(channel); 332 break; 333 case hwmon_in_max: 334 reg = BCM54140_HWMON_IN_MAX_REG(channel); 335 break; 336 default: 337 return -EOPNOTSUPP; 338 } 339 340 return bcm_phy_modify_rdb(phydev, reg, mask, 341 BCM54140_HWMON_FROM_IN(channel, val)); 342 } 343 344 static int bcm54140_hwmon_write(struct device *dev, 345 enum hwmon_sensor_types type, u32 attr, 346 int channel, long val) 347 { 348 switch (type) { 349 case hwmon_temp: 350 return bcm54140_hwmon_write_temp(dev, attr, channel, val); 351 case hwmon_in: 352 return bcm54140_hwmon_write_in(dev, attr, channel, val); 353 default: 354 return -EOPNOTSUPP; 355 } 356 } 357 358 static const struct hwmon_channel_info *bcm54140_hwmon_info[] = { 359 HWMON_CHANNEL_INFO(temp, 360 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | 361 HWMON_T_ALARM), 362 HWMON_CHANNEL_INFO(in, 363 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 364 HWMON_I_ALARM | HWMON_I_LABEL, 365 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 366 HWMON_I_ALARM | HWMON_I_LABEL), 367 NULL 368 }; 369 370 static const struct hwmon_ops bcm54140_hwmon_ops = { 371 .is_visible = bcm54140_hwmon_is_visible, 372 .read = bcm54140_hwmon_read, 373 .read_string = bcm54140_hwmon_read_string, 374 .write = bcm54140_hwmon_write, 375 }; 376 377 static const struct hwmon_chip_info bcm54140_chip_info = { 378 .ops = &bcm54140_hwmon_ops, 379 .info = bcm54140_hwmon_info, 380 }; 381 382 static int bcm54140_enable_monitoring(struct phy_device *phydev) 383 { 384 u16 mask, set; 385 386 /* 3.3V voltage mode */ 387 set = BCM54140_RDB_MON_CTRL_V_MODE; 388 389 /* select round-robin */ 390 mask = BCM54140_RDB_MON_CTRL_SEL_MASK; 391 set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK, 392 BCM54140_RDB_MON_CTRL_SEL_RR); 393 394 /* remove power-down bit */ 395 mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN; 396 397 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set); 398 } 399 400 /* Check if one PHY has already done the init of the parts common to all PHYs 401 * in the Quad PHY package. 402 */ 403 static bool bcm54140_is_pkg_init(struct phy_device *phydev) 404 { 405 struct bcm54140_priv *priv = phydev->priv; 406 struct mii_bus *bus = phydev->mdio.bus; 407 int base_addr = priv->base_addr; 408 struct phy_device *phy; 409 int i; 410 411 /* Quad PHY */ 412 for (i = 0; i < 4; i++) { 413 phy = mdiobus_get_phy(bus, base_addr + i); 414 if (!phy) 415 continue; 416 417 if ((phy->phy_id & phydev->drv->phy_id_mask) != 418 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) 419 continue; 420 421 priv = phy->priv; 422 423 if (priv && priv->pkg_init) 424 return true; 425 } 426 427 return false; 428 } 429 430 static int bcm54140_probe_once(struct phy_device *phydev) 431 { 432 struct device *hwmon; 433 int ret; 434 435 /* enable hardware monitoring */ 436 ret = bcm54140_enable_monitoring(phydev); 437 if (ret) 438 return ret; 439 440 hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev, 441 "BCM54140", phydev, 442 &bcm54140_chip_info, 443 NULL); 444 return PTR_ERR_OR_ZERO(hwmon); 445 } 446 #endif 447 448 static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb) 449 { 450 struct bcm54140_priv *priv = phydev->priv; 451 struct mii_bus *bus = phydev->mdio.bus; 452 int ret; 453 454 mutex_lock(&bus->mdio_lock); 455 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 456 if (ret < 0) 457 goto out; 458 459 ret = __mdiobus_read(bus, priv->base_addr, MII_BCM54XX_RDB_DATA); 460 461 out: 462 mutex_unlock(&bus->mdio_lock); 463 return ret; 464 } 465 466 static int bcm54140_base_write_rdb(struct phy_device *phydev, 467 u16 rdb, u16 val) 468 { 469 struct bcm54140_priv *priv = phydev->priv; 470 struct mii_bus *bus = phydev->mdio.bus; 471 int ret; 472 473 mutex_lock(&bus->mdio_lock); 474 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 475 if (ret < 0) 476 goto out; 477 478 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_DATA, val); 479 480 out: 481 mutex_unlock(&bus->mdio_lock); 482 return ret; 483 } 484 485 /* Under some circumstances a core PLL may not lock, this will then prevent 486 * a successful link establishment. Restart the PLL after the voltages are 487 * stable to workaround this issue. 488 */ 489 static int bcm54140_b0_workaround(struct phy_device *phydev) 490 { 491 int spare3; 492 int ret; 493 494 spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3); 495 if (spare3 < 0) 496 return spare3; 497 498 spare3 &= ~BCM54140_RDB_SPARE3_BIT0; 499 500 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 501 if (ret) 502 return ret; 503 504 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 505 if (ret) 506 return ret; 507 508 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 509 if (ret) 510 return ret; 511 512 spare3 |= BCM54140_RDB_SPARE3_BIT0; 513 514 return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 515 } 516 517 /* The BCM54140 is a quad PHY where only the first port has access to the 518 * global register. Thus we need to find out its PHY address. 519 * 520 */ 521 static int bcm54140_get_base_addr_and_port(struct phy_device *phydev) 522 { 523 struct bcm54140_priv *priv = phydev->priv; 524 struct mii_bus *bus = phydev->mdio.bus; 525 int addr, min_addr, max_addr; 526 int step = 1; 527 u32 phy_id; 528 int tmp; 529 530 min_addr = phydev->mdio.addr; 531 max_addr = phydev->mdio.addr; 532 addr = phydev->mdio.addr; 533 534 /* We scan forward and backwards and look for PHYs which have the 535 * same phy_id like we do. Step 1 will scan forward, step 2 536 * backwards. Once we are finished, we have a min_addr and 537 * max_addr which resembles the range of PHY addresses of the same 538 * type of PHY. There is one caveat; there may be many PHYs of 539 * the same type, but we know that each PHY takes exactly 4 540 * consecutive addresses. Therefore we can deduce our offset 541 * to the base address of this quad PHY. 542 */ 543 544 while (1) { 545 if (step == 3) { 546 break; 547 } else if (step == 1) { 548 max_addr = addr; 549 addr++; 550 } else { 551 min_addr = addr; 552 addr--; 553 } 554 555 if (addr < 0 || addr >= PHY_MAX_ADDR) { 556 addr = phydev->mdio.addr; 557 step++; 558 continue; 559 } 560 561 /* read the PHY id */ 562 tmp = mdiobus_read(bus, addr, MII_PHYSID1); 563 if (tmp < 0) 564 return tmp; 565 phy_id = tmp << 16; 566 tmp = mdiobus_read(bus, addr, MII_PHYSID2); 567 if (tmp < 0) 568 return tmp; 569 phy_id |= tmp; 570 571 /* see if it is still the same PHY */ 572 if ((phy_id & phydev->drv->phy_id_mask) != 573 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) { 574 addr = phydev->mdio.addr; 575 step++; 576 } 577 } 578 579 /* The range we get should be a multiple of four. Please note that both 580 * the min_addr and max_addr are inclusive. So we have to add one if we 581 * subtract them. 582 */ 583 if ((max_addr - min_addr + 1) % 4) { 584 dev_err(&phydev->mdio.dev, 585 "Detected Quad PHY IDs %d..%d doesn't make sense.\n", 586 min_addr, max_addr); 587 return -EINVAL; 588 } 589 590 priv->port = (phydev->mdio.addr - min_addr) % 4; 591 priv->base_addr = phydev->mdio.addr - priv->port; 592 593 return 0; 594 } 595 596 static int bcm54140_probe(struct phy_device *phydev) 597 { 598 struct bcm54140_priv *priv; 599 int ret; 600 601 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 602 if (!priv) 603 return -ENOMEM; 604 605 phydev->priv = priv; 606 607 ret = bcm54140_get_base_addr_and_port(phydev); 608 if (ret) 609 return ret; 610 611 #if IS_ENABLED(CONFIG_HWMON) 612 mutex_init(&priv->alarm_lock); 613 614 if (!bcm54140_is_pkg_init(phydev)) { 615 ret = bcm54140_probe_once(phydev); 616 if (ret) 617 return ret; 618 } 619 620 priv->pkg_init = true; 621 #endif 622 623 phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n", 624 priv->port, priv->base_addr); 625 626 return 0; 627 } 628 629 static int bcm54140_config_init(struct phy_device *phydev) 630 { 631 u16 reg = 0xffff; 632 int ret; 633 634 /* Apply hardware errata */ 635 ret = bcm54140_b0_workaround(phydev); 636 if (ret) 637 return ret; 638 639 /* Unmask events we are interested in. */ 640 reg &= ~(BCM54140_RDB_INT_DUPLEX | 641 BCM54140_RDB_INT_SPEED | 642 BCM54140_RDB_INT_LINK); 643 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg); 644 if (ret) 645 return ret; 646 647 /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */ 648 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1, 649 0, BCM54140_RDB_SPARE1_LSLM); 650 if (ret) 651 return ret; 652 653 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL, 654 0, BCM54140_RDB_LED_CTRL_ACTLINK0); 655 if (ret) 656 return ret; 657 658 /* disable super isolate mode */ 659 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR, 660 BCM54140_RDB_C_PWR_ISOLATE, 0); 661 } 662 663 int bcm54140_did_interrupt(struct phy_device *phydev) 664 { 665 int ret; 666 667 ret = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 668 669 return (ret < 0) ? 0 : ret; 670 } 671 672 int bcm54140_ack_intr(struct phy_device *phydev) 673 { 674 int reg; 675 676 /* clear pending interrupts */ 677 reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 678 if (reg < 0) 679 return reg; 680 681 return 0; 682 } 683 684 int bcm54140_config_intr(struct phy_device *phydev) 685 { 686 struct bcm54140_priv *priv = phydev->priv; 687 static const u16 port_to_imr_bit[] = { 688 BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1, 689 BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3, 690 }; 691 int reg; 692 693 if (priv->port >= ARRAY_SIZE(port_to_imr_bit)) 694 return -EINVAL; 695 696 reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR); 697 if (reg < 0) 698 return reg; 699 700 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 701 reg &= ~port_to_imr_bit[priv->port]; 702 else 703 reg |= port_to_imr_bit[priv->port]; 704 705 return bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg); 706 } 707 708 static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data) 709 { 710 int val; 711 712 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL); 713 if (val < 0) 714 return val; 715 716 if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) { 717 *data = DOWNSHIFT_DEV_DISABLE; 718 return 0; 719 } 720 721 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2); 722 if (val < 0) 723 return val; 724 725 if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS) 726 *data = 1; 727 else 728 *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2; 729 730 return 0; 731 } 732 733 static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt) 734 { 735 u16 mask, set; 736 int ret; 737 738 if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT) 739 return -EINVAL; 740 741 if (!cnt) 742 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 743 BCM54140_RDB_C_MISC_CTRL_WS_EN, 0); 744 745 if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT) 746 cnt = BCM54140_DEFAULT_DOWNSHIFT; 747 748 if (cnt == 1) { 749 mask = 0; 750 set = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 751 } else { 752 mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 753 mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT; 754 set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2); 755 } 756 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2, 757 mask, set); 758 if (ret) 759 return ret; 760 761 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 762 0, BCM54140_RDB_C_MISC_CTRL_WS_EN); 763 } 764 765 static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval) 766 { 767 int val; 768 769 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR); 770 if (val < 0) 771 return val; 772 773 switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) { 774 case BCM54140_RDB_C_APWR_APD_MODE_DIS: 775 case BCM54140_RDB_C_APWR_APD_MODE_DIS2: 776 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE; 777 break; 778 case BCM54140_RDB_C_APWR_APD_MODE_EN: 779 case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG: 780 switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) { 781 case BCM54140_RDB_C_APWR_SLP_TIM_2_7: 782 *tx_interval = 2700; 783 break; 784 case BCM54140_RDB_C_APWR_SLP_TIM_5_4: 785 *tx_interval = 5400; 786 break; 787 } 788 } 789 790 return 0; 791 } 792 793 static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval) 794 { 795 u16 mask, set; 796 797 mask = BCM54140_RDB_C_APWR_APD_MODE_MASK; 798 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE) 799 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 800 BCM54140_RDB_C_APWR_APD_MODE_DIS); 801 else 802 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 803 BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG); 804 805 /* enable single pulse mode */ 806 set |= BCM54140_RDB_C_APWR_SINGLE_PULSE; 807 808 /* set sleep timer */ 809 mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK; 810 switch (tx_interval) { 811 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 812 case ETHTOOL_PHY_EDPD_DISABLE: 813 case 2700: 814 set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7; 815 break; 816 case 5400: 817 set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4; 818 break; 819 default: 820 return -EINVAL; 821 } 822 823 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set); 824 } 825 826 static int bcm54140_get_tunable(struct phy_device *phydev, 827 struct ethtool_tunable *tuna, void *data) 828 { 829 switch (tuna->id) { 830 case ETHTOOL_PHY_DOWNSHIFT: 831 return bcm54140_get_downshift(phydev, data); 832 case ETHTOOL_PHY_EDPD: 833 return bcm54140_get_edpd(phydev, data); 834 default: 835 return -EOPNOTSUPP; 836 } 837 } 838 839 static int bcm54140_set_tunable(struct phy_device *phydev, 840 struct ethtool_tunable *tuna, const void *data) 841 { 842 switch (tuna->id) { 843 case ETHTOOL_PHY_DOWNSHIFT: 844 return bcm54140_set_downshift(phydev, *(const u8 *)data); 845 case ETHTOOL_PHY_EDPD: 846 return bcm54140_set_edpd(phydev, *(const u16 *)data); 847 default: 848 return -EOPNOTSUPP; 849 } 850 } 851 852 static struct phy_driver bcm54140_drivers[] = { 853 { 854 .phy_id = PHY_ID_BCM54140, 855 .phy_id_mask = 0xfffffff0, 856 .name = "Broadcom BCM54140", 857 .features = PHY_GBIT_FEATURES, 858 .config_init = bcm54140_config_init, 859 .did_interrupt = bcm54140_did_interrupt, 860 .ack_interrupt = bcm54140_ack_intr, 861 .config_intr = bcm54140_config_intr, 862 .probe = bcm54140_probe, 863 .suspend = genphy_suspend, 864 .resume = genphy_resume, 865 .get_tunable = bcm54140_get_tunable, 866 .set_tunable = bcm54140_set_tunable, 867 }, 868 }; 869 module_phy_driver(bcm54140_drivers); 870 871 static struct mdio_device_id __maybe_unused bcm54140_tbl[] = { 872 { PHY_ID_BCM54140, 0xfffffff0 }, 873 { } 874 }; 875 876 MODULE_AUTHOR("Michael Walle"); 877 MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver"); 878 MODULE_DEVICE_TABLE(mdio, bcm54140_tbl); 879 MODULE_LICENSE("GPL"); 880