1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY 3 * 4 * Copyright (c) 2020 Michael Walle <michael@walle.cc> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/brcmphy.h> 9 #include <linux/hwmon.h> 10 #include <linux/module.h> 11 #include <linux/phy.h> 12 13 #include "bcm-phy-lib.h" 14 15 /* RDB per-port registers 16 */ 17 #define BCM54140_RDB_ISR 0x00a /* interrupt status */ 18 #define BCM54140_RDB_IMR 0x00b /* interrupt mask */ 19 #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */ 20 #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */ 21 #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */ 22 #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */ 23 #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */ 24 #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */ 25 #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */ 26 #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */ 27 #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */ 28 #define BCM54140_RDB_SPARE3_BIT0 BIT(0) 29 #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */ 30 #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4) 31 #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8) 32 #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */ 33 #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */ 34 #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */ 35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */ 36 #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */ 37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */ 38 #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5) 39 #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */ 40 #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */ 41 #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */ 42 #define BCM54140_RDB_C_PWR 0x02a /* copper power control */ 43 #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */ 44 #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */ 45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */ 46 47 /* RDB global registers 48 */ 49 #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */ 50 #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4) 51 #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5) 52 #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6) 53 #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7) 54 #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */ 55 #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */ 56 #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1) 57 #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */ 58 #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */ 59 #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */ 60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */ 61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */ 62 #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */ 63 #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */ 64 #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */ 65 #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0) 66 #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */ 67 #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */ 68 #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */ 69 #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0) 70 #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */ 71 #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */ 72 #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */ 73 #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0) 74 #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */ 75 #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */ 76 #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */ 77 #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */ 78 79 /* According to the datasheet the formula is: 80 * T = 413.35 - (0.49055 * bits[9:0]) 81 */ 82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491) 83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491) 84 85 /* According to the datasheet the formula is: 86 * U = bits[11:0] / 1024 * 220 / 0.2 87 * 88 * Normalized: 89 * U = bits[11:0] / 4096 * 2514 90 */ 91 #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11) 92 #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514) 93 94 /* According to the datasheet the formula is: 95 * U = bits[10:0] / 1024 * 880 / 0.7 96 * 97 * Normalized: 98 * U = bits[10:0] / 2048 * 4400 99 */ 100 #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12) 101 #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400) 102 103 #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \ 104 : BCM54140_HWMON_TO_IN_1V0(v)) 105 #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \ 106 : BCM54140_HWMON_FROM_IN_1V0(v)) 107 #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \ 108 : BCM54140_RDB_MON_1V0_DATA_MASK) 109 #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \ 110 : BCM54140_RDB_MON_1V0_VAL) 111 #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \ 112 : BCM54140_RDB_MON_1V0_MIN) 113 #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \ 114 : BCM54140_RDB_MON_1V0_MAX) 115 #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \ 116 : BCM54140_RDB_MON_ISR_1V0) 117 118 #define BCM54140_DEFAULT_DOWNSHIFT 5 119 #define BCM54140_MAX_DOWNSHIFT 9 120 121 struct bcm54140_priv { 122 int port; 123 int base_addr; 124 #if IS_ENABLED(CONFIG_HWMON) 125 bool pkg_init; 126 /* protect the alarm bits */ 127 struct mutex alarm_lock; 128 u16 alarm; 129 #endif 130 }; 131 132 #if IS_ENABLED(CONFIG_HWMON) 133 static umode_t bcm54140_hwmon_is_visible(const void *data, 134 enum hwmon_sensor_types type, 135 u32 attr, int channel) 136 { 137 switch (type) { 138 case hwmon_in: 139 switch (attr) { 140 case hwmon_in_min: 141 case hwmon_in_max: 142 return 0644; 143 case hwmon_in_label: 144 case hwmon_in_input: 145 case hwmon_in_alarm: 146 return 0444; 147 default: 148 return 0; 149 } 150 case hwmon_temp: 151 switch (attr) { 152 case hwmon_temp_min: 153 case hwmon_temp_max: 154 return 0644; 155 case hwmon_temp_input: 156 case hwmon_temp_alarm: 157 return 0444; 158 default: 159 return 0; 160 } 161 default: 162 return 0; 163 } 164 } 165 166 static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit, 167 long *val) 168 { 169 struct phy_device *phydev = dev_get_drvdata(dev); 170 struct bcm54140_priv *priv = phydev->priv; 171 int tmp, ret = 0; 172 173 mutex_lock(&priv->alarm_lock); 174 175 /* latch any alarm bits */ 176 tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR); 177 if (tmp < 0) { 178 ret = tmp; 179 goto out; 180 } 181 priv->alarm |= tmp; 182 183 *val = !!(priv->alarm & bit); 184 priv->alarm &= ~bit; 185 186 out: 187 mutex_unlock(&priv->alarm_lock); 188 return ret; 189 } 190 191 static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val) 192 { 193 struct phy_device *phydev = dev_get_drvdata(dev); 194 u16 reg, tmp; 195 196 switch (attr) { 197 case hwmon_temp_input: 198 reg = BCM54140_RDB_MON_TEMP_VAL; 199 break; 200 case hwmon_temp_min: 201 reg = BCM54140_RDB_MON_TEMP_MIN; 202 break; 203 case hwmon_temp_max: 204 reg = BCM54140_RDB_MON_TEMP_MAX; 205 break; 206 case hwmon_temp_alarm: 207 return bcm54140_hwmon_read_alarm(dev, 208 BCM54140_RDB_MON_ISR_TEMP, 209 val); 210 default: 211 return -EOPNOTSUPP; 212 } 213 214 tmp = bcm_phy_read_rdb(phydev, reg); 215 if (tmp < 0) 216 return tmp; 217 218 *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK); 219 220 return 0; 221 } 222 223 static int bcm54140_hwmon_read_in(struct device *dev, u32 attr, 224 int channel, long *val) 225 { 226 struct phy_device *phydev = dev_get_drvdata(dev); 227 u16 bit, reg, tmp; 228 229 switch (attr) { 230 case hwmon_in_input: 231 reg = BCM54140_HWMON_IN_VAL_REG(channel); 232 break; 233 case hwmon_in_min: 234 reg = BCM54140_HWMON_IN_MIN_REG(channel); 235 break; 236 case hwmon_in_max: 237 reg = BCM54140_HWMON_IN_MAX_REG(channel); 238 break; 239 case hwmon_in_alarm: 240 bit = BCM54140_HWMON_IN_ALARM_BIT(channel); 241 return bcm54140_hwmon_read_alarm(dev, bit, val); 242 default: 243 return -EOPNOTSUPP; 244 } 245 246 tmp = bcm_phy_read_rdb(phydev, reg); 247 if (tmp < 0) 248 return tmp; 249 250 tmp &= BCM54140_HWMON_IN_MASK(channel); 251 *val = BCM54140_HWMON_TO_IN(channel, tmp); 252 253 return 0; 254 } 255 256 static int bcm54140_hwmon_read(struct device *dev, 257 enum hwmon_sensor_types type, u32 attr, 258 int channel, long *val) 259 { 260 switch (type) { 261 case hwmon_temp: 262 return bcm54140_hwmon_read_temp(dev, attr, val); 263 case hwmon_in: 264 return bcm54140_hwmon_read_in(dev, attr, channel, val); 265 default: 266 return -EOPNOTSUPP; 267 } 268 } 269 270 static const char *const bcm54140_hwmon_in_labels[] = { 271 "AVDDL", 272 "AVDDH", 273 }; 274 275 static int bcm54140_hwmon_read_string(struct device *dev, 276 enum hwmon_sensor_types type, u32 attr, 277 int channel, const char **str) 278 { 279 switch (type) { 280 case hwmon_in: 281 switch (attr) { 282 case hwmon_in_label: 283 *str = bcm54140_hwmon_in_labels[channel]; 284 return 0; 285 default: 286 return -EOPNOTSUPP; 287 } 288 default: 289 return -EOPNOTSUPP; 290 } 291 } 292 293 static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr, 294 int channel, long val) 295 { 296 struct phy_device *phydev = dev_get_drvdata(dev); 297 u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK; 298 u16 reg; 299 300 val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask), 301 BCM54140_HWMON_TO_TEMP(0)); 302 303 switch (attr) { 304 case hwmon_temp_min: 305 reg = BCM54140_RDB_MON_TEMP_MIN; 306 break; 307 case hwmon_temp_max: 308 reg = BCM54140_RDB_MON_TEMP_MAX; 309 break; 310 default: 311 return -EOPNOTSUPP; 312 } 313 314 return bcm_phy_modify_rdb(phydev, reg, mask, 315 BCM54140_HWMON_FROM_TEMP(val)); 316 } 317 318 static int bcm54140_hwmon_write_in(struct device *dev, u32 attr, 319 int channel, long val) 320 { 321 struct phy_device *phydev = dev_get_drvdata(dev); 322 u16 mask = BCM54140_HWMON_IN_MASK(channel); 323 u16 reg; 324 325 val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask)); 326 327 switch (attr) { 328 case hwmon_in_min: 329 reg = BCM54140_HWMON_IN_MIN_REG(channel); 330 break; 331 case hwmon_in_max: 332 reg = BCM54140_HWMON_IN_MAX_REG(channel); 333 break; 334 default: 335 return -EOPNOTSUPP; 336 } 337 338 return bcm_phy_modify_rdb(phydev, reg, mask, 339 BCM54140_HWMON_FROM_IN(channel, val)); 340 } 341 342 static int bcm54140_hwmon_write(struct device *dev, 343 enum hwmon_sensor_types type, u32 attr, 344 int channel, long val) 345 { 346 switch (type) { 347 case hwmon_temp: 348 return bcm54140_hwmon_write_temp(dev, attr, channel, val); 349 case hwmon_in: 350 return bcm54140_hwmon_write_in(dev, attr, channel, val); 351 default: 352 return -EOPNOTSUPP; 353 } 354 } 355 356 static const struct hwmon_channel_info *bcm54140_hwmon_info[] = { 357 HWMON_CHANNEL_INFO(temp, 358 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | 359 HWMON_T_ALARM), 360 HWMON_CHANNEL_INFO(in, 361 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 362 HWMON_I_ALARM | HWMON_I_LABEL, 363 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 364 HWMON_I_ALARM | HWMON_I_LABEL), 365 NULL 366 }; 367 368 static const struct hwmon_ops bcm54140_hwmon_ops = { 369 .is_visible = bcm54140_hwmon_is_visible, 370 .read = bcm54140_hwmon_read, 371 .read_string = bcm54140_hwmon_read_string, 372 .write = bcm54140_hwmon_write, 373 }; 374 375 static const struct hwmon_chip_info bcm54140_chip_info = { 376 .ops = &bcm54140_hwmon_ops, 377 .info = bcm54140_hwmon_info, 378 }; 379 380 static int bcm54140_enable_monitoring(struct phy_device *phydev) 381 { 382 u16 mask, set; 383 384 /* 3.3V voltage mode */ 385 set = BCM54140_RDB_MON_CTRL_V_MODE; 386 387 /* select round-robin */ 388 mask = BCM54140_RDB_MON_CTRL_SEL_MASK; 389 set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK, 390 BCM54140_RDB_MON_CTRL_SEL_RR); 391 392 /* remove power-down bit */ 393 mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN; 394 395 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set); 396 } 397 398 /* Check if one PHY has already done the init of the parts common to all PHYs 399 * in the Quad PHY package. 400 */ 401 static bool bcm54140_is_pkg_init(struct phy_device *phydev) 402 { 403 struct bcm54140_priv *priv = phydev->priv; 404 struct mii_bus *bus = phydev->mdio.bus; 405 int base_addr = priv->base_addr; 406 struct phy_device *phy; 407 int i; 408 409 /* Quad PHY */ 410 for (i = 0; i < 4; i++) { 411 phy = mdiobus_get_phy(bus, base_addr + i); 412 if (!phy) 413 continue; 414 415 if ((phy->phy_id & phydev->drv->phy_id_mask) != 416 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) 417 continue; 418 419 priv = phy->priv; 420 421 if (priv && priv->pkg_init) 422 return true; 423 } 424 425 return false; 426 } 427 428 static int bcm54140_probe_once(struct phy_device *phydev) 429 { 430 struct device *hwmon; 431 int ret; 432 433 /* enable hardware monitoring */ 434 ret = bcm54140_enable_monitoring(phydev); 435 if (ret) 436 return ret; 437 438 hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev, 439 "BCM54140", phydev, 440 &bcm54140_chip_info, 441 NULL); 442 return PTR_ERR_OR_ZERO(hwmon); 443 } 444 #endif 445 446 static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb) 447 { 448 struct bcm54140_priv *priv = phydev->priv; 449 struct mii_bus *bus = phydev->mdio.bus; 450 int ret; 451 452 mutex_lock(&bus->mdio_lock); 453 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 454 if (ret < 0) 455 goto out; 456 457 ret = __mdiobus_read(bus, priv->base_addr, MII_BCM54XX_RDB_DATA); 458 459 out: 460 mutex_unlock(&bus->mdio_lock); 461 return ret; 462 } 463 464 static int bcm54140_base_write_rdb(struct phy_device *phydev, 465 u16 rdb, u16 val) 466 { 467 struct bcm54140_priv *priv = phydev->priv; 468 struct mii_bus *bus = phydev->mdio.bus; 469 int ret; 470 471 mutex_lock(&bus->mdio_lock); 472 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 473 if (ret < 0) 474 goto out; 475 476 ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_DATA, val); 477 478 out: 479 mutex_unlock(&bus->mdio_lock); 480 return ret; 481 } 482 483 /* Under some circumstances a core PLL may not lock, this will then prevent 484 * a successful link establishment. Restart the PLL after the voltages are 485 * stable to workaround this issue. 486 */ 487 static int bcm54140_b0_workaround(struct phy_device *phydev) 488 { 489 int spare3; 490 int ret; 491 492 spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3); 493 if (spare3 < 0) 494 return spare3; 495 496 spare3 &= ~BCM54140_RDB_SPARE3_BIT0; 497 498 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 499 if (ret) 500 return ret; 501 502 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 503 if (ret) 504 return ret; 505 506 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 507 if (ret) 508 return ret; 509 510 spare3 |= BCM54140_RDB_SPARE3_BIT0; 511 512 return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 513 } 514 515 /* The BCM54140 is a quad PHY where only the first port has access to the 516 * global register. Thus we need to find out its PHY address. 517 * 518 */ 519 static int bcm54140_get_base_addr_and_port(struct phy_device *phydev) 520 { 521 struct bcm54140_priv *priv = phydev->priv; 522 struct mii_bus *bus = phydev->mdio.bus; 523 int addr, min_addr, max_addr; 524 int step = 1; 525 u32 phy_id; 526 int tmp; 527 528 min_addr = phydev->mdio.addr; 529 max_addr = phydev->mdio.addr; 530 addr = phydev->mdio.addr; 531 532 /* We scan forward and backwards and look for PHYs which have the 533 * same phy_id like we do. Step 1 will scan forward, step 2 534 * backwards. Once we are finished, we have a min_addr and 535 * max_addr which resembles the range of PHY addresses of the same 536 * type of PHY. There is one caveat; there may be many PHYs of 537 * the same type, but we know that each PHY takes exactly 4 538 * consecutive addresses. Therefore we can deduce our offset 539 * to the base address of this quad PHY. 540 */ 541 542 while (1) { 543 if (step == 3) { 544 break; 545 } else if (step == 1) { 546 max_addr = addr; 547 addr++; 548 } else { 549 min_addr = addr; 550 addr--; 551 } 552 553 if (addr < 0 || addr >= PHY_MAX_ADDR) { 554 addr = phydev->mdio.addr; 555 step++; 556 continue; 557 } 558 559 /* read the PHY id */ 560 tmp = mdiobus_read(bus, addr, MII_PHYSID1); 561 if (tmp < 0) 562 return tmp; 563 phy_id = tmp << 16; 564 tmp = mdiobus_read(bus, addr, MII_PHYSID2); 565 if (tmp < 0) 566 return tmp; 567 phy_id |= tmp; 568 569 /* see if it is still the same PHY */ 570 if ((phy_id & phydev->drv->phy_id_mask) != 571 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) { 572 addr = phydev->mdio.addr; 573 step++; 574 } 575 } 576 577 /* The range we get should be a multiple of four. Please note that both 578 * the min_addr and max_addr are inclusive. So we have to add one if we 579 * subtract them. 580 */ 581 if ((max_addr - min_addr + 1) % 4) { 582 dev_err(&phydev->mdio.dev, 583 "Detected Quad PHY IDs %d..%d doesn't make sense.\n", 584 min_addr, max_addr); 585 return -EINVAL; 586 } 587 588 priv->port = (phydev->mdio.addr - min_addr) % 4; 589 priv->base_addr = phydev->mdio.addr - priv->port; 590 591 return 0; 592 } 593 594 static int bcm54140_probe(struct phy_device *phydev) 595 { 596 struct bcm54140_priv *priv; 597 int ret; 598 599 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 600 if (!priv) 601 return -ENOMEM; 602 603 phydev->priv = priv; 604 605 ret = bcm54140_get_base_addr_and_port(phydev); 606 if (ret) 607 return ret; 608 609 #if IS_ENABLED(CONFIG_HWMON) 610 mutex_init(&priv->alarm_lock); 611 612 if (!bcm54140_is_pkg_init(phydev)) { 613 ret = bcm54140_probe_once(phydev); 614 if (ret) 615 return ret; 616 } 617 618 priv->pkg_init = true; 619 #endif 620 621 phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n", 622 priv->port, priv->base_addr); 623 624 return 0; 625 } 626 627 static int bcm54140_config_init(struct phy_device *phydev) 628 { 629 u16 reg = 0xffff; 630 int ret; 631 632 /* Apply hardware errata */ 633 ret = bcm54140_b0_workaround(phydev); 634 if (ret) 635 return ret; 636 637 /* Unmask events we are interested in. */ 638 reg &= ~(BCM54140_RDB_INT_DUPLEX | 639 BCM54140_RDB_INT_SPEED | 640 BCM54140_RDB_INT_LINK); 641 ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg); 642 if (ret) 643 return ret; 644 645 /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */ 646 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1, 647 0, BCM54140_RDB_SPARE1_LSLM); 648 if (ret) 649 return ret; 650 651 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL, 652 0, BCM54140_RDB_LED_CTRL_ACTLINK0); 653 if (ret) 654 return ret; 655 656 /* disable super isolate mode */ 657 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR, 658 BCM54140_RDB_C_PWR_ISOLATE, 0); 659 } 660 661 int bcm54140_did_interrupt(struct phy_device *phydev) 662 { 663 int ret; 664 665 ret = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 666 667 return (ret < 0) ? 0 : ret; 668 } 669 670 int bcm54140_ack_intr(struct phy_device *phydev) 671 { 672 int reg; 673 674 /* clear pending interrupts */ 675 reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 676 if (reg < 0) 677 return reg; 678 679 return 0; 680 } 681 682 int bcm54140_config_intr(struct phy_device *phydev) 683 { 684 struct bcm54140_priv *priv = phydev->priv; 685 static const u16 port_to_imr_bit[] = { 686 BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1, 687 BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3, 688 }; 689 int reg; 690 691 if (priv->port >= ARRAY_SIZE(port_to_imr_bit)) 692 return -EINVAL; 693 694 reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR); 695 if (reg < 0) 696 return reg; 697 698 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 699 reg &= ~port_to_imr_bit[priv->port]; 700 else 701 reg |= port_to_imr_bit[priv->port]; 702 703 return bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg); 704 } 705 706 static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data) 707 { 708 int val; 709 710 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL); 711 if (val < 0) 712 return val; 713 714 if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) { 715 *data = DOWNSHIFT_DEV_DISABLE; 716 return 0; 717 } 718 719 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2); 720 if (val < 0) 721 return val; 722 723 if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS) 724 *data = 1; 725 else 726 *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2; 727 728 return 0; 729 } 730 731 static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt) 732 { 733 u16 mask, set; 734 int ret; 735 736 if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT) 737 return -EINVAL; 738 739 if (!cnt) 740 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 741 BCM54140_RDB_C_MISC_CTRL_WS_EN, 0); 742 743 if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT) 744 cnt = BCM54140_DEFAULT_DOWNSHIFT; 745 746 if (cnt == 1) { 747 mask = 0; 748 set = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 749 } else { 750 mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 751 mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT; 752 set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2); 753 } 754 ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2, 755 mask, set); 756 if (ret) 757 return ret; 758 759 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 760 0, BCM54140_RDB_C_MISC_CTRL_WS_EN); 761 } 762 763 static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval) 764 { 765 int val; 766 767 val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR); 768 if (val < 0) 769 return val; 770 771 switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) { 772 case BCM54140_RDB_C_APWR_APD_MODE_DIS: 773 case BCM54140_RDB_C_APWR_APD_MODE_DIS2: 774 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE; 775 break; 776 case BCM54140_RDB_C_APWR_APD_MODE_EN: 777 case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG: 778 switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) { 779 case BCM54140_RDB_C_APWR_SLP_TIM_2_7: 780 *tx_interval = 2700; 781 break; 782 case BCM54140_RDB_C_APWR_SLP_TIM_5_4: 783 *tx_interval = 5400; 784 break; 785 } 786 } 787 788 return 0; 789 } 790 791 static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval) 792 { 793 u16 mask, set; 794 795 mask = BCM54140_RDB_C_APWR_APD_MODE_MASK; 796 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE) 797 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 798 BCM54140_RDB_C_APWR_APD_MODE_DIS); 799 else 800 set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 801 BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG); 802 803 /* enable single pulse mode */ 804 set |= BCM54140_RDB_C_APWR_SINGLE_PULSE; 805 806 /* set sleep timer */ 807 mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK; 808 switch (tx_interval) { 809 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 810 case ETHTOOL_PHY_EDPD_DISABLE: 811 case 2700: 812 set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7; 813 break; 814 case 5400: 815 set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4; 816 break; 817 default: 818 return -EINVAL; 819 } 820 821 return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set); 822 } 823 824 static int bcm54140_get_tunable(struct phy_device *phydev, 825 struct ethtool_tunable *tuna, void *data) 826 { 827 switch (tuna->id) { 828 case ETHTOOL_PHY_DOWNSHIFT: 829 return bcm54140_get_downshift(phydev, data); 830 case ETHTOOL_PHY_EDPD: 831 return bcm54140_get_edpd(phydev, data); 832 default: 833 return -EOPNOTSUPP; 834 } 835 } 836 837 static int bcm54140_set_tunable(struct phy_device *phydev, 838 struct ethtool_tunable *tuna, const void *data) 839 { 840 switch (tuna->id) { 841 case ETHTOOL_PHY_DOWNSHIFT: 842 return bcm54140_set_downshift(phydev, *(const u8 *)data); 843 case ETHTOOL_PHY_EDPD: 844 return bcm54140_set_edpd(phydev, *(const u16 *)data); 845 default: 846 return -EOPNOTSUPP; 847 } 848 } 849 850 static struct phy_driver bcm54140_drivers[] = { 851 { 852 .phy_id = PHY_ID_BCM54140, 853 .phy_id_mask = 0xfffffff0, 854 .name = "Broadcom BCM54140", 855 .features = PHY_GBIT_FEATURES, 856 .config_init = bcm54140_config_init, 857 .did_interrupt = bcm54140_did_interrupt, 858 .ack_interrupt = bcm54140_ack_intr, 859 .config_intr = bcm54140_config_intr, 860 .probe = bcm54140_probe, 861 .suspend = genphy_suspend, 862 .resume = genphy_resume, 863 .get_tunable = bcm54140_get_tunable, 864 .set_tunable = bcm54140_set_tunable, 865 }, 866 }; 867 module_phy_driver(bcm54140_drivers); 868 869 static struct mdio_device_id __maybe_unused bcm54140_tbl[] = { 870 { PHY_ID_BCM54140, 0xfffffff0 }, 871 { } 872 }; 873 874 MODULE_AUTHOR("Michael Walle"); 875 MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver"); 876 MODULE_DEVICE_TABLE(mdio, bcm54140_tbl); 877 MODULE_LICENSE("GPL"); 878