1 /* 2 * Copyright (C) 2015 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include "bcm-phy-lib.h" 15 #include <linux/brcmphy.h> 16 #include <linux/export.h> 17 #include <linux/mdio.h> 18 #include <linux/module.h> 19 #include <linux/phy.h> 20 21 #define MII_BCM_CHANNEL_WIDTH 0x2000 22 #define BCM_CL45VEN_EEE_ADV 0x3c 23 24 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) 25 { 26 int rc; 27 28 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); 29 if (rc < 0) 30 return rc; 31 32 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); 33 } 34 EXPORT_SYMBOL_GPL(bcm_phy_write_exp); 35 36 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg) 37 { 38 int val; 39 40 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); 41 if (val < 0) 42 return val; 43 44 val = phy_read(phydev, MII_BCM54XX_EXP_DATA); 45 46 /* Restore default value. It's O.K. if this write fails. */ 47 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0); 48 49 return val; 50 } 51 EXPORT_SYMBOL_GPL(bcm_phy_read_exp); 52 53 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum) 54 { 55 /* The register must be written to both the Shadow Register Select and 56 * the Shadow Read Register Selector 57 */ 58 phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | 59 regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT); 60 return phy_read(phydev, MII_BCM54XX_AUX_CTL); 61 } 62 EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read); 63 64 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) 65 { 66 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); 67 } 68 EXPORT_SYMBOL(bcm54xx_auxctl_write); 69 70 int bcm_phy_write_misc(struct phy_device *phydev, 71 u16 reg, u16 chl, u16 val) 72 { 73 int rc; 74 int tmp; 75 76 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 77 MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 78 if (rc < 0) 79 return rc; 80 81 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL); 82 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA; 83 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); 84 if (rc < 0) 85 return rc; 86 87 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg; 88 rc = bcm_phy_write_exp(phydev, tmp, val); 89 90 return rc; 91 } 92 EXPORT_SYMBOL_GPL(bcm_phy_write_misc); 93 94 int bcm_phy_read_misc(struct phy_device *phydev, 95 u16 reg, u16 chl) 96 { 97 int rc; 98 int tmp; 99 100 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 101 MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 102 if (rc < 0) 103 return rc; 104 105 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL); 106 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA; 107 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); 108 if (rc < 0) 109 return rc; 110 111 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg; 112 rc = bcm_phy_read_exp(phydev, tmp); 113 114 return rc; 115 } 116 EXPORT_SYMBOL_GPL(bcm_phy_read_misc); 117 118 int bcm_phy_ack_intr(struct phy_device *phydev) 119 { 120 int reg; 121 122 /* Clear pending interrupts. */ 123 reg = phy_read(phydev, MII_BCM54XX_ISR); 124 if (reg < 0) 125 return reg; 126 127 return 0; 128 } 129 EXPORT_SYMBOL_GPL(bcm_phy_ack_intr); 130 131 int bcm_phy_config_intr(struct phy_device *phydev) 132 { 133 int reg; 134 135 reg = phy_read(phydev, MII_BCM54XX_ECR); 136 if (reg < 0) 137 return reg; 138 139 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 140 reg &= ~MII_BCM54XX_ECR_IM; 141 else 142 reg |= MII_BCM54XX_ECR_IM; 143 144 return phy_write(phydev, MII_BCM54XX_ECR, reg); 145 } 146 EXPORT_SYMBOL_GPL(bcm_phy_config_intr); 147 148 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow) 149 { 150 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); 151 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD)); 152 } 153 EXPORT_SYMBOL_GPL(bcm_phy_read_shadow); 154 155 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow, 156 u16 val) 157 { 158 return phy_write(phydev, MII_BCM54XX_SHD, 159 MII_BCM54XX_SHD_WRITE | 160 MII_BCM54XX_SHD_VAL(shadow) | 161 MII_BCM54XX_SHD_DATA(val)); 162 } 163 EXPORT_SYMBOL_GPL(bcm_phy_write_shadow); 164 165 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down) 166 { 167 int val; 168 169 if (dll_pwr_down) { 170 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); 171 if (val < 0) 172 return val; 173 174 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; 175 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); 176 } 177 178 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); 179 if (val < 0) 180 return val; 181 182 /* Clear APD bits */ 183 val &= BCM_APD_CLR_MASK; 184 185 if (phydev->autoneg == AUTONEG_ENABLE) 186 val |= BCM54XX_SHD_APD_EN; 187 else 188 val |= BCM_NO_ANEG_APD_EN; 189 190 /* Enable energy detect single link pulse for easy wakeup */ 191 val |= BCM_APD_SINGLELP_EN; 192 193 /* Enable Auto Power-Down (APD) for the PHY */ 194 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); 195 } 196 EXPORT_SYMBOL_GPL(bcm_phy_enable_apd); 197 198 int bcm_phy_set_eee(struct phy_device *phydev, bool enable) 199 { 200 int val; 201 202 /* Enable EEE at PHY level */ 203 val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL, 204 MDIO_MMD_AN); 205 if (val < 0) 206 return val; 207 208 if (enable) 209 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X; 210 else 211 val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X); 212 213 phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL, 214 MDIO_MMD_AN, (u32)val); 215 216 /* Advertise EEE */ 217 val = phy_read_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV, 218 MDIO_MMD_AN); 219 if (val < 0) 220 return val; 221 222 if (enable) 223 val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T); 224 else 225 val &= ~(MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T); 226 227 phy_write_mmd_indirect(phydev, BCM_CL45VEN_EEE_ADV, 228 MDIO_MMD_AN, (u32)val); 229 230 return 0; 231 } 232 EXPORT_SYMBOL_GPL(bcm_phy_set_eee); 233 234 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count) 235 { 236 int val; 237 238 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 239 if (val < 0) 240 return val; 241 242 /* Check if wirespeed is enabled or not */ 243 if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) { 244 *count = DOWNSHIFT_DEV_DISABLE; 245 return 0; 246 } 247 248 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2); 249 if (val < 0) 250 return val; 251 252 /* Downgrade after one link attempt */ 253 if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) { 254 *count = 1; 255 } else { 256 /* Downgrade after configured retry count */ 257 val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT; 258 val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK; 259 *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET; 260 } 261 262 return 0; 263 } 264 EXPORT_SYMBOL_GPL(bcm_phy_downshift_get); 265 266 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count) 267 { 268 int val = 0, ret = 0; 269 270 /* Range check the number given */ 271 if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET > 272 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK && 273 count != DOWNSHIFT_DEV_DEFAULT_COUNT) { 274 return -ERANGE; 275 } 276 277 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 278 if (val < 0) 279 return val; 280 281 /* Se the write enable bit */ 282 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 283 284 if (count == DOWNSHIFT_DEV_DISABLE) { 285 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN; 286 return bcm54xx_auxctl_write(phydev, 287 MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 288 val); 289 } else { 290 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN; 291 ret = bcm54xx_auxctl_write(phydev, 292 MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 293 val); 294 if (ret < 0) 295 return ret; 296 } 297 298 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2); 299 val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK << 300 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT | 301 BCM54XX_SHD_SCR2_WSPD_RTRY_DIS); 302 303 switch (count) { 304 case 1: 305 val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS; 306 break; 307 case DOWNSHIFT_DEV_DEFAULT_COUNT: 308 val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT; 309 break; 310 default: 311 val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) << 312 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT; 313 break; 314 } 315 316 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val); 317 } 318 EXPORT_SYMBOL_GPL(bcm_phy_downshift_set); 319 320 MODULE_DESCRIPTION("Broadcom PHY Library"); 321 MODULE_LICENSE("GPL v2"); 322 MODULE_AUTHOR("Broadcom Corporation"); 323