1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 17 #include "aquantia.h" 18 19 #define PHY_ID_AQ1202 0x03a1b445 20 #define PHY_ID_AQ2104 0x03a1b460 21 #define PHY_ID_AQR105 0x03a1b4a2 22 #define PHY_ID_AQR106 0x03a1b4d0 23 #define PHY_ID_AQR107 0x03a1b4e0 24 #define PHY_ID_AQCS109 0x03a1b5c2 25 #define PHY_ID_AQR405 0x03a1b4b0 26 #define PHY_ID_AQR111 0x03a1b610 27 #define PHY_ID_AQR111B0 0x03a1b612 28 #define PHY_ID_AQR112 0x03a1b662 29 #define PHY_ID_AQR412 0x03a1b712 30 #define PHY_ID_AQR113 0x31c31c40 31 #define PHY_ID_AQR113C 0x31c31c12 32 #define PHY_ID_AQR114C 0x31c31c22 33 #define PHY_ID_AQR115C 0x31c31c33 34 #define PHY_ID_AQR813 0x31c31cb2 35 36 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9 46 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 47 48 #define MDIO_AN_VEND_PROV 0xc400 49 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 50 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 51 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 52 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 53 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 54 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 55 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 56 57 #define MDIO_AN_RESVD_VEND_PROV 0xc410 58 #define MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO 0 59 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDI 1 60 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX 2 61 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK GENMASK(1, 0) 62 63 #define MDIO_AN_TX_VEND_STATUS1 0xc800 64 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 65 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 66 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 67 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 68 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 69 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 70 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 71 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 72 73 #define MDIO_AN_RESVD_VEND_STATUS1 0xc810 74 #define MDIO_AN_RESVD_VEND_STATUS1_MDIX BIT(8) 75 76 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 77 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 78 79 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 80 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 81 82 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 83 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 84 85 #define PMAPMD_RSVD_VEND_PROV 0xe400 86 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) 87 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) 88 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) 89 90 #define MDIO_AN_RX_LP_STAT1 0xe820 91 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 92 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 93 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 94 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 95 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 96 97 #define MDIO_AN_RX_LP_STAT4 0xe823 98 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 99 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 100 101 #define MDIO_AN_RX_VEND_STAT3 0xe832 102 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 103 104 /* Sleep and timeout for checking if the Processor-Intensive 105 * MDIO operation is finished 106 */ 107 #define AQR107_OP_IN_PROG_SLEEP 1000 108 #define AQR107_OP_IN_PROG_TIMEOUT 100000 109 110 static int aqr107_get_sset_count(struct phy_device *phydev) 111 { 112 return AQR107_SGMII_STAT_SZ; 113 } 114 115 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 116 { 117 int i; 118 119 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 120 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 121 ETH_GSTRING_LEN); 122 } 123 124 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 125 { 126 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 127 int len_l = min(stat->size, 16); 128 int len_h = stat->size - len_l; 129 u64 ret; 130 int val; 131 132 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 133 if (val < 0) 134 return U64_MAX; 135 136 ret = val & GENMASK(len_l - 1, 0); 137 if (len_h) { 138 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 139 if (val < 0) 140 return U64_MAX; 141 142 ret += (val & GENMASK(len_h - 1, 0)) << 16; 143 } 144 145 return ret; 146 } 147 148 static void aqr107_get_stats(struct phy_device *phydev, 149 struct ethtool_stats *stats, u64 *data) 150 { 151 struct aqr107_priv *priv = phydev->priv; 152 u64 val; 153 int i; 154 155 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 156 val = aqr107_get_stat(phydev, i); 157 if (val == U64_MAX) 158 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 159 aqr107_hw_stats[i].name); 160 else 161 priv->sgmii_stats[i] += val; 162 163 data[i] = priv->sgmii_stats[i]; 164 } 165 } 166 167 static int aqr_set_mdix(struct phy_device *phydev, int mdix) 168 { 169 u16 val = 0; 170 171 switch (mdix) { 172 case ETH_TP_MDI: 173 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDI; 174 break; 175 case ETH_TP_MDI_X: 176 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX; 177 break; 178 case ETH_TP_MDI_AUTO: 179 case ETH_TP_MDI_INVALID: 180 default: 181 val = MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO; 182 break; 183 } 184 185 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_PROV, 186 MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val); 187 } 188 189 static int aqr_config_aneg(struct phy_device *phydev) 190 { 191 bool changed = false; 192 u16 reg; 193 int ret; 194 195 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 196 if (ret < 0) 197 return ret; 198 if (ret > 0) 199 changed = true; 200 201 if (phydev->autoneg == AUTONEG_DISABLE) 202 return genphy_c45_pma_setup_forced(phydev); 203 204 ret = genphy_c45_an_config_aneg(phydev); 205 if (ret < 0) 206 return ret; 207 if (ret > 0) 208 changed = true; 209 210 /* Clause 45 has no standardized support for 1000BaseT, therefore 211 * use vendor registers for this mode. 212 */ 213 reg = 0; 214 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 215 phydev->advertising)) 216 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 217 218 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 219 phydev->advertising)) 220 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 221 222 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 223 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 224 phydev->advertising)) 225 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 226 227 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 228 phydev->advertising)) 229 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 230 231 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 232 MDIO_AN_VEND_PROV_1000BASET_HALF | 233 MDIO_AN_VEND_PROV_1000BASET_FULL | 234 MDIO_AN_VEND_PROV_2500BASET_FULL | 235 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 236 if (ret < 0) 237 return ret; 238 if (ret > 0) 239 changed = true; 240 241 return genphy_c45_check_and_restart_aneg(phydev, changed); 242 } 243 244 static int aqr_config_intr(struct phy_device *phydev) 245 { 246 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 247 int err; 248 249 if (en) { 250 /* Clear any pending interrupts before enabling them */ 251 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 252 if (err < 0) 253 return err; 254 } 255 256 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 257 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 258 if (err < 0) 259 return err; 260 261 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 262 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 263 if (err < 0) 264 return err; 265 266 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 267 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 268 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 269 if (err < 0) 270 return err; 271 272 if (!en) { 273 /* Clear any pending interrupts after we have disabled them */ 274 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 275 if (err < 0) 276 return err; 277 } 278 279 return 0; 280 } 281 282 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 283 { 284 int irq_status; 285 286 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 287 MDIO_AN_TX_VEND_INT_STATUS2); 288 if (irq_status < 0) { 289 phy_error(phydev); 290 return IRQ_NONE; 291 } 292 293 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 294 return IRQ_NONE; 295 296 phy_trigger_machine(phydev); 297 298 return IRQ_HANDLED; 299 } 300 301 static int aqr_read_status(struct phy_device *phydev) 302 { 303 int val; 304 305 if (phydev->autoneg == AUTONEG_ENABLE) { 306 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 307 if (val < 0) 308 return val; 309 310 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 311 phydev->lp_advertising, 312 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 313 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 314 phydev->lp_advertising, 315 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 316 } 317 318 val = genphy_c45_aneg_done(phydev); 319 if (val < 0) 320 return val; 321 if (val) { 322 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_STATUS1); 323 if (val < 0) 324 return val; 325 if (val & MDIO_AN_RESVD_VEND_STATUS1_MDIX) 326 phydev->mdix = ETH_TP_MDI_X; 327 else 328 phydev->mdix = ETH_TP_MDI; 329 } else { 330 phydev->mdix = ETH_TP_MDI_INVALID; 331 } 332 333 return genphy_c45_read_status(phydev); 334 } 335 336 static int aqr107_read_rate(struct phy_device *phydev) 337 { 338 u32 config_reg; 339 int val; 340 341 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 342 if (val < 0) 343 return val; 344 345 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 346 phydev->duplex = DUPLEX_FULL; 347 else 348 phydev->duplex = DUPLEX_HALF; 349 350 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 351 case MDIO_AN_TX_VEND_STATUS1_10BASET: 352 phydev->speed = SPEED_10; 353 config_reg = VEND1_GLOBAL_CFG_10M; 354 break; 355 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 356 phydev->speed = SPEED_100; 357 config_reg = VEND1_GLOBAL_CFG_100M; 358 break; 359 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 360 phydev->speed = SPEED_1000; 361 config_reg = VEND1_GLOBAL_CFG_1G; 362 break; 363 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 364 phydev->speed = SPEED_2500; 365 config_reg = VEND1_GLOBAL_CFG_2_5G; 366 break; 367 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 368 phydev->speed = SPEED_5000; 369 config_reg = VEND1_GLOBAL_CFG_5G; 370 break; 371 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 372 phydev->speed = SPEED_10000; 373 config_reg = VEND1_GLOBAL_CFG_10G; 374 break; 375 default: 376 phydev->speed = SPEED_UNKNOWN; 377 return 0; 378 } 379 380 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 381 if (val < 0) 382 return val; 383 384 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 385 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 386 phydev->rate_matching = RATE_MATCH_PAUSE; 387 else 388 phydev->rate_matching = RATE_MATCH_NONE; 389 390 return 0; 391 } 392 393 static int aqr107_read_status(struct phy_device *phydev) 394 { 395 int val, ret; 396 397 ret = aqr_read_status(phydev); 398 if (ret) 399 return ret; 400 401 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 402 return 0; 403 404 /** 405 * The status register is not immediately correct on line side link up. 406 * Poll periodically until it reflects the correct ON state. 407 * Only return fail for read error, timeout defaults to OFF state. 408 */ 409 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 410 MDIO_PHYXS_VEND_IF_STATUS, val, 411 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 412 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 413 AQR107_OP_IN_PROG_SLEEP, 414 AQR107_OP_IN_PROG_TIMEOUT, false); 415 if (ret && ret != -ETIMEDOUT) 416 return ret; 417 418 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 419 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 420 phydev->interface = PHY_INTERFACE_MODE_10GKR; 421 break; 422 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 423 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 424 break; 425 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 426 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 427 break; 428 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 429 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 430 break; 431 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 432 phydev->interface = PHY_INTERFACE_MODE_XAUI; 433 break; 434 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 435 phydev->interface = PHY_INTERFACE_MODE_SGMII; 436 break; 437 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 438 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 439 break; 440 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 441 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 442 break; 443 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 444 default: 445 phydev->link = false; 446 phydev->interface = PHY_INTERFACE_MODE_NA; 447 break; 448 } 449 450 /* Read possibly downshifted rate from vendor register */ 451 return aqr107_read_rate(phydev); 452 } 453 454 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 455 { 456 int val, cnt, enable; 457 458 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 459 if (val < 0) 460 return val; 461 462 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 463 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 464 465 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 466 467 return 0; 468 } 469 470 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 471 { 472 int val = 0; 473 474 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 475 return -E2BIG; 476 477 if (cnt != DOWNSHIFT_DEV_DISABLE) { 478 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 479 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 480 } 481 482 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 483 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 484 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 485 } 486 487 static int aqr107_get_tunable(struct phy_device *phydev, 488 struct ethtool_tunable *tuna, void *data) 489 { 490 switch (tuna->id) { 491 case ETHTOOL_PHY_DOWNSHIFT: 492 return aqr107_get_downshift(phydev, data); 493 default: 494 return -EOPNOTSUPP; 495 } 496 } 497 498 static int aqr107_set_tunable(struct phy_device *phydev, 499 struct ethtool_tunable *tuna, const void *data) 500 { 501 switch (tuna->id) { 502 case ETHTOOL_PHY_DOWNSHIFT: 503 return aqr107_set_downshift(phydev, *(const u8 *)data); 504 default: 505 return -EOPNOTSUPP; 506 } 507 } 508 509 #define AQR_FW_WAIT_SLEEP_US 20000 510 #define AQR_FW_WAIT_TIMEOUT_US 2000000 511 512 /* If we configure settings whilst firmware is still initializing the chip, 513 * then these settings may be overwritten. Therefore make sure chip 514 * initialization has completed. Use presence of the firmware ID as 515 * indicator for initialization having completed. 516 * The chip also provides a "reset completed" bit, but it's cleared after 517 * read. Therefore function would time out if called again. 518 */ 519 int aqr_wait_reset_complete(struct phy_device *phydev) 520 { 521 int ret, val; 522 523 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 524 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 525 false, phydev, MDIO_MMD_VEND1, 526 VEND1_GLOBAL_FW_ID); 527 if (val < 0) { 528 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 529 ERR_PTR(val)); 530 return val; 531 } 532 533 return ret; 534 } 535 536 static void aqr107_chip_info(struct phy_device *phydev) 537 { 538 u8 fw_major, fw_minor, build_id, prov_id; 539 int val; 540 541 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 542 if (val < 0) 543 return; 544 545 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 546 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 547 548 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 549 if (val < 0) 550 return; 551 552 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 553 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 554 555 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 556 fw_major, fw_minor, build_id, prov_id); 557 } 558 559 static int aqr107_config_mdi(struct phy_device *phydev) 560 { 561 struct device_node *np = phydev->mdio.dev.of_node; 562 u32 mdi_conf; 563 int ret; 564 565 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); 566 567 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ 568 if (ret == -EINVAL || ret == -ENOSYS) 569 return 0; 570 571 if (ret) 572 return ret; 573 574 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) 575 return -EINVAL; 576 577 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, 578 PMAPMD_RSVD_VEND_PROV_MDI_CONF, 579 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); 580 } 581 582 static int aqr107_config_init(struct phy_device *phydev) 583 { 584 struct aqr107_priv *priv = phydev->priv; 585 u32 led_idx; 586 int ret; 587 588 /* Check that the PHY interface type is compatible */ 589 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 590 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 591 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 592 phydev->interface != PHY_INTERFACE_MODE_XGMII && 593 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 594 phydev->interface != PHY_INTERFACE_MODE_10GKR && 595 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 596 phydev->interface != PHY_INTERFACE_MODE_XAUI && 597 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 598 return -ENODEV; 599 600 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 601 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 602 603 ret = aqr_wait_reset_complete(phydev); 604 if (!ret) 605 aqr107_chip_info(phydev); 606 607 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 608 if (ret) 609 return ret; 610 611 ret = aqr107_config_mdi(phydev); 612 if (ret) 613 return ret; 614 615 /* Restore LED polarity state after reset */ 616 for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) { 617 ret = aqr_phy_led_active_low_set(phydev, led_idx, true); 618 if (ret) 619 return ret; 620 } 621 622 for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) { 623 ret = aqr_phy_led_active_low_set(phydev, led_idx, false); 624 if (ret) 625 return ret; 626 } 627 628 return 0; 629 } 630 631 static int aqcs109_config_init(struct phy_device *phydev) 632 { 633 int ret; 634 635 /* Check that the PHY interface type is compatible */ 636 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 637 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 638 return -ENODEV; 639 640 ret = aqr_wait_reset_complete(phydev); 641 if (!ret) 642 aqr107_chip_info(phydev); 643 644 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 645 } 646 647 static void aqr107_link_change_notify(struct phy_device *phydev) 648 { 649 u8 fw_major, fw_minor; 650 bool downshift, short_reach, afr; 651 int mode, val; 652 653 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 654 return; 655 656 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 657 /* call failed or link partner is no Aquantia PHY */ 658 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 659 return; 660 661 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 662 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 663 664 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 665 if (val < 0) 666 return; 667 668 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 669 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 670 671 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 672 if (val < 0) 673 return; 674 675 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 676 677 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 678 fw_major, fw_minor, 679 short_reach ? ", short reach mode" : "", 680 downshift ? ", fast-retrain downshift advertised" : "", 681 afr ? ", fast reframe advertised" : ""); 682 683 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 684 if (val < 0) 685 return; 686 687 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 688 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 689 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 690 } 691 692 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 693 { 694 int val, err; 695 696 /* The datasheet notes to wait at least 1ms after issuing a 697 * processor intensive operation before checking. 698 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 699 * because that just determines the maximum time slept, not the minimum. 700 */ 701 usleep_range(1000, 5000); 702 703 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 704 VEND1_GLOBAL_GEN_STAT2, val, 705 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 706 AQR107_OP_IN_PROG_SLEEP, 707 AQR107_OP_IN_PROG_TIMEOUT, false); 708 if (err) { 709 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 710 return err; 711 } 712 713 return 0; 714 } 715 716 static int aqr107_get_rate_matching(struct phy_device *phydev, 717 phy_interface_t iface) 718 { 719 if (iface == PHY_INTERFACE_MODE_10GBASER || 720 iface == PHY_INTERFACE_MODE_2500BASEX || 721 iface == PHY_INTERFACE_MODE_NA) 722 return RATE_MATCH_PAUSE; 723 return RATE_MATCH_NONE; 724 } 725 726 static int aqr107_suspend(struct phy_device *phydev) 727 { 728 int err; 729 730 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 731 MDIO_CTRL1_LPOWER); 732 if (err) 733 return err; 734 735 return aqr107_wait_processor_intensive_op(phydev); 736 } 737 738 static int aqr107_resume(struct phy_device *phydev) 739 { 740 int err; 741 742 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 743 MDIO_CTRL1_LPOWER); 744 if (err) 745 return err; 746 747 return aqr107_wait_processor_intensive_op(phydev); 748 } 749 750 static const u16 aqr_global_cfg_regs[] = { 751 VEND1_GLOBAL_CFG_10M, 752 VEND1_GLOBAL_CFG_100M, 753 VEND1_GLOBAL_CFG_1G, 754 VEND1_GLOBAL_CFG_2_5G, 755 VEND1_GLOBAL_CFG_5G, 756 VEND1_GLOBAL_CFG_10G 757 }; 758 759 static int aqr107_fill_interface_modes(struct phy_device *phydev) 760 { 761 unsigned long *possible = phydev->possible_interfaces; 762 unsigned int serdes_mode, rate_adapt; 763 phy_interface_t interface; 764 int i, val; 765 766 /* Walk the media-speed configuration registers to determine which 767 * host-side serdes modes may be used by the PHY depending on the 768 * negotiated media speed. 769 */ 770 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 771 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 772 aqr_global_cfg_regs[i]); 773 if (val < 0) 774 return val; 775 776 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 777 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 778 779 switch (serdes_mode) { 780 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 781 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 782 interface = PHY_INTERFACE_MODE_USXGMII; 783 else 784 interface = PHY_INTERFACE_MODE_10GBASER; 785 break; 786 787 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 788 interface = PHY_INTERFACE_MODE_5GBASER; 789 break; 790 791 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 792 interface = PHY_INTERFACE_MODE_2500BASEX; 793 break; 794 795 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 796 interface = PHY_INTERFACE_MODE_SGMII; 797 break; 798 799 default: 800 phydev_warn(phydev, "unrecognised serdes mode %u\n", 801 serdes_mode); 802 interface = PHY_INTERFACE_MODE_NA; 803 break; 804 } 805 806 if (interface != PHY_INTERFACE_MODE_NA) 807 __set_bit(interface, possible); 808 } 809 810 return 0; 811 } 812 813 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 814 { 815 int val, ret; 816 817 /* It's been observed on some models that - when coming out of suspend 818 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 819 * continue on returning zeroes for some time. Let's poll the 100M 820 * register until it returns a real value as both 113c and 115c support 821 * this mode. 822 */ 823 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 824 VEND1_GLOBAL_CFG_100M, val, val != 0, 825 1000, 100000, false); 826 if (ret) 827 return ret; 828 829 return aqr107_fill_interface_modes(phydev); 830 } 831 832 static int aqr115c_get_features(struct phy_device *phydev) 833 { 834 unsigned long *supported = phydev->supported; 835 836 /* PHY supports speeds up to 2.5G with autoneg. PMA capabilities 837 * are not useful. 838 */ 839 linkmode_or(supported, supported, phy_gbit_features); 840 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported); 841 842 return 0; 843 } 844 845 static int aqr111_get_features(struct phy_device *phydev) 846 { 847 /* PHY supports speeds up to 5G with autoneg. PMA capabilities 848 * are not useful. 849 */ 850 aqr115c_get_features(phydev); 851 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 852 phydev->supported); 853 854 return 0; 855 } 856 857 static int aqr113c_config_init(struct phy_device *phydev) 858 { 859 int ret; 860 861 ret = aqr107_config_init(phydev); 862 if (ret < 0) 863 return ret; 864 865 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 866 MDIO_PMD_TXDIS_GLOBAL); 867 if (ret) 868 return ret; 869 870 ret = aqr107_wait_processor_intensive_op(phydev); 871 if (ret) 872 return ret; 873 874 return aqr113c_fill_interface_modes(phydev); 875 } 876 877 static int aqr107_probe(struct phy_device *phydev) 878 { 879 int ret; 880 881 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 882 sizeof(struct aqr107_priv), GFP_KERNEL); 883 if (!phydev->priv) 884 return -ENOMEM; 885 886 ret = aqr_firmware_load(phydev); 887 if (ret) 888 return ret; 889 890 return aqr_hwmon_probe(phydev); 891 } 892 893 894 static struct phy_driver aqr_driver[] = { 895 { 896 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 897 .name = "Aquantia AQ1202", 898 .config_aneg = aqr_config_aneg, 899 .config_intr = aqr_config_intr, 900 .handle_interrupt = aqr_handle_interrupt, 901 .read_status = aqr_read_status, 902 }, 903 { 904 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 905 .name = "Aquantia AQ2104", 906 .config_aneg = aqr_config_aneg, 907 .config_intr = aqr_config_intr, 908 .handle_interrupt = aqr_handle_interrupt, 909 .read_status = aqr_read_status, 910 }, 911 { 912 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 913 .name = "Aquantia AQR105", 914 .config_aneg = aqr_config_aneg, 915 .config_intr = aqr_config_intr, 916 .handle_interrupt = aqr_handle_interrupt, 917 .read_status = aqr_read_status, 918 .suspend = aqr107_suspend, 919 .resume = aqr107_resume, 920 }, 921 { 922 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 923 .name = "Aquantia AQR106", 924 .config_aneg = aqr_config_aneg, 925 .config_intr = aqr_config_intr, 926 .handle_interrupt = aqr_handle_interrupt, 927 .read_status = aqr_read_status, 928 }, 929 { 930 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 931 .name = "Aquantia AQR107", 932 .probe = aqr107_probe, 933 .get_rate_matching = aqr107_get_rate_matching, 934 .config_init = aqr107_config_init, 935 .config_aneg = aqr_config_aneg, 936 .config_intr = aqr_config_intr, 937 .handle_interrupt = aqr_handle_interrupt, 938 .read_status = aqr107_read_status, 939 .get_tunable = aqr107_get_tunable, 940 .set_tunable = aqr107_set_tunable, 941 .suspend = aqr107_suspend, 942 .resume = aqr107_resume, 943 .get_sset_count = aqr107_get_sset_count, 944 .get_strings = aqr107_get_strings, 945 .get_stats = aqr107_get_stats, 946 .link_change_notify = aqr107_link_change_notify, 947 .led_brightness_set = aqr_phy_led_brightness_set, 948 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 949 .led_hw_control_set = aqr_phy_led_hw_control_set, 950 .led_hw_control_get = aqr_phy_led_hw_control_get, 951 .led_polarity_set = aqr_phy_led_polarity_set, 952 }, 953 { 954 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 955 .name = "Aquantia AQCS109", 956 .probe = aqr107_probe, 957 .get_rate_matching = aqr107_get_rate_matching, 958 .config_init = aqcs109_config_init, 959 .config_aneg = aqr_config_aneg, 960 .config_intr = aqr_config_intr, 961 .handle_interrupt = aqr_handle_interrupt, 962 .read_status = aqr107_read_status, 963 .get_tunable = aqr107_get_tunable, 964 .set_tunable = aqr107_set_tunable, 965 .suspend = aqr107_suspend, 966 .resume = aqr107_resume, 967 .get_sset_count = aqr107_get_sset_count, 968 .get_strings = aqr107_get_strings, 969 .get_stats = aqr107_get_stats, 970 .get_features = aqr115c_get_features, 971 .link_change_notify = aqr107_link_change_notify, 972 .led_brightness_set = aqr_phy_led_brightness_set, 973 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 974 .led_hw_control_set = aqr_phy_led_hw_control_set, 975 .led_hw_control_get = aqr_phy_led_hw_control_get, 976 .led_polarity_set = aqr_phy_led_polarity_set, 977 }, 978 { 979 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 980 .name = "Aquantia AQR111", 981 .probe = aqr107_probe, 982 .get_rate_matching = aqr107_get_rate_matching, 983 .config_init = aqr107_config_init, 984 .config_aneg = aqr_config_aneg, 985 .config_intr = aqr_config_intr, 986 .handle_interrupt = aqr_handle_interrupt, 987 .read_status = aqr107_read_status, 988 .get_tunable = aqr107_get_tunable, 989 .set_tunable = aqr107_set_tunable, 990 .suspend = aqr107_suspend, 991 .resume = aqr107_resume, 992 .get_sset_count = aqr107_get_sset_count, 993 .get_strings = aqr107_get_strings, 994 .get_stats = aqr107_get_stats, 995 .get_features = aqr111_get_features, 996 .link_change_notify = aqr107_link_change_notify, 997 .led_brightness_set = aqr_phy_led_brightness_set, 998 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 999 .led_hw_control_set = aqr_phy_led_hw_control_set, 1000 .led_hw_control_get = aqr_phy_led_hw_control_get, 1001 .led_polarity_set = aqr_phy_led_polarity_set, 1002 }, 1003 { 1004 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 1005 .name = "Aquantia AQR111B0", 1006 .probe = aqr107_probe, 1007 .get_rate_matching = aqr107_get_rate_matching, 1008 .config_init = aqr107_config_init, 1009 .config_aneg = aqr_config_aneg, 1010 .config_intr = aqr_config_intr, 1011 .handle_interrupt = aqr_handle_interrupt, 1012 .read_status = aqr107_read_status, 1013 .get_tunable = aqr107_get_tunable, 1014 .set_tunable = aqr107_set_tunable, 1015 .suspend = aqr107_suspend, 1016 .resume = aqr107_resume, 1017 .get_sset_count = aqr107_get_sset_count, 1018 .get_strings = aqr107_get_strings, 1019 .get_stats = aqr107_get_stats, 1020 .get_features = aqr111_get_features, 1021 .link_change_notify = aqr107_link_change_notify, 1022 .led_brightness_set = aqr_phy_led_brightness_set, 1023 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1024 .led_hw_control_set = aqr_phy_led_hw_control_set, 1025 .led_hw_control_get = aqr_phy_led_hw_control_get, 1026 .led_polarity_set = aqr_phy_led_polarity_set, 1027 }, 1028 { 1029 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 1030 .name = "Aquantia AQR405", 1031 .config_aneg = aqr_config_aneg, 1032 .config_intr = aqr_config_intr, 1033 .handle_interrupt = aqr_handle_interrupt, 1034 .read_status = aqr_read_status, 1035 }, 1036 { 1037 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 1038 .name = "Aquantia AQR112", 1039 .probe = aqr107_probe, 1040 .config_aneg = aqr_config_aneg, 1041 .config_intr = aqr_config_intr, 1042 .handle_interrupt = aqr_handle_interrupt, 1043 .get_tunable = aqr107_get_tunable, 1044 .set_tunable = aqr107_set_tunable, 1045 .suspend = aqr107_suspend, 1046 .resume = aqr107_resume, 1047 .read_status = aqr107_read_status, 1048 .get_rate_matching = aqr107_get_rate_matching, 1049 .get_sset_count = aqr107_get_sset_count, 1050 .get_strings = aqr107_get_strings, 1051 .get_stats = aqr107_get_stats, 1052 .link_change_notify = aqr107_link_change_notify, 1053 .led_brightness_set = aqr_phy_led_brightness_set, 1054 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1055 .led_hw_control_set = aqr_phy_led_hw_control_set, 1056 .led_hw_control_get = aqr_phy_led_hw_control_get, 1057 .led_polarity_set = aqr_phy_led_polarity_set, 1058 }, 1059 { 1060 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 1061 .name = "Aquantia AQR412", 1062 .probe = aqr107_probe, 1063 .config_aneg = aqr_config_aneg, 1064 .config_intr = aqr_config_intr, 1065 .handle_interrupt = aqr_handle_interrupt, 1066 .get_tunable = aqr107_get_tunable, 1067 .set_tunable = aqr107_set_tunable, 1068 .suspend = aqr107_suspend, 1069 .resume = aqr107_resume, 1070 .read_status = aqr107_read_status, 1071 .get_rate_matching = aqr107_get_rate_matching, 1072 .get_sset_count = aqr107_get_sset_count, 1073 .get_strings = aqr107_get_strings, 1074 .get_stats = aqr107_get_stats, 1075 .link_change_notify = aqr107_link_change_notify, 1076 }, 1077 { 1078 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 1079 .name = "Aquantia AQR113", 1080 .probe = aqr107_probe, 1081 .get_rate_matching = aqr107_get_rate_matching, 1082 .config_init = aqr113c_config_init, 1083 .config_aneg = aqr_config_aneg, 1084 .config_intr = aqr_config_intr, 1085 .handle_interrupt = aqr_handle_interrupt, 1086 .read_status = aqr107_read_status, 1087 .get_tunable = aqr107_get_tunable, 1088 .set_tunable = aqr107_set_tunable, 1089 .suspend = aqr107_suspend, 1090 .resume = aqr107_resume, 1091 .get_sset_count = aqr107_get_sset_count, 1092 .get_strings = aqr107_get_strings, 1093 .get_stats = aqr107_get_stats, 1094 .link_change_notify = aqr107_link_change_notify, 1095 .led_brightness_set = aqr_phy_led_brightness_set, 1096 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1097 .led_hw_control_set = aqr_phy_led_hw_control_set, 1098 .led_hw_control_get = aqr_phy_led_hw_control_get, 1099 .led_polarity_set = aqr_phy_led_polarity_set, 1100 }, 1101 { 1102 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 1103 .name = "Aquantia AQR113C", 1104 .probe = aqr107_probe, 1105 .get_rate_matching = aqr107_get_rate_matching, 1106 .config_init = aqr113c_config_init, 1107 .config_aneg = aqr_config_aneg, 1108 .config_intr = aqr_config_intr, 1109 .handle_interrupt = aqr_handle_interrupt, 1110 .read_status = aqr107_read_status, 1111 .get_tunable = aqr107_get_tunable, 1112 .set_tunable = aqr107_set_tunable, 1113 .suspend = aqr107_suspend, 1114 .resume = aqr107_resume, 1115 .get_sset_count = aqr107_get_sset_count, 1116 .get_strings = aqr107_get_strings, 1117 .get_stats = aqr107_get_stats, 1118 .link_change_notify = aqr107_link_change_notify, 1119 .led_brightness_set = aqr_phy_led_brightness_set, 1120 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1121 .led_hw_control_set = aqr_phy_led_hw_control_set, 1122 .led_hw_control_get = aqr_phy_led_hw_control_get, 1123 .led_polarity_set = aqr_phy_led_polarity_set, 1124 }, 1125 { 1126 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1127 .name = "Aquantia AQR114C", 1128 .probe = aqr107_probe, 1129 .get_rate_matching = aqr107_get_rate_matching, 1130 .config_init = aqr107_config_init, 1131 .config_aneg = aqr_config_aneg, 1132 .config_intr = aqr_config_intr, 1133 .handle_interrupt = aqr_handle_interrupt, 1134 .read_status = aqr107_read_status, 1135 .get_tunable = aqr107_get_tunable, 1136 .set_tunable = aqr107_set_tunable, 1137 .suspend = aqr107_suspend, 1138 .resume = aqr107_resume, 1139 .get_sset_count = aqr107_get_sset_count, 1140 .get_strings = aqr107_get_strings, 1141 .get_stats = aqr107_get_stats, 1142 .get_features = aqr111_get_features, 1143 .link_change_notify = aqr107_link_change_notify, 1144 .led_brightness_set = aqr_phy_led_brightness_set, 1145 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1146 .led_hw_control_set = aqr_phy_led_hw_control_set, 1147 .led_hw_control_get = aqr_phy_led_hw_control_get, 1148 .led_polarity_set = aqr_phy_led_polarity_set, 1149 }, 1150 { 1151 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1152 .name = "Aquantia AQR115C", 1153 .probe = aqr107_probe, 1154 .get_rate_matching = aqr107_get_rate_matching, 1155 .config_init = aqr113c_config_init, 1156 .config_aneg = aqr_config_aneg, 1157 .config_intr = aqr_config_intr, 1158 .handle_interrupt = aqr_handle_interrupt, 1159 .read_status = aqr107_read_status, 1160 .get_tunable = aqr107_get_tunable, 1161 .set_tunable = aqr107_set_tunable, 1162 .suspend = aqr107_suspend, 1163 .resume = aqr107_resume, 1164 .get_sset_count = aqr107_get_sset_count, 1165 .get_strings = aqr107_get_strings, 1166 .get_stats = aqr107_get_stats, 1167 .get_features = aqr115c_get_features, 1168 .link_change_notify = aqr107_link_change_notify, 1169 .led_brightness_set = aqr_phy_led_brightness_set, 1170 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1171 .led_hw_control_set = aqr_phy_led_hw_control_set, 1172 .led_hw_control_get = aqr_phy_led_hw_control_get, 1173 .led_polarity_set = aqr_phy_led_polarity_set, 1174 }, 1175 { 1176 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1177 .name = "Aquantia AQR813", 1178 .probe = aqr107_probe, 1179 .get_rate_matching = aqr107_get_rate_matching, 1180 .config_init = aqr107_config_init, 1181 .config_aneg = aqr_config_aneg, 1182 .config_intr = aqr_config_intr, 1183 .handle_interrupt = aqr_handle_interrupt, 1184 .read_status = aqr107_read_status, 1185 .get_tunable = aqr107_get_tunable, 1186 .set_tunable = aqr107_set_tunable, 1187 .suspend = aqr107_suspend, 1188 .resume = aqr107_resume, 1189 .get_sset_count = aqr107_get_sset_count, 1190 .get_strings = aqr107_get_strings, 1191 .get_stats = aqr107_get_stats, 1192 .link_change_notify = aqr107_link_change_notify, 1193 .led_brightness_set = aqr_phy_led_brightness_set, 1194 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1195 .led_hw_control_set = aqr_phy_led_hw_control_set, 1196 .led_hw_control_get = aqr_phy_led_hw_control_get, 1197 .led_polarity_set = aqr_phy_led_polarity_set, 1198 }, 1199 }; 1200 1201 module_phy_driver(aqr_driver); 1202 1203 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1204 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1205 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1206 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1207 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1208 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1209 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1210 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1211 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1212 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1213 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1214 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1215 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1216 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1217 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1218 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1219 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1220 { } 1221 }; 1222 1223 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1224 1225 MODULE_DESCRIPTION("Aquantia PHY driver"); 1226 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1227 MODULE_LICENSE("GPL v2"); 1228