1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 17 #include "aquantia.h" 18 19 #define PHY_ID_AQ1202 0x03a1b445 20 #define PHY_ID_AQ2104 0x03a1b460 21 #define PHY_ID_AQR105 0x03a1b4a2 22 #define PHY_ID_AQR106 0x03a1b4d0 23 #define PHY_ID_AQR107 0x03a1b4e0 24 #define PHY_ID_AQCS109 0x03a1b5c2 25 #define PHY_ID_AQR405 0x03a1b4b0 26 #define PHY_ID_AQR111 0x03a1b610 27 #define PHY_ID_AQR111B0 0x03a1b612 28 #define PHY_ID_AQR112 0x03a1b662 29 #define PHY_ID_AQR412 0x03a1b712 30 #define PHY_ID_AQR113 0x31c31c40 31 #define PHY_ID_AQR113C 0x31c31c12 32 #define PHY_ID_AQR114C 0x31c31c22 33 #define PHY_ID_AQR115C 0x31c31c33 34 #define PHY_ID_AQR813 0x31c31cb2 35 36 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9 46 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 47 48 #define MDIO_AN_VEND_PROV 0xc400 49 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 50 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 51 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 52 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 53 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 54 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 55 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 56 57 #define MDIO_AN_TX_VEND_STATUS1 0xc800 58 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 59 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 60 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 61 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 62 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 63 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 64 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 65 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 66 67 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 68 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 69 70 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 71 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 72 73 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 74 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 75 76 #define PMAPMD_RSVD_VEND_PROV 0xe400 77 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) 78 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) 79 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) 80 81 #define MDIO_AN_RX_LP_STAT1 0xe820 82 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 83 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 84 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 85 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 86 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 87 88 #define MDIO_AN_RX_LP_STAT4 0xe823 89 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 90 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 91 92 #define MDIO_AN_RX_VEND_STAT3 0xe832 93 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 94 95 /* Sleep and timeout for checking if the Processor-Intensive 96 * MDIO operation is finished 97 */ 98 #define AQR107_OP_IN_PROG_SLEEP 1000 99 #define AQR107_OP_IN_PROG_TIMEOUT 100000 100 101 static int aqr107_get_sset_count(struct phy_device *phydev) 102 { 103 return AQR107_SGMII_STAT_SZ; 104 } 105 106 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 107 { 108 int i; 109 110 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 111 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 112 ETH_GSTRING_LEN); 113 } 114 115 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 116 { 117 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 118 int len_l = min(stat->size, 16); 119 int len_h = stat->size - len_l; 120 u64 ret; 121 int val; 122 123 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 124 if (val < 0) 125 return U64_MAX; 126 127 ret = val & GENMASK(len_l - 1, 0); 128 if (len_h) { 129 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 130 if (val < 0) 131 return U64_MAX; 132 133 ret += (val & GENMASK(len_h - 1, 0)) << 16; 134 } 135 136 return ret; 137 } 138 139 static void aqr107_get_stats(struct phy_device *phydev, 140 struct ethtool_stats *stats, u64 *data) 141 { 142 struct aqr107_priv *priv = phydev->priv; 143 u64 val; 144 int i; 145 146 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 147 val = aqr107_get_stat(phydev, i); 148 if (val == U64_MAX) 149 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 150 aqr107_hw_stats[i].name); 151 else 152 priv->sgmii_stats[i] += val; 153 154 data[i] = priv->sgmii_stats[i]; 155 } 156 } 157 158 static int aqr_config_aneg(struct phy_device *phydev) 159 { 160 bool changed = false; 161 u16 reg; 162 int ret; 163 164 if (phydev->autoneg == AUTONEG_DISABLE) 165 return genphy_c45_pma_setup_forced(phydev); 166 167 ret = genphy_c45_an_config_aneg(phydev); 168 if (ret < 0) 169 return ret; 170 if (ret > 0) 171 changed = true; 172 173 /* Clause 45 has no standardized support for 1000BaseT, therefore 174 * use vendor registers for this mode. 175 */ 176 reg = 0; 177 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 178 phydev->advertising)) 179 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 180 181 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 182 phydev->advertising)) 183 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 184 185 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 186 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 187 phydev->advertising)) 188 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 189 190 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 191 phydev->advertising)) 192 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 193 194 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 195 MDIO_AN_VEND_PROV_1000BASET_HALF | 196 MDIO_AN_VEND_PROV_1000BASET_FULL | 197 MDIO_AN_VEND_PROV_2500BASET_FULL | 198 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 199 if (ret < 0) 200 return ret; 201 if (ret > 0) 202 changed = true; 203 204 return genphy_c45_check_and_restart_aneg(phydev, changed); 205 } 206 207 static int aqr_config_intr(struct phy_device *phydev) 208 { 209 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 210 int err; 211 212 if (en) { 213 /* Clear any pending interrupts before enabling them */ 214 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 215 if (err < 0) 216 return err; 217 } 218 219 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 220 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 221 if (err < 0) 222 return err; 223 224 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 225 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 226 if (err < 0) 227 return err; 228 229 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 230 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 231 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 232 if (err < 0) 233 return err; 234 235 if (!en) { 236 /* Clear any pending interrupts after we have disabled them */ 237 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 238 if (err < 0) 239 return err; 240 } 241 242 return 0; 243 } 244 245 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 246 { 247 int irq_status; 248 249 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 250 MDIO_AN_TX_VEND_INT_STATUS2); 251 if (irq_status < 0) { 252 phy_error(phydev); 253 return IRQ_NONE; 254 } 255 256 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 257 return IRQ_NONE; 258 259 phy_trigger_machine(phydev); 260 261 return IRQ_HANDLED; 262 } 263 264 static int aqr_read_status(struct phy_device *phydev) 265 { 266 int val; 267 268 if (phydev->autoneg == AUTONEG_ENABLE) { 269 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 270 if (val < 0) 271 return val; 272 273 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 274 phydev->lp_advertising, 275 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 276 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 277 phydev->lp_advertising, 278 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 279 } 280 281 return genphy_c45_read_status(phydev); 282 } 283 284 static int aqr107_read_rate(struct phy_device *phydev) 285 { 286 u32 config_reg; 287 int val; 288 289 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 290 if (val < 0) 291 return val; 292 293 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 294 phydev->duplex = DUPLEX_FULL; 295 else 296 phydev->duplex = DUPLEX_HALF; 297 298 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 299 case MDIO_AN_TX_VEND_STATUS1_10BASET: 300 phydev->speed = SPEED_10; 301 config_reg = VEND1_GLOBAL_CFG_10M; 302 break; 303 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 304 phydev->speed = SPEED_100; 305 config_reg = VEND1_GLOBAL_CFG_100M; 306 break; 307 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 308 phydev->speed = SPEED_1000; 309 config_reg = VEND1_GLOBAL_CFG_1G; 310 break; 311 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 312 phydev->speed = SPEED_2500; 313 config_reg = VEND1_GLOBAL_CFG_2_5G; 314 break; 315 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 316 phydev->speed = SPEED_5000; 317 config_reg = VEND1_GLOBAL_CFG_5G; 318 break; 319 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 320 phydev->speed = SPEED_10000; 321 config_reg = VEND1_GLOBAL_CFG_10G; 322 break; 323 default: 324 phydev->speed = SPEED_UNKNOWN; 325 return 0; 326 } 327 328 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 329 if (val < 0) 330 return val; 331 332 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 333 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 334 phydev->rate_matching = RATE_MATCH_PAUSE; 335 else 336 phydev->rate_matching = RATE_MATCH_NONE; 337 338 return 0; 339 } 340 341 static int aqr107_read_status(struct phy_device *phydev) 342 { 343 int val, ret; 344 345 ret = aqr_read_status(phydev); 346 if (ret) 347 return ret; 348 349 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 350 return 0; 351 352 /** 353 * The status register is not immediately correct on line side link up. 354 * Poll periodically until it reflects the correct ON state. 355 * Only return fail for read error, timeout defaults to OFF state. 356 */ 357 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 358 MDIO_PHYXS_VEND_IF_STATUS, val, 359 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 360 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 361 AQR107_OP_IN_PROG_SLEEP, 362 AQR107_OP_IN_PROG_TIMEOUT, false); 363 if (ret && ret != -ETIMEDOUT) 364 return ret; 365 366 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 367 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 368 phydev->interface = PHY_INTERFACE_MODE_10GKR; 369 break; 370 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 371 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 372 break; 373 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 374 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 375 break; 376 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 377 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 378 break; 379 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 380 phydev->interface = PHY_INTERFACE_MODE_XAUI; 381 break; 382 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 383 phydev->interface = PHY_INTERFACE_MODE_SGMII; 384 break; 385 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 386 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 387 break; 388 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 389 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 390 break; 391 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 392 default: 393 phydev->link = false; 394 phydev->interface = PHY_INTERFACE_MODE_NA; 395 break; 396 } 397 398 /* Read possibly downshifted rate from vendor register */ 399 return aqr107_read_rate(phydev); 400 } 401 402 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 403 { 404 int val, cnt, enable; 405 406 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 407 if (val < 0) 408 return val; 409 410 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 411 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 412 413 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 414 415 return 0; 416 } 417 418 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 419 { 420 int val = 0; 421 422 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 423 return -E2BIG; 424 425 if (cnt != DOWNSHIFT_DEV_DISABLE) { 426 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 427 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 428 } 429 430 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 431 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 432 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 433 } 434 435 static int aqr107_get_tunable(struct phy_device *phydev, 436 struct ethtool_tunable *tuna, void *data) 437 { 438 switch (tuna->id) { 439 case ETHTOOL_PHY_DOWNSHIFT: 440 return aqr107_get_downshift(phydev, data); 441 default: 442 return -EOPNOTSUPP; 443 } 444 } 445 446 static int aqr107_set_tunable(struct phy_device *phydev, 447 struct ethtool_tunable *tuna, const void *data) 448 { 449 switch (tuna->id) { 450 case ETHTOOL_PHY_DOWNSHIFT: 451 return aqr107_set_downshift(phydev, *(const u8 *)data); 452 default: 453 return -EOPNOTSUPP; 454 } 455 } 456 457 #define AQR_FW_WAIT_SLEEP_US 20000 458 #define AQR_FW_WAIT_TIMEOUT_US 2000000 459 460 /* If we configure settings whilst firmware is still initializing the chip, 461 * then these settings may be overwritten. Therefore make sure chip 462 * initialization has completed. Use presence of the firmware ID as 463 * indicator for initialization having completed. 464 * The chip also provides a "reset completed" bit, but it's cleared after 465 * read. Therefore function would time out if called again. 466 */ 467 int aqr_wait_reset_complete(struct phy_device *phydev) 468 { 469 int ret, val; 470 471 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 472 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 473 false, phydev, MDIO_MMD_VEND1, 474 VEND1_GLOBAL_FW_ID); 475 if (val < 0) { 476 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 477 ERR_PTR(val)); 478 return val; 479 } 480 481 return ret; 482 } 483 484 static void aqr107_chip_info(struct phy_device *phydev) 485 { 486 u8 fw_major, fw_minor, build_id, prov_id; 487 int val; 488 489 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 490 if (val < 0) 491 return; 492 493 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 494 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 495 496 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 497 if (val < 0) 498 return; 499 500 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 501 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 502 503 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 504 fw_major, fw_minor, build_id, prov_id); 505 } 506 507 static int aqr107_config_mdi(struct phy_device *phydev) 508 { 509 struct device_node *np = phydev->mdio.dev.of_node; 510 u32 mdi_conf; 511 int ret; 512 513 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); 514 515 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ 516 if (ret == -EINVAL || ret == -ENOSYS) 517 return 0; 518 519 if (ret) 520 return ret; 521 522 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) 523 return -EINVAL; 524 525 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, 526 PMAPMD_RSVD_VEND_PROV_MDI_CONF, 527 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); 528 } 529 530 static int aqr107_config_init(struct phy_device *phydev) 531 { 532 struct aqr107_priv *priv = phydev->priv; 533 u32 led_idx; 534 int ret; 535 536 /* Check that the PHY interface type is compatible */ 537 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 538 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 539 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 540 phydev->interface != PHY_INTERFACE_MODE_XGMII && 541 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 542 phydev->interface != PHY_INTERFACE_MODE_10GKR && 543 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 544 phydev->interface != PHY_INTERFACE_MODE_XAUI && 545 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 546 return -ENODEV; 547 548 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 549 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 550 551 ret = aqr_wait_reset_complete(phydev); 552 if (!ret) 553 aqr107_chip_info(phydev); 554 555 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 556 if (ret) 557 return ret; 558 559 ret = aqr107_config_mdi(phydev); 560 if (ret) 561 return ret; 562 563 /* Restore LED polarity state after reset */ 564 for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) { 565 ret = aqr_phy_led_active_low_set(phydev, led_idx, true); 566 if (ret) 567 return ret; 568 } 569 570 for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) { 571 ret = aqr_phy_led_active_low_set(phydev, led_idx, false); 572 if (ret) 573 return ret; 574 } 575 576 return 0; 577 } 578 579 static int aqcs109_config_init(struct phy_device *phydev) 580 { 581 int ret; 582 583 /* Check that the PHY interface type is compatible */ 584 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 585 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 586 return -ENODEV; 587 588 ret = aqr_wait_reset_complete(phydev); 589 if (!ret) 590 aqr107_chip_info(phydev); 591 592 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 593 } 594 595 static void aqr107_link_change_notify(struct phy_device *phydev) 596 { 597 u8 fw_major, fw_minor; 598 bool downshift, short_reach, afr; 599 int mode, val; 600 601 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 602 return; 603 604 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 605 /* call failed or link partner is no Aquantia PHY */ 606 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 607 return; 608 609 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 610 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 611 612 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 613 if (val < 0) 614 return; 615 616 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 617 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 618 619 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 620 if (val < 0) 621 return; 622 623 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 624 625 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 626 fw_major, fw_minor, 627 short_reach ? ", short reach mode" : "", 628 downshift ? ", fast-retrain downshift advertised" : "", 629 afr ? ", fast reframe advertised" : ""); 630 631 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 632 if (val < 0) 633 return; 634 635 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 636 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 637 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 638 } 639 640 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 641 { 642 int val, err; 643 644 /* The datasheet notes to wait at least 1ms after issuing a 645 * processor intensive operation before checking. 646 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 647 * because that just determines the maximum time slept, not the minimum. 648 */ 649 usleep_range(1000, 5000); 650 651 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 652 VEND1_GLOBAL_GEN_STAT2, val, 653 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 654 AQR107_OP_IN_PROG_SLEEP, 655 AQR107_OP_IN_PROG_TIMEOUT, false); 656 if (err) { 657 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 658 return err; 659 } 660 661 return 0; 662 } 663 664 static int aqr107_get_rate_matching(struct phy_device *phydev, 665 phy_interface_t iface) 666 { 667 if (iface == PHY_INTERFACE_MODE_10GBASER || 668 iface == PHY_INTERFACE_MODE_2500BASEX || 669 iface == PHY_INTERFACE_MODE_NA) 670 return RATE_MATCH_PAUSE; 671 return RATE_MATCH_NONE; 672 } 673 674 static int aqr107_suspend(struct phy_device *phydev) 675 { 676 int err; 677 678 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 679 MDIO_CTRL1_LPOWER); 680 if (err) 681 return err; 682 683 return aqr107_wait_processor_intensive_op(phydev); 684 } 685 686 static int aqr107_resume(struct phy_device *phydev) 687 { 688 int err; 689 690 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 691 MDIO_CTRL1_LPOWER); 692 if (err) 693 return err; 694 695 return aqr107_wait_processor_intensive_op(phydev); 696 } 697 698 static const u16 aqr_global_cfg_regs[] = { 699 VEND1_GLOBAL_CFG_10M, 700 VEND1_GLOBAL_CFG_100M, 701 VEND1_GLOBAL_CFG_1G, 702 VEND1_GLOBAL_CFG_2_5G, 703 VEND1_GLOBAL_CFG_5G, 704 VEND1_GLOBAL_CFG_10G 705 }; 706 707 static int aqr107_fill_interface_modes(struct phy_device *phydev) 708 { 709 unsigned long *possible = phydev->possible_interfaces; 710 unsigned int serdes_mode, rate_adapt; 711 phy_interface_t interface; 712 int i, val; 713 714 /* Walk the media-speed configuration registers to determine which 715 * host-side serdes modes may be used by the PHY depending on the 716 * negotiated media speed. 717 */ 718 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 719 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 720 aqr_global_cfg_regs[i]); 721 if (val < 0) 722 return val; 723 724 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 725 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 726 727 switch (serdes_mode) { 728 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 729 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 730 interface = PHY_INTERFACE_MODE_USXGMII; 731 else 732 interface = PHY_INTERFACE_MODE_10GBASER; 733 break; 734 735 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 736 interface = PHY_INTERFACE_MODE_5GBASER; 737 break; 738 739 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 740 interface = PHY_INTERFACE_MODE_2500BASEX; 741 break; 742 743 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 744 interface = PHY_INTERFACE_MODE_SGMII; 745 break; 746 747 default: 748 phydev_warn(phydev, "unrecognised serdes mode %u\n", 749 serdes_mode); 750 interface = PHY_INTERFACE_MODE_NA; 751 break; 752 } 753 754 if (interface != PHY_INTERFACE_MODE_NA) 755 __set_bit(interface, possible); 756 } 757 758 return 0; 759 } 760 761 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 762 { 763 int val, ret; 764 765 /* It's been observed on some models that - when coming out of suspend 766 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 767 * continue on returning zeroes for some time. Let's poll the 100M 768 * register until it returns a real value as both 113c and 115c support 769 * this mode. 770 */ 771 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 772 VEND1_GLOBAL_CFG_100M, val, val != 0, 773 1000, 100000, false); 774 if (ret) 775 return ret; 776 777 return aqr107_fill_interface_modes(phydev); 778 } 779 780 static int aqr115c_get_features(struct phy_device *phydev) 781 { 782 unsigned long *supported = phydev->supported; 783 784 /* PHY supports speeds up to 2.5G with autoneg. PMA capabilities 785 * are not useful. 786 */ 787 linkmode_or(supported, supported, phy_gbit_features); 788 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported); 789 790 return 0; 791 } 792 793 static int aqr111_get_features(struct phy_device *phydev) 794 { 795 /* PHY supports speeds up to 5G with autoneg. PMA capabilities 796 * are not useful. 797 */ 798 aqr115c_get_features(phydev); 799 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 800 phydev->supported); 801 802 return 0; 803 } 804 805 static int aqr113c_config_init(struct phy_device *phydev) 806 { 807 int ret; 808 809 ret = aqr107_config_init(phydev); 810 if (ret < 0) 811 return ret; 812 813 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 814 MDIO_PMD_TXDIS_GLOBAL); 815 if (ret) 816 return ret; 817 818 ret = aqr107_wait_processor_intensive_op(phydev); 819 if (ret) 820 return ret; 821 822 return aqr113c_fill_interface_modes(phydev); 823 } 824 825 static int aqr107_probe(struct phy_device *phydev) 826 { 827 int ret; 828 829 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 830 sizeof(struct aqr107_priv), GFP_KERNEL); 831 if (!phydev->priv) 832 return -ENOMEM; 833 834 ret = aqr_firmware_load(phydev); 835 if (ret) 836 return ret; 837 838 return aqr_hwmon_probe(phydev); 839 } 840 841 842 static struct phy_driver aqr_driver[] = { 843 { 844 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 845 .name = "Aquantia AQ1202", 846 .config_aneg = aqr_config_aneg, 847 .config_intr = aqr_config_intr, 848 .handle_interrupt = aqr_handle_interrupt, 849 .read_status = aqr_read_status, 850 }, 851 { 852 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 853 .name = "Aquantia AQ2104", 854 .config_aneg = aqr_config_aneg, 855 .config_intr = aqr_config_intr, 856 .handle_interrupt = aqr_handle_interrupt, 857 .read_status = aqr_read_status, 858 }, 859 { 860 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 861 .name = "Aquantia AQR105", 862 .config_aneg = aqr_config_aneg, 863 .config_intr = aqr_config_intr, 864 .handle_interrupt = aqr_handle_interrupt, 865 .read_status = aqr_read_status, 866 .suspend = aqr107_suspend, 867 .resume = aqr107_resume, 868 }, 869 { 870 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 871 .name = "Aquantia AQR106", 872 .config_aneg = aqr_config_aneg, 873 .config_intr = aqr_config_intr, 874 .handle_interrupt = aqr_handle_interrupt, 875 .read_status = aqr_read_status, 876 }, 877 { 878 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 879 .name = "Aquantia AQR107", 880 .probe = aqr107_probe, 881 .get_rate_matching = aqr107_get_rate_matching, 882 .config_init = aqr107_config_init, 883 .config_aneg = aqr_config_aneg, 884 .config_intr = aqr_config_intr, 885 .handle_interrupt = aqr_handle_interrupt, 886 .read_status = aqr107_read_status, 887 .get_tunable = aqr107_get_tunable, 888 .set_tunable = aqr107_set_tunable, 889 .suspend = aqr107_suspend, 890 .resume = aqr107_resume, 891 .get_sset_count = aqr107_get_sset_count, 892 .get_strings = aqr107_get_strings, 893 .get_stats = aqr107_get_stats, 894 .link_change_notify = aqr107_link_change_notify, 895 .led_brightness_set = aqr_phy_led_brightness_set, 896 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 897 .led_hw_control_set = aqr_phy_led_hw_control_set, 898 .led_hw_control_get = aqr_phy_led_hw_control_get, 899 .led_polarity_set = aqr_phy_led_polarity_set, 900 }, 901 { 902 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 903 .name = "Aquantia AQCS109", 904 .probe = aqr107_probe, 905 .get_rate_matching = aqr107_get_rate_matching, 906 .config_init = aqcs109_config_init, 907 .config_aneg = aqr_config_aneg, 908 .config_intr = aqr_config_intr, 909 .handle_interrupt = aqr_handle_interrupt, 910 .read_status = aqr107_read_status, 911 .get_tunable = aqr107_get_tunable, 912 .set_tunable = aqr107_set_tunable, 913 .suspend = aqr107_suspend, 914 .resume = aqr107_resume, 915 .get_sset_count = aqr107_get_sset_count, 916 .get_strings = aqr107_get_strings, 917 .get_stats = aqr107_get_stats, 918 .get_features = aqr115c_get_features, 919 .link_change_notify = aqr107_link_change_notify, 920 .led_brightness_set = aqr_phy_led_brightness_set, 921 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 922 .led_hw_control_set = aqr_phy_led_hw_control_set, 923 .led_hw_control_get = aqr_phy_led_hw_control_get, 924 .led_polarity_set = aqr_phy_led_polarity_set, 925 }, 926 { 927 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 928 .name = "Aquantia AQR111", 929 .probe = aqr107_probe, 930 .get_rate_matching = aqr107_get_rate_matching, 931 .config_init = aqr107_config_init, 932 .config_aneg = aqr_config_aneg, 933 .config_intr = aqr_config_intr, 934 .handle_interrupt = aqr_handle_interrupt, 935 .read_status = aqr107_read_status, 936 .get_tunable = aqr107_get_tunable, 937 .set_tunable = aqr107_set_tunable, 938 .suspend = aqr107_suspend, 939 .resume = aqr107_resume, 940 .get_sset_count = aqr107_get_sset_count, 941 .get_strings = aqr107_get_strings, 942 .get_stats = aqr107_get_stats, 943 .get_features = aqr111_get_features, 944 .link_change_notify = aqr107_link_change_notify, 945 .led_brightness_set = aqr_phy_led_brightness_set, 946 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 947 .led_hw_control_set = aqr_phy_led_hw_control_set, 948 .led_hw_control_get = aqr_phy_led_hw_control_get, 949 .led_polarity_set = aqr_phy_led_polarity_set, 950 }, 951 { 952 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 953 .name = "Aquantia AQR111B0", 954 .probe = aqr107_probe, 955 .get_rate_matching = aqr107_get_rate_matching, 956 .config_init = aqr107_config_init, 957 .config_aneg = aqr_config_aneg, 958 .config_intr = aqr_config_intr, 959 .handle_interrupt = aqr_handle_interrupt, 960 .read_status = aqr107_read_status, 961 .get_tunable = aqr107_get_tunable, 962 .set_tunable = aqr107_set_tunable, 963 .suspend = aqr107_suspend, 964 .resume = aqr107_resume, 965 .get_sset_count = aqr107_get_sset_count, 966 .get_strings = aqr107_get_strings, 967 .get_stats = aqr107_get_stats, 968 .get_features = aqr111_get_features, 969 .link_change_notify = aqr107_link_change_notify, 970 .led_brightness_set = aqr_phy_led_brightness_set, 971 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 972 .led_hw_control_set = aqr_phy_led_hw_control_set, 973 .led_hw_control_get = aqr_phy_led_hw_control_get, 974 .led_polarity_set = aqr_phy_led_polarity_set, 975 }, 976 { 977 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 978 .name = "Aquantia AQR405", 979 .config_aneg = aqr_config_aneg, 980 .config_intr = aqr_config_intr, 981 .handle_interrupt = aqr_handle_interrupt, 982 .read_status = aqr_read_status, 983 }, 984 { 985 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 986 .name = "Aquantia AQR112", 987 .probe = aqr107_probe, 988 .config_aneg = aqr_config_aneg, 989 .config_intr = aqr_config_intr, 990 .handle_interrupt = aqr_handle_interrupt, 991 .get_tunable = aqr107_get_tunable, 992 .set_tunable = aqr107_set_tunable, 993 .suspend = aqr107_suspend, 994 .resume = aqr107_resume, 995 .read_status = aqr107_read_status, 996 .get_rate_matching = aqr107_get_rate_matching, 997 .get_sset_count = aqr107_get_sset_count, 998 .get_strings = aqr107_get_strings, 999 .get_stats = aqr107_get_stats, 1000 .link_change_notify = aqr107_link_change_notify, 1001 .led_brightness_set = aqr_phy_led_brightness_set, 1002 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1003 .led_hw_control_set = aqr_phy_led_hw_control_set, 1004 .led_hw_control_get = aqr_phy_led_hw_control_get, 1005 .led_polarity_set = aqr_phy_led_polarity_set, 1006 }, 1007 { 1008 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 1009 .name = "Aquantia AQR412", 1010 .probe = aqr107_probe, 1011 .config_aneg = aqr_config_aneg, 1012 .config_intr = aqr_config_intr, 1013 .handle_interrupt = aqr_handle_interrupt, 1014 .get_tunable = aqr107_get_tunable, 1015 .set_tunable = aqr107_set_tunable, 1016 .suspend = aqr107_suspend, 1017 .resume = aqr107_resume, 1018 .read_status = aqr107_read_status, 1019 .get_rate_matching = aqr107_get_rate_matching, 1020 .get_sset_count = aqr107_get_sset_count, 1021 .get_strings = aqr107_get_strings, 1022 .get_stats = aqr107_get_stats, 1023 .link_change_notify = aqr107_link_change_notify, 1024 }, 1025 { 1026 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 1027 .name = "Aquantia AQR113", 1028 .probe = aqr107_probe, 1029 .get_rate_matching = aqr107_get_rate_matching, 1030 .config_init = aqr113c_config_init, 1031 .config_aneg = aqr_config_aneg, 1032 .config_intr = aqr_config_intr, 1033 .handle_interrupt = aqr_handle_interrupt, 1034 .read_status = aqr107_read_status, 1035 .get_tunable = aqr107_get_tunable, 1036 .set_tunable = aqr107_set_tunable, 1037 .suspend = aqr107_suspend, 1038 .resume = aqr107_resume, 1039 .get_sset_count = aqr107_get_sset_count, 1040 .get_strings = aqr107_get_strings, 1041 .get_stats = aqr107_get_stats, 1042 .link_change_notify = aqr107_link_change_notify, 1043 .led_brightness_set = aqr_phy_led_brightness_set, 1044 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1045 .led_hw_control_set = aqr_phy_led_hw_control_set, 1046 .led_hw_control_get = aqr_phy_led_hw_control_get, 1047 .led_polarity_set = aqr_phy_led_polarity_set, 1048 }, 1049 { 1050 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 1051 .name = "Aquantia AQR113C", 1052 .probe = aqr107_probe, 1053 .get_rate_matching = aqr107_get_rate_matching, 1054 .config_init = aqr113c_config_init, 1055 .config_aneg = aqr_config_aneg, 1056 .config_intr = aqr_config_intr, 1057 .handle_interrupt = aqr_handle_interrupt, 1058 .read_status = aqr107_read_status, 1059 .get_tunable = aqr107_get_tunable, 1060 .set_tunable = aqr107_set_tunable, 1061 .suspend = aqr107_suspend, 1062 .resume = aqr107_resume, 1063 .get_sset_count = aqr107_get_sset_count, 1064 .get_strings = aqr107_get_strings, 1065 .get_stats = aqr107_get_stats, 1066 .link_change_notify = aqr107_link_change_notify, 1067 .led_brightness_set = aqr_phy_led_brightness_set, 1068 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1069 .led_hw_control_set = aqr_phy_led_hw_control_set, 1070 .led_hw_control_get = aqr_phy_led_hw_control_get, 1071 .led_polarity_set = aqr_phy_led_polarity_set, 1072 }, 1073 { 1074 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1075 .name = "Aquantia AQR114C", 1076 .probe = aqr107_probe, 1077 .get_rate_matching = aqr107_get_rate_matching, 1078 .config_init = aqr107_config_init, 1079 .config_aneg = aqr_config_aneg, 1080 .config_intr = aqr_config_intr, 1081 .handle_interrupt = aqr_handle_interrupt, 1082 .read_status = aqr107_read_status, 1083 .get_tunable = aqr107_get_tunable, 1084 .set_tunable = aqr107_set_tunable, 1085 .suspend = aqr107_suspend, 1086 .resume = aqr107_resume, 1087 .get_sset_count = aqr107_get_sset_count, 1088 .get_strings = aqr107_get_strings, 1089 .get_stats = aqr107_get_stats, 1090 .get_features = aqr111_get_features, 1091 .link_change_notify = aqr107_link_change_notify, 1092 .led_brightness_set = aqr_phy_led_brightness_set, 1093 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1094 .led_hw_control_set = aqr_phy_led_hw_control_set, 1095 .led_hw_control_get = aqr_phy_led_hw_control_get, 1096 .led_polarity_set = aqr_phy_led_polarity_set, 1097 }, 1098 { 1099 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1100 .name = "Aquantia AQR115C", 1101 .probe = aqr107_probe, 1102 .get_rate_matching = aqr107_get_rate_matching, 1103 .config_init = aqr113c_config_init, 1104 .config_aneg = aqr_config_aneg, 1105 .config_intr = aqr_config_intr, 1106 .handle_interrupt = aqr_handle_interrupt, 1107 .read_status = aqr107_read_status, 1108 .get_tunable = aqr107_get_tunable, 1109 .set_tunable = aqr107_set_tunable, 1110 .suspend = aqr107_suspend, 1111 .resume = aqr107_resume, 1112 .get_sset_count = aqr107_get_sset_count, 1113 .get_strings = aqr107_get_strings, 1114 .get_stats = aqr107_get_stats, 1115 .get_features = aqr115c_get_features, 1116 .link_change_notify = aqr107_link_change_notify, 1117 .led_brightness_set = aqr_phy_led_brightness_set, 1118 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1119 .led_hw_control_set = aqr_phy_led_hw_control_set, 1120 .led_hw_control_get = aqr_phy_led_hw_control_get, 1121 .led_polarity_set = aqr_phy_led_polarity_set, 1122 }, 1123 { 1124 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1125 .name = "Aquantia AQR813", 1126 .probe = aqr107_probe, 1127 .get_rate_matching = aqr107_get_rate_matching, 1128 .config_init = aqr107_config_init, 1129 .config_aneg = aqr_config_aneg, 1130 .config_intr = aqr_config_intr, 1131 .handle_interrupt = aqr_handle_interrupt, 1132 .read_status = aqr107_read_status, 1133 .get_tunable = aqr107_get_tunable, 1134 .set_tunable = aqr107_set_tunable, 1135 .suspend = aqr107_suspend, 1136 .resume = aqr107_resume, 1137 .get_sset_count = aqr107_get_sset_count, 1138 .get_strings = aqr107_get_strings, 1139 .get_stats = aqr107_get_stats, 1140 .link_change_notify = aqr107_link_change_notify, 1141 .led_brightness_set = aqr_phy_led_brightness_set, 1142 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1143 .led_hw_control_set = aqr_phy_led_hw_control_set, 1144 .led_hw_control_get = aqr_phy_led_hw_control_get, 1145 .led_polarity_set = aqr_phy_led_polarity_set, 1146 }, 1147 }; 1148 1149 module_phy_driver(aqr_driver); 1150 1151 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1152 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1153 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1154 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1155 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1156 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1157 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1158 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1159 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1160 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1161 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1162 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1163 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1164 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1165 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1166 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1167 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1168 { } 1169 }; 1170 1171 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1172 1173 MODULE_DESCRIPTION("Aquantia PHY driver"); 1174 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1175 MODULE_LICENSE("GPL v2"); 1176