1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 17 #include "aquantia.h" 18 19 #define PHY_ID_AQ1202 0x03a1b445 20 #define PHY_ID_AQ2104 0x03a1b460 21 #define PHY_ID_AQR105 0x03a1b4a2 22 #define PHY_ID_AQR106 0x03a1b4d0 23 #define PHY_ID_AQR107 0x03a1b4e0 24 #define PHY_ID_AQCS109 0x03a1b5c2 25 #define PHY_ID_AQR405 0x03a1b4b0 26 #define PHY_ID_AQR111 0x03a1b610 27 #define PHY_ID_AQR111B0 0x03a1b612 28 #define PHY_ID_AQR112 0x03a1b662 29 #define PHY_ID_AQR412 0x03a1b712 30 #define PHY_ID_AQR113 0x31c31c40 31 #define PHY_ID_AQR113C 0x31c31c12 32 #define PHY_ID_AQR114C 0x31c31c22 33 #define PHY_ID_AQR115C 0x31c31c33 34 #define PHY_ID_AQR813 0x31c31cb2 35 36 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9 46 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 47 48 #define MDIO_AN_VEND_PROV 0xc400 49 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 50 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 51 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 52 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 53 #define MDIO_AN_VEND_PROV_EXC_PHYID_INFO BIT(6) 54 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 55 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 56 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 57 58 #define MDIO_AN_RESVD_VEND_PROV 0xc410 59 #define MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO 0 60 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDI 1 61 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX 2 62 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK GENMASK(1, 0) 63 64 #define MDIO_AN_TX_VEND_STATUS1 0xc800 65 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 66 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 67 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 68 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 69 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 70 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 71 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 72 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 73 74 #define MDIO_AN_RESVD_VEND_STATUS1 0xc810 75 #define MDIO_AN_RESVD_VEND_STATUS1_MDIX BIT(8) 76 77 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 78 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 79 80 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 81 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 82 83 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 84 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 85 86 #define PMAPMD_RSVD_VEND_PROV 0xe400 87 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) 88 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) 89 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) 90 91 #define MDIO_AN_RX_LP_STAT1 0xe820 92 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 93 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 94 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 95 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 96 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 97 98 #define MDIO_AN_RX_LP_STAT4 0xe823 99 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 100 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 101 102 #define MDIO_AN_RX_VEND_STAT3 0xe832 103 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 104 105 /* Sleep and timeout for checking if the Processor-Intensive 106 * MDIO operation is finished 107 */ 108 #define AQR107_OP_IN_PROG_SLEEP 1000 109 #define AQR107_OP_IN_PROG_TIMEOUT 100000 110 111 static int aqr107_get_sset_count(struct phy_device *phydev) 112 { 113 return AQR107_SGMII_STAT_SZ; 114 } 115 116 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 117 { 118 int i; 119 120 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 121 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 122 ETH_GSTRING_LEN); 123 } 124 125 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 126 { 127 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 128 int len_l = min(stat->size, 16); 129 int len_h = stat->size - len_l; 130 u64 ret; 131 int val; 132 133 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 134 if (val < 0) 135 return U64_MAX; 136 137 ret = val & GENMASK(len_l - 1, 0); 138 if (len_h) { 139 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 140 if (val < 0) 141 return U64_MAX; 142 143 ret += (val & GENMASK(len_h - 1, 0)) << 16; 144 } 145 146 return ret; 147 } 148 149 static void aqr107_get_stats(struct phy_device *phydev, 150 struct ethtool_stats *stats, u64 *data) 151 { 152 struct aqr107_priv *priv = phydev->priv; 153 u64 val; 154 int i; 155 156 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 157 val = aqr107_get_stat(phydev, i); 158 if (val == U64_MAX) 159 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 160 aqr107_hw_stats[i].name); 161 else 162 priv->sgmii_stats[i] += val; 163 164 data[i] = priv->sgmii_stats[i]; 165 } 166 } 167 168 static int aqr_set_mdix(struct phy_device *phydev, int mdix) 169 { 170 u16 val = 0; 171 172 switch (mdix) { 173 case ETH_TP_MDI: 174 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDI; 175 break; 176 case ETH_TP_MDI_X: 177 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX; 178 break; 179 case ETH_TP_MDI_AUTO: 180 case ETH_TP_MDI_INVALID: 181 default: 182 val = MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO; 183 break; 184 } 185 186 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_PROV, 187 MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val); 188 } 189 190 static int aqr_config_aneg(struct phy_device *phydev) 191 { 192 bool changed = false; 193 u16 reg; 194 int ret; 195 196 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 197 if (ret < 0) 198 return ret; 199 if (ret > 0) 200 changed = true; 201 202 if (phydev->autoneg == AUTONEG_DISABLE) 203 return genphy_c45_pma_setup_forced(phydev); 204 205 ret = genphy_c45_an_config_aneg(phydev); 206 if (ret < 0) 207 return ret; 208 if (ret > 0) 209 changed = true; 210 211 /* Clause 45 has no standardized support for 1000BaseT, therefore 212 * use vendor registers for this mode. 213 */ 214 reg = 0; 215 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 216 phydev->advertising)) 217 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 218 219 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 220 phydev->advertising)) 221 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 222 223 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 224 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 225 phydev->advertising)) 226 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 227 228 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 229 phydev->advertising)) 230 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 231 232 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 233 MDIO_AN_VEND_PROV_1000BASET_HALF | 234 MDIO_AN_VEND_PROV_1000BASET_FULL | 235 MDIO_AN_VEND_PROV_2500BASET_FULL | 236 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 237 if (ret < 0) 238 return ret; 239 if (ret > 0) 240 changed = true; 241 242 return genphy_c45_check_and_restart_aneg(phydev, changed); 243 } 244 245 static int aqr_config_intr(struct phy_device *phydev) 246 { 247 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 248 int err; 249 250 if (en) { 251 /* Clear any pending interrupts before enabling them */ 252 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 253 if (err < 0) 254 return err; 255 } 256 257 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 258 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 259 if (err < 0) 260 return err; 261 262 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 263 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 264 if (err < 0) 265 return err; 266 267 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 268 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 269 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 270 if (err < 0) 271 return err; 272 273 if (!en) { 274 /* Clear any pending interrupts after we have disabled them */ 275 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 276 if (err < 0) 277 return err; 278 } 279 280 return 0; 281 } 282 283 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 284 { 285 int irq_status; 286 287 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 288 MDIO_AN_TX_VEND_INT_STATUS2); 289 if (irq_status < 0) { 290 phy_error(phydev); 291 return IRQ_NONE; 292 } 293 294 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 295 return IRQ_NONE; 296 297 phy_trigger_machine(phydev); 298 299 return IRQ_HANDLED; 300 } 301 302 static int aqr_read_status(struct phy_device *phydev) 303 { 304 int val; 305 306 if (phydev->autoneg == AUTONEG_ENABLE) { 307 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 308 if (val < 0) 309 return val; 310 311 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 312 phydev->lp_advertising, 313 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 314 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 315 phydev->lp_advertising, 316 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 317 } 318 319 val = genphy_c45_aneg_done(phydev); 320 if (val < 0) 321 return val; 322 if (val) { 323 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_STATUS1); 324 if (val < 0) 325 return val; 326 if (val & MDIO_AN_RESVD_VEND_STATUS1_MDIX) 327 phydev->mdix = ETH_TP_MDI_X; 328 else 329 phydev->mdix = ETH_TP_MDI; 330 } else { 331 phydev->mdix = ETH_TP_MDI_INVALID; 332 } 333 334 return genphy_c45_read_status(phydev); 335 } 336 337 static int aqr105_get_features(struct phy_device *phydev) 338 { 339 int ret; 340 341 /* Normal feature discovery */ 342 ret = genphy_c45_pma_read_abilities(phydev); 343 if (ret) 344 return ret; 345 346 /* The AQR105 PHY misses to indicate the 2.5G and 5G modes, so add them 347 * here 348 */ 349 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 350 phydev->supported); 351 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 352 phydev->supported); 353 354 /* The AQR105 PHY suppports both RJ45 and SFP+ interfaces */ 355 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); 356 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 357 358 return 0; 359 } 360 361 static int aqr105_setup_forced(struct phy_device *phydev) 362 { 363 int vend = MDIO_AN_VEND_PROV_EXC_PHYID_INFO; 364 int ctrl10 = 0; 365 int adv = ADVERTISE_CSMA; 366 int ret; 367 368 switch (phydev->speed) { 369 case SPEED_100: 370 adv |= ADVERTISE_100FULL; 371 break; 372 case SPEED_1000: 373 adv |= ADVERTISE_NPAGE; 374 if (phydev->duplex == DUPLEX_FULL) 375 vend |= MDIO_AN_VEND_PROV_1000BASET_FULL; 376 else 377 vend |= MDIO_AN_VEND_PROV_1000BASET_HALF; 378 break; 379 case SPEED_2500: 380 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 381 vend |= MDIO_AN_VEND_PROV_2500BASET_FULL; 382 break; 383 case SPEED_5000: 384 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 385 vend |= MDIO_AN_VEND_PROV_5000BASET_FULL; 386 break; 387 case SPEED_10000: 388 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 389 ctrl10 |= MDIO_AN_10GBT_CTRL_ADV10G; 390 break; 391 default: 392 return -EINVAL; 393 } 394 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); 395 if (ret < 0) 396 return ret; 397 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend); 398 if (ret < 0) 399 return ret; 400 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10); 401 if (ret < 0) 402 return ret; 403 404 /* set by vendor driver, but should be on by default */ 405 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 406 MDIO_AN_CTRL1_XNP); 407 if (ret < 0) 408 return ret; 409 410 return genphy_c45_an_disable_aneg(phydev); 411 } 412 413 static int aqr105_config_aneg(struct phy_device *phydev) 414 { 415 bool changed = false; 416 u16 reg; 417 int ret; 418 419 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 420 if (ret < 0) 421 return ret; 422 if (ret > 0) 423 changed = true; 424 425 if (phydev->autoneg == AUTONEG_DISABLE) 426 return aqr105_setup_forced(phydev); 427 428 ret = genphy_c45_an_config_aneg(phydev); 429 if (ret < 0) 430 return ret; 431 if (ret > 0) 432 changed = true; 433 434 /* Clause 45 has no standardized support for 1000BaseT, therefore 435 * use vendor registers for this mode. 436 */ 437 reg = 0; 438 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 439 phydev->advertising)) 440 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 441 442 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 443 phydev->advertising)) 444 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 445 446 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 447 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 448 phydev->advertising)) 449 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 450 451 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 452 phydev->advertising)) 453 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 454 455 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 456 MDIO_AN_VEND_PROV_1000BASET_HALF | 457 MDIO_AN_VEND_PROV_1000BASET_FULL | 458 MDIO_AN_VEND_PROV_2500BASET_FULL | 459 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 460 if (ret < 0) 461 return ret; 462 if (ret > 0) 463 changed = true; 464 465 return genphy_c45_check_and_restart_aneg(phydev, changed); 466 } 467 468 static int aqr105_read_rate(struct phy_device *phydev) 469 { 470 int val; 471 472 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 473 if (val < 0) 474 return val; 475 476 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 477 phydev->duplex = DUPLEX_FULL; 478 else 479 phydev->duplex = DUPLEX_HALF; 480 481 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 482 case MDIO_AN_TX_VEND_STATUS1_10BASET: 483 phydev->speed = SPEED_10; 484 break; 485 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 486 phydev->speed = SPEED_100; 487 break; 488 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 489 phydev->speed = SPEED_1000; 490 break; 491 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 492 phydev->speed = SPEED_2500; 493 break; 494 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 495 phydev->speed = SPEED_5000; 496 break; 497 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 498 phydev->speed = SPEED_10000; 499 break; 500 default: 501 phydev->speed = SPEED_UNKNOWN; 502 } 503 504 return 0; 505 } 506 507 static int aqr105_read_status(struct phy_device *phydev) 508 { 509 int ret; 510 int val; 511 512 ret = aqr_read_status(phydev); 513 if (ret) 514 return ret; 515 516 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 517 return 0; 518 519 /* The status register is not immediately correct on line side link up. 520 * Poll periodically until it reflects the correct ON state. 521 * Only return fail for read error, timeout defaults to OFF state. 522 */ 523 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 524 MDIO_PHYXS_VEND_IF_STATUS, val, 525 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 526 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 527 AQR107_OP_IN_PROG_SLEEP, 528 AQR107_OP_IN_PROG_TIMEOUT, false); 529 if (ret && ret != -ETIMEDOUT) 530 return ret; 531 532 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 533 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 534 phydev->interface = PHY_INTERFACE_MODE_10GKR; 535 break; 536 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 537 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 538 break; 539 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 540 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 541 break; 542 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 543 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 544 break; 545 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 546 phydev->interface = PHY_INTERFACE_MODE_XAUI; 547 break; 548 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 549 phydev->interface = PHY_INTERFACE_MODE_SGMII; 550 break; 551 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 552 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 553 break; 554 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 555 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 556 break; 557 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 558 default: 559 phydev->link = false; 560 phydev->interface = PHY_INTERFACE_MODE_NA; 561 break; 562 } 563 564 /* Read rate from vendor register */ 565 return aqr105_read_rate(phydev); 566 } 567 568 static int aqr107_read_rate(struct phy_device *phydev) 569 { 570 u32 config_reg; 571 int val; 572 573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 574 if (val < 0) 575 return val; 576 577 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 578 phydev->duplex = DUPLEX_FULL; 579 else 580 phydev->duplex = DUPLEX_HALF; 581 582 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 583 case MDIO_AN_TX_VEND_STATUS1_10BASET: 584 phydev->speed = SPEED_10; 585 config_reg = VEND1_GLOBAL_CFG_10M; 586 break; 587 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 588 phydev->speed = SPEED_100; 589 config_reg = VEND1_GLOBAL_CFG_100M; 590 break; 591 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 592 phydev->speed = SPEED_1000; 593 config_reg = VEND1_GLOBAL_CFG_1G; 594 break; 595 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 596 phydev->speed = SPEED_2500; 597 config_reg = VEND1_GLOBAL_CFG_2_5G; 598 break; 599 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 600 phydev->speed = SPEED_5000; 601 config_reg = VEND1_GLOBAL_CFG_5G; 602 break; 603 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 604 phydev->speed = SPEED_10000; 605 config_reg = VEND1_GLOBAL_CFG_10G; 606 break; 607 default: 608 phydev->speed = SPEED_UNKNOWN; 609 return 0; 610 } 611 612 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 613 if (val < 0) 614 return val; 615 616 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 617 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 618 phydev->rate_matching = RATE_MATCH_PAUSE; 619 else 620 phydev->rate_matching = RATE_MATCH_NONE; 621 622 return 0; 623 } 624 625 static int aqr107_read_status(struct phy_device *phydev) 626 { 627 int val, ret; 628 629 ret = aqr_read_status(phydev); 630 if (ret) 631 return ret; 632 633 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 634 return 0; 635 636 /* The status register is not immediately correct on line side link up. 637 * Poll periodically until it reflects the correct ON state. 638 * Only return fail for read error, timeout defaults to OFF state. 639 */ 640 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 641 MDIO_PHYXS_VEND_IF_STATUS, val, 642 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 643 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 644 AQR107_OP_IN_PROG_SLEEP, 645 AQR107_OP_IN_PROG_TIMEOUT, false); 646 if (ret && ret != -ETIMEDOUT) 647 return ret; 648 649 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 650 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 651 phydev->interface = PHY_INTERFACE_MODE_10GKR; 652 break; 653 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 654 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 655 break; 656 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 657 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 658 break; 659 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 660 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 661 break; 662 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 663 phydev->interface = PHY_INTERFACE_MODE_XAUI; 664 break; 665 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 666 phydev->interface = PHY_INTERFACE_MODE_SGMII; 667 break; 668 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 669 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 670 break; 671 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 672 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 673 break; 674 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 675 default: 676 phydev->link = false; 677 phydev->interface = PHY_INTERFACE_MODE_NA; 678 break; 679 } 680 681 /* Read possibly downshifted rate from vendor register */ 682 return aqr107_read_rate(phydev); 683 } 684 685 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 686 { 687 int val, cnt, enable; 688 689 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 690 if (val < 0) 691 return val; 692 693 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 694 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 695 696 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 697 698 return 0; 699 } 700 701 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 702 { 703 int val = 0; 704 705 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 706 return -E2BIG; 707 708 if (cnt != DOWNSHIFT_DEV_DISABLE) { 709 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 710 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 711 } 712 713 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 714 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 715 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 716 } 717 718 static int aqr107_get_tunable(struct phy_device *phydev, 719 struct ethtool_tunable *tuna, void *data) 720 { 721 switch (tuna->id) { 722 case ETHTOOL_PHY_DOWNSHIFT: 723 return aqr107_get_downshift(phydev, data); 724 default: 725 return -EOPNOTSUPP; 726 } 727 } 728 729 static int aqr107_set_tunable(struct phy_device *phydev, 730 struct ethtool_tunable *tuna, const void *data) 731 { 732 switch (tuna->id) { 733 case ETHTOOL_PHY_DOWNSHIFT: 734 return aqr107_set_downshift(phydev, *(const u8 *)data); 735 default: 736 return -EOPNOTSUPP; 737 } 738 } 739 740 #define AQR_FW_WAIT_SLEEP_US 20000 741 #define AQR_FW_WAIT_TIMEOUT_US 2000000 742 743 /* If we configure settings whilst firmware is still initializing the chip, 744 * then these settings may be overwritten. Therefore make sure chip 745 * initialization has completed. Use presence of the firmware ID as 746 * indicator for initialization having completed. 747 * The chip also provides a "reset completed" bit, but it's cleared after 748 * read. Therefore function would time out if called again. 749 */ 750 int aqr_wait_reset_complete(struct phy_device *phydev) 751 { 752 int ret, val; 753 754 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 755 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 756 false, phydev, MDIO_MMD_VEND1, 757 VEND1_GLOBAL_FW_ID); 758 if (val < 0) { 759 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 760 ERR_PTR(val)); 761 return val; 762 } 763 764 return ret; 765 } 766 767 static void aqr107_chip_info(struct phy_device *phydev) 768 { 769 u8 fw_major, fw_minor, build_id, prov_id; 770 int val; 771 772 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 773 if (val < 0) 774 return; 775 776 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 777 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 778 779 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 780 if (val < 0) 781 return; 782 783 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 784 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 785 786 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 787 fw_major, fw_minor, build_id, prov_id); 788 } 789 790 static int aqr107_config_mdi(struct phy_device *phydev) 791 { 792 struct device_node *np = phydev->mdio.dev.of_node; 793 u32 mdi_conf; 794 int ret; 795 796 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); 797 798 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ 799 if (ret == -EINVAL || ret == -ENOSYS) 800 return 0; 801 802 if (ret) 803 return ret; 804 805 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) 806 return -EINVAL; 807 808 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, 809 PMAPMD_RSVD_VEND_PROV_MDI_CONF, 810 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); 811 } 812 813 static int aqr107_config_init(struct phy_device *phydev) 814 { 815 struct aqr107_priv *priv = phydev->priv; 816 u32 led_idx; 817 int ret; 818 819 /* Check that the PHY interface type is compatible */ 820 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 821 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 822 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 823 phydev->interface != PHY_INTERFACE_MODE_XGMII && 824 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 825 phydev->interface != PHY_INTERFACE_MODE_10GKR && 826 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 827 phydev->interface != PHY_INTERFACE_MODE_XAUI && 828 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 829 return -ENODEV; 830 831 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 832 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 833 834 ret = aqr_wait_reset_complete(phydev); 835 if (!ret) 836 aqr107_chip_info(phydev); 837 838 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 839 if (ret) 840 return ret; 841 842 ret = aqr107_config_mdi(phydev); 843 if (ret) 844 return ret; 845 846 /* Restore LED polarity state after reset */ 847 for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) { 848 ret = aqr_phy_led_active_low_set(phydev, led_idx, true); 849 if (ret) 850 return ret; 851 } 852 853 for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) { 854 ret = aqr_phy_led_active_low_set(phydev, led_idx, false); 855 if (ret) 856 return ret; 857 } 858 859 return 0; 860 } 861 862 static int aqcs109_config_init(struct phy_device *phydev) 863 { 864 int ret; 865 866 /* Check that the PHY interface type is compatible */ 867 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 868 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 869 return -ENODEV; 870 871 ret = aqr_wait_reset_complete(phydev); 872 if (!ret) 873 aqr107_chip_info(phydev); 874 875 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 876 } 877 878 static void aqr107_link_change_notify(struct phy_device *phydev) 879 { 880 u8 fw_major, fw_minor; 881 bool downshift, short_reach, afr; 882 int mode, val; 883 884 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 885 return; 886 887 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 888 /* call failed or link partner is no Aquantia PHY */ 889 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 890 return; 891 892 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 893 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 894 895 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 896 if (val < 0) 897 return; 898 899 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 900 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 901 902 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 903 if (val < 0) 904 return; 905 906 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 907 908 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 909 fw_major, fw_minor, 910 short_reach ? ", short reach mode" : "", 911 downshift ? ", fast-retrain downshift advertised" : "", 912 afr ? ", fast reframe advertised" : ""); 913 914 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 915 if (val < 0) 916 return; 917 918 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 919 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 920 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 921 } 922 923 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 924 { 925 int val, err; 926 927 /* The datasheet notes to wait at least 1ms after issuing a 928 * processor intensive operation before checking. 929 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 930 * because that just determines the maximum time slept, not the minimum. 931 */ 932 usleep_range(1000, 5000); 933 934 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 935 VEND1_GLOBAL_GEN_STAT2, val, 936 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 937 AQR107_OP_IN_PROG_SLEEP, 938 AQR107_OP_IN_PROG_TIMEOUT, false); 939 if (err) { 940 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 941 return err; 942 } 943 944 return 0; 945 } 946 947 static int aqr107_get_rate_matching(struct phy_device *phydev, 948 phy_interface_t iface) 949 { 950 if (iface == PHY_INTERFACE_MODE_10GBASER || 951 iface == PHY_INTERFACE_MODE_2500BASEX || 952 iface == PHY_INTERFACE_MODE_NA) 953 return RATE_MATCH_PAUSE; 954 return RATE_MATCH_NONE; 955 } 956 957 static int aqr107_suspend(struct phy_device *phydev) 958 { 959 int err; 960 961 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 962 MDIO_CTRL1_LPOWER); 963 if (err) 964 return err; 965 966 return aqr107_wait_processor_intensive_op(phydev); 967 } 968 969 static int aqr107_resume(struct phy_device *phydev) 970 { 971 int err; 972 973 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 974 MDIO_CTRL1_LPOWER); 975 if (err) 976 return err; 977 978 return aqr107_wait_processor_intensive_op(phydev); 979 } 980 981 static const u16 aqr_global_cfg_regs[] = { 982 VEND1_GLOBAL_CFG_10M, 983 VEND1_GLOBAL_CFG_100M, 984 VEND1_GLOBAL_CFG_1G, 985 VEND1_GLOBAL_CFG_2_5G, 986 VEND1_GLOBAL_CFG_5G, 987 VEND1_GLOBAL_CFG_10G 988 }; 989 990 static int aqr107_fill_interface_modes(struct phy_device *phydev) 991 { 992 unsigned long *possible = phydev->possible_interfaces; 993 unsigned int serdes_mode, rate_adapt; 994 phy_interface_t interface; 995 int i, val; 996 997 /* Walk the media-speed configuration registers to determine which 998 * host-side serdes modes may be used by the PHY depending on the 999 * negotiated media speed. 1000 */ 1001 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 1002 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1003 aqr_global_cfg_regs[i]); 1004 if (val < 0) 1005 return val; 1006 1007 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 1008 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 1009 1010 switch (serdes_mode) { 1011 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 1012 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 1013 interface = PHY_INTERFACE_MODE_USXGMII; 1014 else 1015 interface = PHY_INTERFACE_MODE_10GBASER; 1016 break; 1017 1018 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 1019 interface = PHY_INTERFACE_MODE_5GBASER; 1020 break; 1021 1022 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 1023 interface = PHY_INTERFACE_MODE_2500BASEX; 1024 break; 1025 1026 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 1027 interface = PHY_INTERFACE_MODE_SGMII; 1028 break; 1029 1030 default: 1031 phydev_warn(phydev, "unrecognised serdes mode %u\n", 1032 serdes_mode); 1033 interface = PHY_INTERFACE_MODE_NA; 1034 break; 1035 } 1036 1037 if (interface != PHY_INTERFACE_MODE_NA) 1038 __set_bit(interface, possible); 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 1045 { 1046 int val, ret; 1047 1048 /* It's been observed on some models that - when coming out of suspend 1049 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 1050 * continue on returning zeroes for some time. Let's poll the 100M 1051 * register until it returns a real value as both 113c and 115c support 1052 * this mode. 1053 */ 1054 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1055 VEND1_GLOBAL_CFG_100M, val, val != 0, 1056 1000, 100000, false); 1057 if (ret) 1058 return ret; 1059 1060 return aqr107_fill_interface_modes(phydev); 1061 } 1062 1063 static int aqr115c_get_features(struct phy_device *phydev) 1064 { 1065 unsigned long *supported = phydev->supported; 1066 1067 /* PHY supports speeds up to 2.5G with autoneg. PMA capabilities 1068 * are not useful. 1069 */ 1070 linkmode_or(supported, supported, phy_gbit_features); 1071 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported); 1072 1073 return 0; 1074 } 1075 1076 static int aqr111_get_features(struct phy_device *phydev) 1077 { 1078 /* PHY supports speeds up to 5G with autoneg. PMA capabilities 1079 * are not useful. 1080 */ 1081 aqr115c_get_features(phydev); 1082 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1083 phydev->supported); 1084 1085 return 0; 1086 } 1087 1088 static int aqr113c_config_init(struct phy_device *phydev) 1089 { 1090 int ret; 1091 1092 ret = aqr107_config_init(phydev); 1093 if (ret < 0) 1094 return ret; 1095 1096 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 1097 MDIO_PMD_TXDIS_GLOBAL); 1098 if (ret) 1099 return ret; 1100 1101 ret = aqr107_wait_processor_intensive_op(phydev); 1102 if (ret) 1103 return ret; 1104 1105 return aqr113c_fill_interface_modes(phydev); 1106 } 1107 1108 static int aqr107_probe(struct phy_device *phydev) 1109 { 1110 int ret; 1111 1112 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 1113 sizeof(struct aqr107_priv), GFP_KERNEL); 1114 if (!phydev->priv) 1115 return -ENOMEM; 1116 1117 ret = aqr_firmware_load(phydev); 1118 if (ret) 1119 return ret; 1120 1121 return aqr_hwmon_probe(phydev); 1122 } 1123 1124 1125 static struct phy_driver aqr_driver[] = { 1126 { 1127 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 1128 .name = "Aquantia AQ1202", 1129 .config_aneg = aqr_config_aneg, 1130 .config_intr = aqr_config_intr, 1131 .handle_interrupt = aqr_handle_interrupt, 1132 .read_status = aqr_read_status, 1133 }, 1134 { 1135 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 1136 .name = "Aquantia AQ2104", 1137 .config_aneg = aqr_config_aneg, 1138 .config_intr = aqr_config_intr, 1139 .handle_interrupt = aqr_handle_interrupt, 1140 .read_status = aqr_read_status, 1141 }, 1142 { 1143 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 1144 .name = "Aquantia AQR105", 1145 .get_features = aqr105_get_features, 1146 .probe = aqr107_probe, 1147 .config_init = aqr107_config_init, 1148 .config_aneg = aqr105_config_aneg, 1149 .config_intr = aqr_config_intr, 1150 .handle_interrupt = aqr_handle_interrupt, 1151 .read_status = aqr105_read_status, 1152 .suspend = aqr107_suspend, 1153 .resume = aqr107_resume, 1154 }, 1155 { 1156 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 1157 .name = "Aquantia AQR106", 1158 .config_aneg = aqr_config_aneg, 1159 .config_intr = aqr_config_intr, 1160 .handle_interrupt = aqr_handle_interrupt, 1161 .read_status = aqr_read_status, 1162 }, 1163 { 1164 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 1165 .name = "Aquantia AQR107", 1166 .probe = aqr107_probe, 1167 .get_rate_matching = aqr107_get_rate_matching, 1168 .config_init = aqr107_config_init, 1169 .config_aneg = aqr_config_aneg, 1170 .config_intr = aqr_config_intr, 1171 .handle_interrupt = aqr_handle_interrupt, 1172 .read_status = aqr107_read_status, 1173 .get_tunable = aqr107_get_tunable, 1174 .set_tunable = aqr107_set_tunable, 1175 .suspend = aqr107_suspend, 1176 .resume = aqr107_resume, 1177 .get_sset_count = aqr107_get_sset_count, 1178 .get_strings = aqr107_get_strings, 1179 .get_stats = aqr107_get_stats, 1180 .link_change_notify = aqr107_link_change_notify, 1181 .led_brightness_set = aqr_phy_led_brightness_set, 1182 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1183 .led_hw_control_set = aqr_phy_led_hw_control_set, 1184 .led_hw_control_get = aqr_phy_led_hw_control_get, 1185 .led_polarity_set = aqr_phy_led_polarity_set, 1186 }, 1187 { 1188 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 1189 .name = "Aquantia AQCS109", 1190 .probe = aqr107_probe, 1191 .get_rate_matching = aqr107_get_rate_matching, 1192 .config_init = aqcs109_config_init, 1193 .config_aneg = aqr_config_aneg, 1194 .config_intr = aqr_config_intr, 1195 .handle_interrupt = aqr_handle_interrupt, 1196 .read_status = aqr107_read_status, 1197 .get_tunable = aqr107_get_tunable, 1198 .set_tunable = aqr107_set_tunable, 1199 .suspend = aqr107_suspend, 1200 .resume = aqr107_resume, 1201 .get_sset_count = aqr107_get_sset_count, 1202 .get_strings = aqr107_get_strings, 1203 .get_stats = aqr107_get_stats, 1204 .get_features = aqr115c_get_features, 1205 .link_change_notify = aqr107_link_change_notify, 1206 .led_brightness_set = aqr_phy_led_brightness_set, 1207 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1208 .led_hw_control_set = aqr_phy_led_hw_control_set, 1209 .led_hw_control_get = aqr_phy_led_hw_control_get, 1210 .led_polarity_set = aqr_phy_led_polarity_set, 1211 }, 1212 { 1213 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 1214 .name = "Aquantia AQR111", 1215 .probe = aqr107_probe, 1216 .get_rate_matching = aqr107_get_rate_matching, 1217 .config_init = aqr107_config_init, 1218 .config_aneg = aqr_config_aneg, 1219 .config_intr = aqr_config_intr, 1220 .handle_interrupt = aqr_handle_interrupt, 1221 .read_status = aqr107_read_status, 1222 .get_tunable = aqr107_get_tunable, 1223 .set_tunable = aqr107_set_tunable, 1224 .suspend = aqr107_suspend, 1225 .resume = aqr107_resume, 1226 .get_sset_count = aqr107_get_sset_count, 1227 .get_strings = aqr107_get_strings, 1228 .get_stats = aqr107_get_stats, 1229 .get_features = aqr111_get_features, 1230 .link_change_notify = aqr107_link_change_notify, 1231 .led_brightness_set = aqr_phy_led_brightness_set, 1232 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1233 .led_hw_control_set = aqr_phy_led_hw_control_set, 1234 .led_hw_control_get = aqr_phy_led_hw_control_get, 1235 .led_polarity_set = aqr_phy_led_polarity_set, 1236 }, 1237 { 1238 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 1239 .name = "Aquantia AQR111B0", 1240 .probe = aqr107_probe, 1241 .get_rate_matching = aqr107_get_rate_matching, 1242 .config_init = aqr107_config_init, 1243 .config_aneg = aqr_config_aneg, 1244 .config_intr = aqr_config_intr, 1245 .handle_interrupt = aqr_handle_interrupt, 1246 .read_status = aqr107_read_status, 1247 .get_tunable = aqr107_get_tunable, 1248 .set_tunable = aqr107_set_tunable, 1249 .suspend = aqr107_suspend, 1250 .resume = aqr107_resume, 1251 .get_sset_count = aqr107_get_sset_count, 1252 .get_strings = aqr107_get_strings, 1253 .get_stats = aqr107_get_stats, 1254 .get_features = aqr111_get_features, 1255 .link_change_notify = aqr107_link_change_notify, 1256 .led_brightness_set = aqr_phy_led_brightness_set, 1257 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1258 .led_hw_control_set = aqr_phy_led_hw_control_set, 1259 .led_hw_control_get = aqr_phy_led_hw_control_get, 1260 .led_polarity_set = aqr_phy_led_polarity_set, 1261 }, 1262 { 1263 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 1264 .name = "Aquantia AQR405", 1265 .config_aneg = aqr_config_aneg, 1266 .config_intr = aqr_config_intr, 1267 .handle_interrupt = aqr_handle_interrupt, 1268 .read_status = aqr_read_status, 1269 }, 1270 { 1271 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 1272 .name = "Aquantia AQR112", 1273 .probe = aqr107_probe, 1274 .config_aneg = aqr_config_aneg, 1275 .config_intr = aqr_config_intr, 1276 .handle_interrupt = aqr_handle_interrupt, 1277 .get_tunable = aqr107_get_tunable, 1278 .set_tunable = aqr107_set_tunable, 1279 .suspend = aqr107_suspend, 1280 .resume = aqr107_resume, 1281 .read_status = aqr107_read_status, 1282 .get_rate_matching = aqr107_get_rate_matching, 1283 .get_sset_count = aqr107_get_sset_count, 1284 .get_strings = aqr107_get_strings, 1285 .get_stats = aqr107_get_stats, 1286 .link_change_notify = aqr107_link_change_notify, 1287 .led_brightness_set = aqr_phy_led_brightness_set, 1288 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1289 .led_hw_control_set = aqr_phy_led_hw_control_set, 1290 .led_hw_control_get = aqr_phy_led_hw_control_get, 1291 .led_polarity_set = aqr_phy_led_polarity_set, 1292 }, 1293 { 1294 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 1295 .name = "Aquantia AQR412", 1296 .probe = aqr107_probe, 1297 .config_aneg = aqr_config_aneg, 1298 .config_intr = aqr_config_intr, 1299 .handle_interrupt = aqr_handle_interrupt, 1300 .get_tunable = aqr107_get_tunable, 1301 .set_tunable = aqr107_set_tunable, 1302 .suspend = aqr107_suspend, 1303 .resume = aqr107_resume, 1304 .read_status = aqr107_read_status, 1305 .get_rate_matching = aqr107_get_rate_matching, 1306 .get_sset_count = aqr107_get_sset_count, 1307 .get_strings = aqr107_get_strings, 1308 .get_stats = aqr107_get_stats, 1309 .link_change_notify = aqr107_link_change_notify, 1310 }, 1311 { 1312 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 1313 .name = "Aquantia AQR113", 1314 .probe = aqr107_probe, 1315 .get_rate_matching = aqr107_get_rate_matching, 1316 .config_init = aqr113c_config_init, 1317 .config_aneg = aqr_config_aneg, 1318 .config_intr = aqr_config_intr, 1319 .handle_interrupt = aqr_handle_interrupt, 1320 .read_status = aqr107_read_status, 1321 .get_tunable = aqr107_get_tunable, 1322 .set_tunable = aqr107_set_tunable, 1323 .suspend = aqr107_suspend, 1324 .resume = aqr107_resume, 1325 .get_sset_count = aqr107_get_sset_count, 1326 .get_strings = aqr107_get_strings, 1327 .get_stats = aqr107_get_stats, 1328 .link_change_notify = aqr107_link_change_notify, 1329 .led_brightness_set = aqr_phy_led_brightness_set, 1330 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1331 .led_hw_control_set = aqr_phy_led_hw_control_set, 1332 .led_hw_control_get = aqr_phy_led_hw_control_get, 1333 .led_polarity_set = aqr_phy_led_polarity_set, 1334 }, 1335 { 1336 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 1337 .name = "Aquantia AQR113C", 1338 .probe = aqr107_probe, 1339 .get_rate_matching = aqr107_get_rate_matching, 1340 .config_init = aqr113c_config_init, 1341 .config_aneg = aqr_config_aneg, 1342 .config_intr = aqr_config_intr, 1343 .handle_interrupt = aqr_handle_interrupt, 1344 .read_status = aqr107_read_status, 1345 .get_tunable = aqr107_get_tunable, 1346 .set_tunable = aqr107_set_tunable, 1347 .suspend = aqr107_suspend, 1348 .resume = aqr107_resume, 1349 .get_sset_count = aqr107_get_sset_count, 1350 .get_strings = aqr107_get_strings, 1351 .get_stats = aqr107_get_stats, 1352 .link_change_notify = aqr107_link_change_notify, 1353 .led_brightness_set = aqr_phy_led_brightness_set, 1354 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1355 .led_hw_control_set = aqr_phy_led_hw_control_set, 1356 .led_hw_control_get = aqr_phy_led_hw_control_get, 1357 .led_polarity_set = aqr_phy_led_polarity_set, 1358 }, 1359 { 1360 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1361 .name = "Aquantia AQR114C", 1362 .probe = aqr107_probe, 1363 .get_rate_matching = aqr107_get_rate_matching, 1364 .config_init = aqr107_config_init, 1365 .config_aneg = aqr_config_aneg, 1366 .config_intr = aqr_config_intr, 1367 .handle_interrupt = aqr_handle_interrupt, 1368 .read_status = aqr107_read_status, 1369 .get_tunable = aqr107_get_tunable, 1370 .set_tunable = aqr107_set_tunable, 1371 .suspend = aqr107_suspend, 1372 .resume = aqr107_resume, 1373 .get_sset_count = aqr107_get_sset_count, 1374 .get_strings = aqr107_get_strings, 1375 .get_stats = aqr107_get_stats, 1376 .get_features = aqr111_get_features, 1377 .link_change_notify = aqr107_link_change_notify, 1378 .led_brightness_set = aqr_phy_led_brightness_set, 1379 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1380 .led_hw_control_set = aqr_phy_led_hw_control_set, 1381 .led_hw_control_get = aqr_phy_led_hw_control_get, 1382 .led_polarity_set = aqr_phy_led_polarity_set, 1383 }, 1384 { 1385 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1386 .name = "Aquantia AQR115C", 1387 .probe = aqr107_probe, 1388 .get_rate_matching = aqr107_get_rate_matching, 1389 .config_init = aqr113c_config_init, 1390 .config_aneg = aqr_config_aneg, 1391 .config_intr = aqr_config_intr, 1392 .handle_interrupt = aqr_handle_interrupt, 1393 .read_status = aqr107_read_status, 1394 .get_tunable = aqr107_get_tunable, 1395 .set_tunable = aqr107_set_tunable, 1396 .suspend = aqr107_suspend, 1397 .resume = aqr107_resume, 1398 .get_sset_count = aqr107_get_sset_count, 1399 .get_strings = aqr107_get_strings, 1400 .get_stats = aqr107_get_stats, 1401 .get_features = aqr115c_get_features, 1402 .link_change_notify = aqr107_link_change_notify, 1403 .led_brightness_set = aqr_phy_led_brightness_set, 1404 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1405 .led_hw_control_set = aqr_phy_led_hw_control_set, 1406 .led_hw_control_get = aqr_phy_led_hw_control_get, 1407 .led_polarity_set = aqr_phy_led_polarity_set, 1408 }, 1409 { 1410 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1411 .name = "Aquantia AQR813", 1412 .probe = aqr107_probe, 1413 .get_rate_matching = aqr107_get_rate_matching, 1414 .config_init = aqr107_config_init, 1415 .config_aneg = aqr_config_aneg, 1416 .config_intr = aqr_config_intr, 1417 .handle_interrupt = aqr_handle_interrupt, 1418 .read_status = aqr107_read_status, 1419 .get_tunable = aqr107_get_tunable, 1420 .set_tunable = aqr107_set_tunable, 1421 .suspend = aqr107_suspend, 1422 .resume = aqr107_resume, 1423 .get_sset_count = aqr107_get_sset_count, 1424 .get_strings = aqr107_get_strings, 1425 .get_stats = aqr107_get_stats, 1426 .link_change_notify = aqr107_link_change_notify, 1427 .led_brightness_set = aqr_phy_led_brightness_set, 1428 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1429 .led_hw_control_set = aqr_phy_led_hw_control_set, 1430 .led_hw_control_get = aqr_phy_led_hw_control_get, 1431 .led_polarity_set = aqr_phy_led_polarity_set, 1432 }, 1433 }; 1434 1435 module_phy_driver(aqr_driver); 1436 1437 static const struct mdio_device_id __maybe_unused aqr_tbl[] = { 1438 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1439 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1440 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1441 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1442 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1443 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1444 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1445 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1446 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1447 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1448 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1449 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1450 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1451 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1452 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1453 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1454 { } 1455 }; 1456 1457 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1458 1459 MODULE_DESCRIPTION("Aquantia PHY driver"); 1460 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1461 MODULE_LICENSE("GPL v2"); 1462