1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR111 0x03a1b610 26 #define PHY_ID_AQR111B0 0x03a1b612 27 #define PHY_ID_AQR112 0x03a1b662 28 #define PHY_ID_AQR412 0x03a1b712 29 #define PHY_ID_AQR113 0x31c31c40 30 #define PHY_ID_AQR113C 0x31c31c12 31 #define PHY_ID_AQR114C 0x31c31c22 32 #define PHY_ID_AQR115C 0x31c31c33 33 #define PHY_ID_AQR813 0x31c31cb2 34 35 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 45 46 #define MDIO_AN_VEND_PROV 0xc400 47 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 48 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 49 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 50 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 51 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 52 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 53 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 54 55 #define MDIO_AN_TX_VEND_STATUS1 0xc800 56 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 57 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 58 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 59 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 60 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 61 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 62 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 63 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 64 65 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 66 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 67 68 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 69 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 70 71 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 72 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 73 74 #define MDIO_AN_RX_LP_STAT1 0xe820 75 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 76 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 77 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 78 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 79 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 80 81 #define MDIO_AN_RX_LP_STAT4 0xe823 82 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 83 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 84 85 #define MDIO_AN_RX_VEND_STAT3 0xe832 86 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 87 88 /* Sleep and timeout for checking if the Processor-Intensive 89 * MDIO operation is finished 90 */ 91 #define AQR107_OP_IN_PROG_SLEEP 1000 92 #define AQR107_OP_IN_PROG_TIMEOUT 100000 93 94 static int aqr107_get_sset_count(struct phy_device *phydev) 95 { 96 return AQR107_SGMII_STAT_SZ; 97 } 98 99 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 100 { 101 int i; 102 103 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 104 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 105 ETH_GSTRING_LEN); 106 } 107 108 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 109 { 110 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 111 int len_l = min(stat->size, 16); 112 int len_h = stat->size - len_l; 113 u64 ret; 114 int val; 115 116 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 117 if (val < 0) 118 return U64_MAX; 119 120 ret = val & GENMASK(len_l - 1, 0); 121 if (len_h) { 122 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 123 if (val < 0) 124 return U64_MAX; 125 126 ret += (val & GENMASK(len_h - 1, 0)) << 16; 127 } 128 129 return ret; 130 } 131 132 static void aqr107_get_stats(struct phy_device *phydev, 133 struct ethtool_stats *stats, u64 *data) 134 { 135 struct aqr107_priv *priv = phydev->priv; 136 u64 val; 137 int i; 138 139 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 140 val = aqr107_get_stat(phydev, i); 141 if (val == U64_MAX) 142 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 143 aqr107_hw_stats[i].name); 144 else 145 priv->sgmii_stats[i] += val; 146 147 data[i] = priv->sgmii_stats[i]; 148 } 149 } 150 151 static int aqr_config_aneg(struct phy_device *phydev) 152 { 153 bool changed = false; 154 u16 reg; 155 int ret; 156 157 if (phydev->autoneg == AUTONEG_DISABLE) 158 return genphy_c45_pma_setup_forced(phydev); 159 160 ret = genphy_c45_an_config_aneg(phydev); 161 if (ret < 0) 162 return ret; 163 if (ret > 0) 164 changed = true; 165 166 /* Clause 45 has no standardized support for 1000BaseT, therefore 167 * use vendor registers for this mode. 168 */ 169 reg = 0; 170 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 171 phydev->advertising)) 172 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 173 174 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 175 phydev->advertising)) 176 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 177 178 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 179 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 180 phydev->advertising)) 181 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 182 183 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 184 phydev->advertising)) 185 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 186 187 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 188 MDIO_AN_VEND_PROV_1000BASET_HALF | 189 MDIO_AN_VEND_PROV_1000BASET_FULL | 190 MDIO_AN_VEND_PROV_2500BASET_FULL | 191 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 192 if (ret < 0) 193 return ret; 194 if (ret > 0) 195 changed = true; 196 197 return genphy_c45_check_and_restart_aneg(phydev, changed); 198 } 199 200 static int aqr_config_intr(struct phy_device *phydev) 201 { 202 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 203 int err; 204 205 if (en) { 206 /* Clear any pending interrupts before enabling them */ 207 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 208 if (err < 0) 209 return err; 210 } 211 212 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 213 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 214 if (err < 0) 215 return err; 216 217 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 218 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 219 if (err < 0) 220 return err; 221 222 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 223 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 224 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 225 if (err < 0) 226 return err; 227 228 if (!en) { 229 /* Clear any pending interrupts after we have disabled them */ 230 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 231 if (err < 0) 232 return err; 233 } 234 235 return 0; 236 } 237 238 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 239 { 240 int irq_status; 241 242 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 243 MDIO_AN_TX_VEND_INT_STATUS2); 244 if (irq_status < 0) { 245 phy_error(phydev); 246 return IRQ_NONE; 247 } 248 249 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 250 return IRQ_NONE; 251 252 phy_trigger_machine(phydev); 253 254 return IRQ_HANDLED; 255 } 256 257 static int aqr_read_status(struct phy_device *phydev) 258 { 259 int val; 260 261 if (phydev->autoneg == AUTONEG_ENABLE) { 262 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 263 if (val < 0) 264 return val; 265 266 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 267 phydev->lp_advertising, 268 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 269 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 270 phydev->lp_advertising, 271 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 272 } 273 274 return genphy_c45_read_status(phydev); 275 } 276 277 static int aqr107_read_rate(struct phy_device *phydev) 278 { 279 u32 config_reg; 280 int val; 281 282 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 283 if (val < 0) 284 return val; 285 286 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 287 phydev->duplex = DUPLEX_FULL; 288 else 289 phydev->duplex = DUPLEX_HALF; 290 291 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 292 case MDIO_AN_TX_VEND_STATUS1_10BASET: 293 phydev->speed = SPEED_10; 294 config_reg = VEND1_GLOBAL_CFG_10M; 295 break; 296 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 297 phydev->speed = SPEED_100; 298 config_reg = VEND1_GLOBAL_CFG_100M; 299 break; 300 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 301 phydev->speed = SPEED_1000; 302 config_reg = VEND1_GLOBAL_CFG_1G; 303 break; 304 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 305 phydev->speed = SPEED_2500; 306 config_reg = VEND1_GLOBAL_CFG_2_5G; 307 break; 308 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 309 phydev->speed = SPEED_5000; 310 config_reg = VEND1_GLOBAL_CFG_5G; 311 break; 312 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 313 phydev->speed = SPEED_10000; 314 config_reg = VEND1_GLOBAL_CFG_10G; 315 break; 316 default: 317 phydev->speed = SPEED_UNKNOWN; 318 return 0; 319 } 320 321 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 322 if (val < 0) 323 return val; 324 325 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 326 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 327 phydev->rate_matching = RATE_MATCH_PAUSE; 328 else 329 phydev->rate_matching = RATE_MATCH_NONE; 330 331 return 0; 332 } 333 334 static int aqr107_read_status(struct phy_device *phydev) 335 { 336 int val, ret; 337 338 ret = aqr_read_status(phydev); 339 if (ret) 340 return ret; 341 342 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 343 return 0; 344 345 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 346 if (val < 0) 347 return val; 348 349 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 350 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 351 phydev->interface = PHY_INTERFACE_MODE_10GKR; 352 break; 353 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 354 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 355 break; 356 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 357 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 358 break; 359 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 360 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 361 break; 362 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 363 phydev->interface = PHY_INTERFACE_MODE_XAUI; 364 break; 365 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 366 phydev->interface = PHY_INTERFACE_MODE_SGMII; 367 break; 368 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 369 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 370 break; 371 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 372 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 373 break; 374 default: 375 phydev->interface = PHY_INTERFACE_MODE_NA; 376 break; 377 } 378 379 /* Read possibly downshifted rate from vendor register */ 380 return aqr107_read_rate(phydev); 381 } 382 383 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 384 { 385 int val, cnt, enable; 386 387 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 388 if (val < 0) 389 return val; 390 391 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 392 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 393 394 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 395 396 return 0; 397 } 398 399 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 400 { 401 int val = 0; 402 403 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 404 return -E2BIG; 405 406 if (cnt != DOWNSHIFT_DEV_DISABLE) { 407 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 408 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 409 } 410 411 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 412 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 413 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 414 } 415 416 static int aqr107_get_tunable(struct phy_device *phydev, 417 struct ethtool_tunable *tuna, void *data) 418 { 419 switch (tuna->id) { 420 case ETHTOOL_PHY_DOWNSHIFT: 421 return aqr107_get_downshift(phydev, data); 422 default: 423 return -EOPNOTSUPP; 424 } 425 } 426 427 static int aqr107_set_tunable(struct phy_device *phydev, 428 struct ethtool_tunable *tuna, const void *data) 429 { 430 switch (tuna->id) { 431 case ETHTOOL_PHY_DOWNSHIFT: 432 return aqr107_set_downshift(phydev, *(const u8 *)data); 433 default: 434 return -EOPNOTSUPP; 435 } 436 } 437 438 #define AQR_FW_WAIT_SLEEP_US 20000 439 #define AQR_FW_WAIT_TIMEOUT_US 2000000 440 441 /* If we configure settings whilst firmware is still initializing the chip, 442 * then these settings may be overwritten. Therefore make sure chip 443 * initialization has completed. Use presence of the firmware ID as 444 * indicator for initialization having completed. 445 * The chip also provides a "reset completed" bit, but it's cleared after 446 * read. Therefore function would time out if called again. 447 */ 448 int aqr_wait_reset_complete(struct phy_device *phydev) 449 { 450 int ret, val; 451 452 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 453 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 454 false, phydev, MDIO_MMD_VEND1, 455 VEND1_GLOBAL_FW_ID); 456 if (val < 0) { 457 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 458 ERR_PTR(val)); 459 return val; 460 } 461 462 return ret; 463 } 464 465 static void aqr107_chip_info(struct phy_device *phydev) 466 { 467 u8 fw_major, fw_minor, build_id, prov_id; 468 int val; 469 470 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 471 if (val < 0) 472 return; 473 474 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 475 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 476 477 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 478 if (val < 0) 479 return; 480 481 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 482 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 483 484 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 485 fw_major, fw_minor, build_id, prov_id); 486 } 487 488 static int aqr107_config_init(struct phy_device *phydev) 489 { 490 struct aqr107_priv *priv = phydev->priv; 491 u32 led_active_low; 492 int ret; 493 494 /* Check that the PHY interface type is compatible */ 495 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 496 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 497 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 498 phydev->interface != PHY_INTERFACE_MODE_XGMII && 499 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 500 phydev->interface != PHY_INTERFACE_MODE_10GKR && 501 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 502 phydev->interface != PHY_INTERFACE_MODE_XAUI && 503 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 504 return -ENODEV; 505 506 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 507 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 508 509 ret = aqr_wait_reset_complete(phydev); 510 if (!ret) 511 aqr107_chip_info(phydev); 512 513 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 514 if (ret) 515 return ret; 516 517 /* Restore LED polarity state after reset */ 518 for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { 519 ret = aqr_phy_led_active_low_set(phydev, led_active_low, true); 520 if (ret) 521 return ret; 522 } 523 524 return 0; 525 } 526 527 static int aqcs109_config_init(struct phy_device *phydev) 528 { 529 int ret; 530 531 /* Check that the PHY interface type is compatible */ 532 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 533 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 534 return -ENODEV; 535 536 ret = aqr_wait_reset_complete(phydev); 537 if (!ret) 538 aqr107_chip_info(phydev); 539 540 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 541 * PMA speed ability bits are the same for all members of the family, 542 * AQCS109 however supports speeds up to 2.5G only. 543 */ 544 phy_set_max_speed(phydev, SPEED_2500); 545 546 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 547 } 548 549 static void aqr107_link_change_notify(struct phy_device *phydev) 550 { 551 u8 fw_major, fw_minor; 552 bool downshift, short_reach, afr; 553 int mode, val; 554 555 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 556 return; 557 558 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 559 /* call failed or link partner is no Aquantia PHY */ 560 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 561 return; 562 563 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 564 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 565 566 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 567 if (val < 0) 568 return; 569 570 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 571 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 572 573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 574 if (val < 0) 575 return; 576 577 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 578 579 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 580 fw_major, fw_minor, 581 short_reach ? ", short reach mode" : "", 582 downshift ? ", fast-retrain downshift advertised" : "", 583 afr ? ", fast reframe advertised" : ""); 584 585 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 586 if (val < 0) 587 return; 588 589 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 590 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 591 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 592 } 593 594 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 595 { 596 int val, err; 597 598 /* The datasheet notes to wait at least 1ms after issuing a 599 * processor intensive operation before checking. 600 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 601 * because that just determines the maximum time slept, not the minimum. 602 */ 603 usleep_range(1000, 5000); 604 605 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 606 VEND1_GLOBAL_GEN_STAT2, val, 607 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 608 AQR107_OP_IN_PROG_SLEEP, 609 AQR107_OP_IN_PROG_TIMEOUT, false); 610 if (err) { 611 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 612 return err; 613 } 614 615 return 0; 616 } 617 618 static int aqr107_get_rate_matching(struct phy_device *phydev, 619 phy_interface_t iface) 620 { 621 if (iface == PHY_INTERFACE_MODE_10GBASER || 622 iface == PHY_INTERFACE_MODE_2500BASEX || 623 iface == PHY_INTERFACE_MODE_NA) 624 return RATE_MATCH_PAUSE; 625 return RATE_MATCH_NONE; 626 } 627 628 static int aqr107_suspend(struct phy_device *phydev) 629 { 630 int err; 631 632 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 633 MDIO_CTRL1_LPOWER); 634 if (err) 635 return err; 636 637 return aqr107_wait_processor_intensive_op(phydev); 638 } 639 640 static int aqr107_resume(struct phy_device *phydev) 641 { 642 int err; 643 644 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 645 MDIO_CTRL1_LPOWER); 646 if (err) 647 return err; 648 649 return aqr107_wait_processor_intensive_op(phydev); 650 } 651 652 static const u16 aqr_global_cfg_regs[] = { 653 VEND1_GLOBAL_CFG_10M, 654 VEND1_GLOBAL_CFG_100M, 655 VEND1_GLOBAL_CFG_1G, 656 VEND1_GLOBAL_CFG_2_5G, 657 VEND1_GLOBAL_CFG_5G, 658 VEND1_GLOBAL_CFG_10G 659 }; 660 661 static int aqr107_fill_interface_modes(struct phy_device *phydev) 662 { 663 unsigned long *possible = phydev->possible_interfaces; 664 unsigned int serdes_mode, rate_adapt; 665 phy_interface_t interface; 666 int i, val; 667 668 /* Walk the media-speed configuration registers to determine which 669 * host-side serdes modes may be used by the PHY depending on the 670 * negotiated media speed. 671 */ 672 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 673 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 674 aqr_global_cfg_regs[i]); 675 if (val < 0) 676 return val; 677 678 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 679 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 680 681 switch (serdes_mode) { 682 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 683 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 684 interface = PHY_INTERFACE_MODE_USXGMII; 685 else 686 interface = PHY_INTERFACE_MODE_10GBASER; 687 break; 688 689 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 690 interface = PHY_INTERFACE_MODE_5GBASER; 691 break; 692 693 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 694 interface = PHY_INTERFACE_MODE_2500BASEX; 695 break; 696 697 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 698 interface = PHY_INTERFACE_MODE_SGMII; 699 break; 700 701 default: 702 phydev_warn(phydev, "unrecognised serdes mode %u\n", 703 serdes_mode); 704 interface = PHY_INTERFACE_MODE_NA; 705 break; 706 } 707 708 if (interface != PHY_INTERFACE_MODE_NA) 709 __set_bit(interface, possible); 710 } 711 712 return 0; 713 } 714 715 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 716 { 717 int val, ret; 718 719 /* It's been observed on some models that - when coming out of suspend 720 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 721 * continue on returning zeroes for some time. Let's poll the 100M 722 * register until it returns a real value as both 113c and 115c support 723 * this mode. 724 */ 725 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 726 VEND1_GLOBAL_CFG_100M, val, val != 0, 727 1000, 100000, false); 728 if (ret) 729 return ret; 730 731 return aqr107_fill_interface_modes(phydev); 732 } 733 734 static int aqr113c_config_init(struct phy_device *phydev) 735 { 736 int ret; 737 738 ret = aqr107_config_init(phydev); 739 if (ret < 0) 740 return ret; 741 742 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 743 MDIO_PMD_TXDIS_GLOBAL); 744 if (ret) 745 return ret; 746 747 ret = aqr107_wait_processor_intensive_op(phydev); 748 if (ret) 749 return ret; 750 751 return aqr113c_fill_interface_modes(phydev); 752 } 753 754 static int aqr107_probe(struct phy_device *phydev) 755 { 756 int ret; 757 758 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 759 sizeof(struct aqr107_priv), GFP_KERNEL); 760 if (!phydev->priv) 761 return -ENOMEM; 762 763 ret = aqr_firmware_load(phydev); 764 if (ret) 765 return ret; 766 767 return aqr_hwmon_probe(phydev); 768 } 769 770 static int aqr111_config_init(struct phy_device *phydev) 771 { 772 /* AQR111 reports supporting speed up to 10G, 773 * however only speeds up to 5G are supported. 774 */ 775 phy_set_max_speed(phydev, SPEED_5000); 776 777 return aqr107_config_init(phydev); 778 } 779 780 static struct phy_driver aqr_driver[] = { 781 { 782 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 783 .name = "Aquantia AQ1202", 784 .config_aneg = aqr_config_aneg, 785 .config_intr = aqr_config_intr, 786 .handle_interrupt = aqr_handle_interrupt, 787 .read_status = aqr_read_status, 788 }, 789 { 790 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 791 .name = "Aquantia AQ2104", 792 .config_aneg = aqr_config_aneg, 793 .config_intr = aqr_config_intr, 794 .handle_interrupt = aqr_handle_interrupt, 795 .read_status = aqr_read_status, 796 }, 797 { 798 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 799 .name = "Aquantia AQR105", 800 .config_aneg = aqr_config_aneg, 801 .config_intr = aqr_config_intr, 802 .handle_interrupt = aqr_handle_interrupt, 803 .read_status = aqr_read_status, 804 .suspend = aqr107_suspend, 805 .resume = aqr107_resume, 806 }, 807 { 808 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 809 .name = "Aquantia AQR106", 810 .config_aneg = aqr_config_aneg, 811 .config_intr = aqr_config_intr, 812 .handle_interrupt = aqr_handle_interrupt, 813 .read_status = aqr_read_status, 814 }, 815 { 816 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 817 .name = "Aquantia AQR107", 818 .probe = aqr107_probe, 819 .get_rate_matching = aqr107_get_rate_matching, 820 .config_init = aqr107_config_init, 821 .config_aneg = aqr_config_aneg, 822 .config_intr = aqr_config_intr, 823 .handle_interrupt = aqr_handle_interrupt, 824 .read_status = aqr107_read_status, 825 .get_tunable = aqr107_get_tunable, 826 .set_tunable = aqr107_set_tunable, 827 .suspend = aqr107_suspend, 828 .resume = aqr107_resume, 829 .get_sset_count = aqr107_get_sset_count, 830 .get_strings = aqr107_get_strings, 831 .get_stats = aqr107_get_stats, 832 .link_change_notify = aqr107_link_change_notify, 833 .led_brightness_set = aqr_phy_led_brightness_set, 834 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 835 .led_hw_control_set = aqr_phy_led_hw_control_set, 836 .led_hw_control_get = aqr_phy_led_hw_control_get, 837 .led_polarity_set = aqr_phy_led_polarity_set, 838 }, 839 { 840 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 841 .name = "Aquantia AQCS109", 842 .probe = aqr107_probe, 843 .get_rate_matching = aqr107_get_rate_matching, 844 .config_init = aqcs109_config_init, 845 .config_aneg = aqr_config_aneg, 846 .config_intr = aqr_config_intr, 847 .handle_interrupt = aqr_handle_interrupt, 848 .read_status = aqr107_read_status, 849 .get_tunable = aqr107_get_tunable, 850 .set_tunable = aqr107_set_tunable, 851 .suspend = aqr107_suspend, 852 .resume = aqr107_resume, 853 .get_sset_count = aqr107_get_sset_count, 854 .get_strings = aqr107_get_strings, 855 .get_stats = aqr107_get_stats, 856 .link_change_notify = aqr107_link_change_notify, 857 .led_brightness_set = aqr_phy_led_brightness_set, 858 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 859 .led_hw_control_set = aqr_phy_led_hw_control_set, 860 .led_hw_control_get = aqr_phy_led_hw_control_get, 861 .led_polarity_set = aqr_phy_led_polarity_set, 862 }, 863 { 864 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 865 .name = "Aquantia AQR111", 866 .probe = aqr107_probe, 867 .get_rate_matching = aqr107_get_rate_matching, 868 .config_init = aqr111_config_init, 869 .config_aneg = aqr_config_aneg, 870 .config_intr = aqr_config_intr, 871 .handle_interrupt = aqr_handle_interrupt, 872 .read_status = aqr107_read_status, 873 .get_tunable = aqr107_get_tunable, 874 .set_tunable = aqr107_set_tunable, 875 .suspend = aqr107_suspend, 876 .resume = aqr107_resume, 877 .get_sset_count = aqr107_get_sset_count, 878 .get_strings = aqr107_get_strings, 879 .get_stats = aqr107_get_stats, 880 .link_change_notify = aqr107_link_change_notify, 881 .led_brightness_set = aqr_phy_led_brightness_set, 882 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 883 .led_hw_control_set = aqr_phy_led_hw_control_set, 884 .led_hw_control_get = aqr_phy_led_hw_control_get, 885 .led_polarity_set = aqr_phy_led_polarity_set, 886 }, 887 { 888 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 889 .name = "Aquantia AQR111B0", 890 .probe = aqr107_probe, 891 .get_rate_matching = aqr107_get_rate_matching, 892 .config_init = aqr111_config_init, 893 .config_aneg = aqr_config_aneg, 894 .config_intr = aqr_config_intr, 895 .handle_interrupt = aqr_handle_interrupt, 896 .read_status = aqr107_read_status, 897 .get_tunable = aqr107_get_tunable, 898 .set_tunable = aqr107_set_tunable, 899 .suspend = aqr107_suspend, 900 .resume = aqr107_resume, 901 .get_sset_count = aqr107_get_sset_count, 902 .get_strings = aqr107_get_strings, 903 .get_stats = aqr107_get_stats, 904 .link_change_notify = aqr107_link_change_notify, 905 .led_brightness_set = aqr_phy_led_brightness_set, 906 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 907 .led_hw_control_set = aqr_phy_led_hw_control_set, 908 .led_hw_control_get = aqr_phy_led_hw_control_get, 909 .led_polarity_set = aqr_phy_led_polarity_set, 910 }, 911 { 912 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 913 .name = "Aquantia AQR405", 914 .config_aneg = aqr_config_aneg, 915 .config_intr = aqr_config_intr, 916 .handle_interrupt = aqr_handle_interrupt, 917 .read_status = aqr_read_status, 918 }, 919 { 920 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 921 .name = "Aquantia AQR112", 922 .probe = aqr107_probe, 923 .config_aneg = aqr_config_aneg, 924 .config_intr = aqr_config_intr, 925 .handle_interrupt = aqr_handle_interrupt, 926 .get_tunable = aqr107_get_tunable, 927 .set_tunable = aqr107_set_tunable, 928 .suspend = aqr107_suspend, 929 .resume = aqr107_resume, 930 .read_status = aqr107_read_status, 931 .get_rate_matching = aqr107_get_rate_matching, 932 .get_sset_count = aqr107_get_sset_count, 933 .get_strings = aqr107_get_strings, 934 .get_stats = aqr107_get_stats, 935 .link_change_notify = aqr107_link_change_notify, 936 .led_brightness_set = aqr_phy_led_brightness_set, 937 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 938 .led_hw_control_set = aqr_phy_led_hw_control_set, 939 .led_hw_control_get = aqr_phy_led_hw_control_get, 940 .led_polarity_set = aqr_phy_led_polarity_set, 941 }, 942 { 943 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 944 .name = "Aquantia AQR412", 945 .probe = aqr107_probe, 946 .config_aneg = aqr_config_aneg, 947 .config_intr = aqr_config_intr, 948 .handle_interrupt = aqr_handle_interrupt, 949 .get_tunable = aqr107_get_tunable, 950 .set_tunable = aqr107_set_tunable, 951 .suspend = aqr107_suspend, 952 .resume = aqr107_resume, 953 .read_status = aqr107_read_status, 954 .get_rate_matching = aqr107_get_rate_matching, 955 .get_sset_count = aqr107_get_sset_count, 956 .get_strings = aqr107_get_strings, 957 .get_stats = aqr107_get_stats, 958 .link_change_notify = aqr107_link_change_notify, 959 }, 960 { 961 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 962 .name = "Aquantia AQR113", 963 .probe = aqr107_probe, 964 .get_rate_matching = aqr107_get_rate_matching, 965 .config_init = aqr113c_config_init, 966 .config_aneg = aqr_config_aneg, 967 .config_intr = aqr_config_intr, 968 .handle_interrupt = aqr_handle_interrupt, 969 .read_status = aqr107_read_status, 970 .get_tunable = aqr107_get_tunable, 971 .set_tunable = aqr107_set_tunable, 972 .suspend = aqr107_suspend, 973 .resume = aqr107_resume, 974 .get_sset_count = aqr107_get_sset_count, 975 .get_strings = aqr107_get_strings, 976 .get_stats = aqr107_get_stats, 977 .link_change_notify = aqr107_link_change_notify, 978 .led_brightness_set = aqr_phy_led_brightness_set, 979 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 980 .led_hw_control_set = aqr_phy_led_hw_control_set, 981 .led_hw_control_get = aqr_phy_led_hw_control_get, 982 .led_polarity_set = aqr_phy_led_polarity_set, 983 }, 984 { 985 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 986 .name = "Aquantia AQR113C", 987 .probe = aqr107_probe, 988 .get_rate_matching = aqr107_get_rate_matching, 989 .config_init = aqr113c_config_init, 990 .config_aneg = aqr_config_aneg, 991 .config_intr = aqr_config_intr, 992 .handle_interrupt = aqr_handle_interrupt, 993 .read_status = aqr107_read_status, 994 .get_tunable = aqr107_get_tunable, 995 .set_tunable = aqr107_set_tunable, 996 .suspend = aqr107_suspend, 997 .resume = aqr107_resume, 998 .get_sset_count = aqr107_get_sset_count, 999 .get_strings = aqr107_get_strings, 1000 .get_stats = aqr107_get_stats, 1001 .link_change_notify = aqr107_link_change_notify, 1002 .led_brightness_set = aqr_phy_led_brightness_set, 1003 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1004 .led_hw_control_set = aqr_phy_led_hw_control_set, 1005 .led_hw_control_get = aqr_phy_led_hw_control_get, 1006 .led_polarity_set = aqr_phy_led_polarity_set, 1007 }, 1008 { 1009 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1010 .name = "Aquantia AQR114C", 1011 .probe = aqr107_probe, 1012 .get_rate_matching = aqr107_get_rate_matching, 1013 .config_init = aqr111_config_init, 1014 .config_aneg = aqr_config_aneg, 1015 .config_intr = aqr_config_intr, 1016 .handle_interrupt = aqr_handle_interrupt, 1017 .read_status = aqr107_read_status, 1018 .get_tunable = aqr107_get_tunable, 1019 .set_tunable = aqr107_set_tunable, 1020 .suspend = aqr107_suspend, 1021 .resume = aqr107_resume, 1022 .get_sset_count = aqr107_get_sset_count, 1023 .get_strings = aqr107_get_strings, 1024 .get_stats = aqr107_get_stats, 1025 .link_change_notify = aqr107_link_change_notify, 1026 .led_brightness_set = aqr_phy_led_brightness_set, 1027 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1028 .led_hw_control_set = aqr_phy_led_hw_control_set, 1029 .led_hw_control_get = aqr_phy_led_hw_control_get, 1030 .led_polarity_set = aqr_phy_led_polarity_set, 1031 }, 1032 { 1033 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1034 .name = "Aquantia AQR115C", 1035 .probe = aqr107_probe, 1036 .get_rate_matching = aqr107_get_rate_matching, 1037 .config_init = aqr113c_config_init, 1038 .config_aneg = aqr_config_aneg, 1039 .config_intr = aqr_config_intr, 1040 .handle_interrupt = aqr_handle_interrupt, 1041 .read_status = aqr107_read_status, 1042 .get_tunable = aqr107_get_tunable, 1043 .set_tunable = aqr107_set_tunable, 1044 .suspend = aqr107_suspend, 1045 .resume = aqr107_resume, 1046 .get_sset_count = aqr107_get_sset_count, 1047 .get_strings = aqr107_get_strings, 1048 .get_stats = aqr107_get_stats, 1049 .link_change_notify = aqr107_link_change_notify, 1050 .led_brightness_set = aqr_phy_led_brightness_set, 1051 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1052 .led_hw_control_set = aqr_phy_led_hw_control_set, 1053 .led_hw_control_get = aqr_phy_led_hw_control_get, 1054 .led_polarity_set = aqr_phy_led_polarity_set, 1055 }, 1056 { 1057 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1058 .name = "Aquantia AQR813", 1059 .probe = aqr107_probe, 1060 .get_rate_matching = aqr107_get_rate_matching, 1061 .config_init = aqr107_config_init, 1062 .config_aneg = aqr_config_aneg, 1063 .config_intr = aqr_config_intr, 1064 .handle_interrupt = aqr_handle_interrupt, 1065 .read_status = aqr107_read_status, 1066 .get_tunable = aqr107_get_tunable, 1067 .set_tunable = aqr107_set_tunable, 1068 .suspend = aqr107_suspend, 1069 .resume = aqr107_resume, 1070 .get_sset_count = aqr107_get_sset_count, 1071 .get_strings = aqr107_get_strings, 1072 .get_stats = aqr107_get_stats, 1073 .link_change_notify = aqr107_link_change_notify, 1074 .led_brightness_set = aqr_phy_led_brightness_set, 1075 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1076 .led_hw_control_set = aqr_phy_led_hw_control_set, 1077 .led_hw_control_get = aqr_phy_led_hw_control_get, 1078 .led_polarity_set = aqr_phy_led_polarity_set, 1079 }, 1080 }; 1081 1082 module_phy_driver(aqr_driver); 1083 1084 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1085 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1086 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1087 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1088 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1089 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1090 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1091 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1092 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1093 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1094 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1095 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1096 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1097 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1098 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1099 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1100 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1101 { } 1102 }; 1103 1104 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1105 1106 MODULE_DESCRIPTION("Aquantia PHY driver"); 1107 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1108 MODULE_LICENSE("GPL v2"); 1109