1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR111 0x03a1b610 26 #define PHY_ID_AQR111B0 0x03a1b612 27 #define PHY_ID_AQR112 0x03a1b662 28 #define PHY_ID_AQR412 0x03a1b712 29 #define PHY_ID_AQR113 0x31c31c40 30 #define PHY_ID_AQR113C 0x31c31c12 31 #define PHY_ID_AQR114C 0x31c31c22 32 #define PHY_ID_AQR813 0x31c31cb2 33 34 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 35 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 44 45 #define MDIO_AN_VEND_PROV 0xc400 46 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 47 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 48 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 49 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 50 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 51 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 52 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 53 54 #define MDIO_AN_TX_VEND_STATUS1 0xc800 55 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 56 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 57 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 58 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 59 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 60 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 61 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 62 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 63 64 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 65 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 66 67 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 68 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 69 70 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 71 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 72 73 #define MDIO_AN_RX_LP_STAT1 0xe820 74 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 75 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 76 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 77 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 78 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 79 80 #define MDIO_AN_RX_LP_STAT4 0xe823 81 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 82 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 83 84 #define MDIO_AN_RX_VEND_STAT3 0xe832 85 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 86 87 /* Sleep and timeout for checking if the Processor-Intensive 88 * MDIO operation is finished 89 */ 90 #define AQR107_OP_IN_PROG_SLEEP 1000 91 #define AQR107_OP_IN_PROG_TIMEOUT 100000 92 93 static int aqr107_get_sset_count(struct phy_device *phydev) 94 { 95 return AQR107_SGMII_STAT_SZ; 96 } 97 98 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 99 { 100 int i; 101 102 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 103 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 104 ETH_GSTRING_LEN); 105 } 106 107 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 108 { 109 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 110 int len_l = min(stat->size, 16); 111 int len_h = stat->size - len_l; 112 u64 ret; 113 int val; 114 115 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 116 if (val < 0) 117 return U64_MAX; 118 119 ret = val & GENMASK(len_l - 1, 0); 120 if (len_h) { 121 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 122 if (val < 0) 123 return U64_MAX; 124 125 ret += (val & GENMASK(len_h - 1, 0)) << 16; 126 } 127 128 return ret; 129 } 130 131 static void aqr107_get_stats(struct phy_device *phydev, 132 struct ethtool_stats *stats, u64 *data) 133 { 134 struct aqr107_priv *priv = phydev->priv; 135 u64 val; 136 int i; 137 138 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 139 val = aqr107_get_stat(phydev, i); 140 if (val == U64_MAX) 141 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 142 aqr107_hw_stats[i].name); 143 else 144 priv->sgmii_stats[i] += val; 145 146 data[i] = priv->sgmii_stats[i]; 147 } 148 } 149 150 static int aqr_config_aneg(struct phy_device *phydev) 151 { 152 bool changed = false; 153 u16 reg; 154 int ret; 155 156 if (phydev->autoneg == AUTONEG_DISABLE) 157 return genphy_c45_pma_setup_forced(phydev); 158 159 ret = genphy_c45_an_config_aneg(phydev); 160 if (ret < 0) 161 return ret; 162 if (ret > 0) 163 changed = true; 164 165 /* Clause 45 has no standardized support for 1000BaseT, therefore 166 * use vendor registers for this mode. 167 */ 168 reg = 0; 169 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 170 phydev->advertising)) 171 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 172 173 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 174 phydev->advertising)) 175 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 176 177 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 178 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 179 phydev->advertising)) 180 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 181 182 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 183 phydev->advertising)) 184 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 185 186 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 187 MDIO_AN_VEND_PROV_1000BASET_HALF | 188 MDIO_AN_VEND_PROV_1000BASET_FULL | 189 MDIO_AN_VEND_PROV_2500BASET_FULL | 190 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 191 if (ret < 0) 192 return ret; 193 if (ret > 0) 194 changed = true; 195 196 return genphy_c45_check_and_restart_aneg(phydev, changed); 197 } 198 199 static int aqr_config_intr(struct phy_device *phydev) 200 { 201 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 202 int err; 203 204 if (en) { 205 /* Clear any pending interrupts before enabling them */ 206 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 207 if (err < 0) 208 return err; 209 } 210 211 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 212 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 213 if (err < 0) 214 return err; 215 216 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 217 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 218 if (err < 0) 219 return err; 220 221 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 222 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 223 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 224 if (err < 0) 225 return err; 226 227 if (!en) { 228 /* Clear any pending interrupts after we have disabled them */ 229 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 230 if (err < 0) 231 return err; 232 } 233 234 return 0; 235 } 236 237 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 238 { 239 int irq_status; 240 241 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 242 MDIO_AN_TX_VEND_INT_STATUS2); 243 if (irq_status < 0) { 244 phy_error(phydev); 245 return IRQ_NONE; 246 } 247 248 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 249 return IRQ_NONE; 250 251 phy_trigger_machine(phydev); 252 253 return IRQ_HANDLED; 254 } 255 256 static int aqr_read_status(struct phy_device *phydev) 257 { 258 int val; 259 260 if (phydev->autoneg == AUTONEG_ENABLE) { 261 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 262 if (val < 0) 263 return val; 264 265 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 266 phydev->lp_advertising, 267 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 268 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 269 phydev->lp_advertising, 270 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 271 } 272 273 return genphy_c45_read_status(phydev); 274 } 275 276 static int aqr107_read_rate(struct phy_device *phydev) 277 { 278 u32 config_reg; 279 int val; 280 281 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 282 if (val < 0) 283 return val; 284 285 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 286 phydev->duplex = DUPLEX_FULL; 287 else 288 phydev->duplex = DUPLEX_HALF; 289 290 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 291 case MDIO_AN_TX_VEND_STATUS1_10BASET: 292 phydev->speed = SPEED_10; 293 config_reg = VEND1_GLOBAL_CFG_10M; 294 break; 295 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 296 phydev->speed = SPEED_100; 297 config_reg = VEND1_GLOBAL_CFG_100M; 298 break; 299 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 300 phydev->speed = SPEED_1000; 301 config_reg = VEND1_GLOBAL_CFG_1G; 302 break; 303 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 304 phydev->speed = SPEED_2500; 305 config_reg = VEND1_GLOBAL_CFG_2_5G; 306 break; 307 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 308 phydev->speed = SPEED_5000; 309 config_reg = VEND1_GLOBAL_CFG_5G; 310 break; 311 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 312 phydev->speed = SPEED_10000; 313 config_reg = VEND1_GLOBAL_CFG_10G; 314 break; 315 default: 316 phydev->speed = SPEED_UNKNOWN; 317 return 0; 318 } 319 320 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 321 if (val < 0) 322 return val; 323 324 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 325 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 326 phydev->rate_matching = RATE_MATCH_PAUSE; 327 else 328 phydev->rate_matching = RATE_MATCH_NONE; 329 330 return 0; 331 } 332 333 static int aqr107_read_status(struct phy_device *phydev) 334 { 335 int val, ret; 336 337 ret = aqr_read_status(phydev); 338 if (ret) 339 return ret; 340 341 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 342 return 0; 343 344 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 345 if (val < 0) 346 return val; 347 348 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 349 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 350 phydev->interface = PHY_INTERFACE_MODE_10GKR; 351 break; 352 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 353 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 354 break; 355 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 356 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 357 break; 358 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 359 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 360 break; 361 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 362 phydev->interface = PHY_INTERFACE_MODE_XAUI; 363 break; 364 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 365 phydev->interface = PHY_INTERFACE_MODE_SGMII; 366 break; 367 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 368 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 369 break; 370 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 371 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 372 break; 373 default: 374 phydev->interface = PHY_INTERFACE_MODE_NA; 375 break; 376 } 377 378 /* Read possibly downshifted rate from vendor register */ 379 return aqr107_read_rate(phydev); 380 } 381 382 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 383 { 384 int val, cnt, enable; 385 386 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 387 if (val < 0) 388 return val; 389 390 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 391 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 392 393 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 394 395 return 0; 396 } 397 398 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 399 { 400 int val = 0; 401 402 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 403 return -E2BIG; 404 405 if (cnt != DOWNSHIFT_DEV_DISABLE) { 406 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 407 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 408 } 409 410 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 411 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 412 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 413 } 414 415 static int aqr107_get_tunable(struct phy_device *phydev, 416 struct ethtool_tunable *tuna, void *data) 417 { 418 switch (tuna->id) { 419 case ETHTOOL_PHY_DOWNSHIFT: 420 return aqr107_get_downshift(phydev, data); 421 default: 422 return -EOPNOTSUPP; 423 } 424 } 425 426 static int aqr107_set_tunable(struct phy_device *phydev, 427 struct ethtool_tunable *tuna, const void *data) 428 { 429 switch (tuna->id) { 430 case ETHTOOL_PHY_DOWNSHIFT: 431 return aqr107_set_downshift(phydev, *(const u8 *)data); 432 default: 433 return -EOPNOTSUPP; 434 } 435 } 436 437 /* If we configure settings whilst firmware is still initializing the chip, 438 * then these settings may be overwritten. Therefore make sure chip 439 * initialization has completed. Use presence of the firmware ID as 440 * indicator for initialization having completed. 441 * The chip also provides a "reset completed" bit, but it's cleared after 442 * read. Therefore function would time out if called again. 443 */ 444 static int aqr107_wait_reset_complete(struct phy_device *phydev) 445 { 446 int val; 447 448 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 449 VEND1_GLOBAL_FW_ID, val, val != 0, 450 20000, 2000000, false); 451 } 452 453 static void aqr107_chip_info(struct phy_device *phydev) 454 { 455 u8 fw_major, fw_minor, build_id, prov_id; 456 int val; 457 458 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 459 if (val < 0) 460 return; 461 462 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 463 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 464 465 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 466 if (val < 0) 467 return; 468 469 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 470 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 471 472 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 473 fw_major, fw_minor, build_id, prov_id); 474 } 475 476 static int aqr107_config_init(struct phy_device *phydev) 477 { 478 struct aqr107_priv *priv = phydev->priv; 479 u32 led_active_low; 480 int ret, index = 0; 481 482 /* Check that the PHY interface type is compatible */ 483 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 484 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 485 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 486 phydev->interface != PHY_INTERFACE_MODE_XGMII && 487 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 488 phydev->interface != PHY_INTERFACE_MODE_10GKR && 489 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 490 phydev->interface != PHY_INTERFACE_MODE_XAUI && 491 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 492 return -ENODEV; 493 494 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 495 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 496 497 ret = aqr107_wait_reset_complete(phydev); 498 if (!ret) 499 aqr107_chip_info(phydev); 500 501 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 502 if (ret) 503 return ret; 504 505 /* Restore LED polarity state after reset */ 506 for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { 507 ret = aqr_phy_led_active_low_set(phydev, index, led_active_low); 508 if (ret) 509 return ret; 510 index++; 511 } 512 513 return 0; 514 } 515 516 static int aqcs109_config_init(struct phy_device *phydev) 517 { 518 int ret; 519 520 /* Check that the PHY interface type is compatible */ 521 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 522 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 523 return -ENODEV; 524 525 ret = aqr107_wait_reset_complete(phydev); 526 if (!ret) 527 aqr107_chip_info(phydev); 528 529 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 530 * PMA speed ability bits are the same for all members of the family, 531 * AQCS109 however supports speeds up to 2.5G only. 532 */ 533 phy_set_max_speed(phydev, SPEED_2500); 534 535 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 536 } 537 538 static void aqr107_link_change_notify(struct phy_device *phydev) 539 { 540 u8 fw_major, fw_minor; 541 bool downshift, short_reach, afr; 542 int mode, val; 543 544 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 545 return; 546 547 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 548 /* call failed or link partner is no Aquantia PHY */ 549 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 550 return; 551 552 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 553 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 554 555 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 556 if (val < 0) 557 return; 558 559 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 560 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 561 562 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 563 if (val < 0) 564 return; 565 566 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 567 568 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 569 fw_major, fw_minor, 570 short_reach ? ", short reach mode" : "", 571 downshift ? ", fast-retrain downshift advertised" : "", 572 afr ? ", fast reframe advertised" : ""); 573 574 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 575 if (val < 0) 576 return; 577 578 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 579 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 580 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 581 } 582 583 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 584 { 585 int val, err; 586 587 /* The datasheet notes to wait at least 1ms after issuing a 588 * processor intensive operation before checking. 589 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 590 * because that just determines the maximum time slept, not the minimum. 591 */ 592 usleep_range(1000, 5000); 593 594 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 595 VEND1_GLOBAL_GEN_STAT2, val, 596 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 597 AQR107_OP_IN_PROG_SLEEP, 598 AQR107_OP_IN_PROG_TIMEOUT, false); 599 if (err) { 600 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 601 return err; 602 } 603 604 return 0; 605 } 606 607 static int aqr107_get_rate_matching(struct phy_device *phydev, 608 phy_interface_t iface) 609 { 610 if (iface == PHY_INTERFACE_MODE_10GBASER || 611 iface == PHY_INTERFACE_MODE_2500BASEX || 612 iface == PHY_INTERFACE_MODE_NA) 613 return RATE_MATCH_PAUSE; 614 return RATE_MATCH_NONE; 615 } 616 617 static int aqr107_suspend(struct phy_device *phydev) 618 { 619 int err; 620 621 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 622 MDIO_CTRL1_LPOWER); 623 if (err) 624 return err; 625 626 return aqr107_wait_processor_intensive_op(phydev); 627 } 628 629 static int aqr107_resume(struct phy_device *phydev) 630 { 631 int err; 632 633 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 634 MDIO_CTRL1_LPOWER); 635 if (err) 636 return err; 637 638 return aqr107_wait_processor_intensive_op(phydev); 639 } 640 641 static const u16 aqr_global_cfg_regs[] = { 642 VEND1_GLOBAL_CFG_10M, 643 VEND1_GLOBAL_CFG_100M, 644 VEND1_GLOBAL_CFG_1G, 645 VEND1_GLOBAL_CFG_2_5G, 646 VEND1_GLOBAL_CFG_5G, 647 VEND1_GLOBAL_CFG_10G 648 }; 649 650 static int aqr107_fill_interface_modes(struct phy_device *phydev) 651 { 652 unsigned long *possible = phydev->possible_interfaces; 653 unsigned int serdes_mode, rate_adapt; 654 phy_interface_t interface; 655 int i, val; 656 657 /* Walk the media-speed configuration registers to determine which 658 * host-side serdes modes may be used by the PHY depending on the 659 * negotiated media speed. 660 */ 661 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 662 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 663 aqr_global_cfg_regs[i]); 664 if (val < 0) 665 return val; 666 667 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 668 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 669 670 switch (serdes_mode) { 671 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 672 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 673 interface = PHY_INTERFACE_MODE_USXGMII; 674 else 675 interface = PHY_INTERFACE_MODE_10GBASER; 676 break; 677 678 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 679 interface = PHY_INTERFACE_MODE_5GBASER; 680 break; 681 682 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 683 interface = PHY_INTERFACE_MODE_2500BASEX; 684 break; 685 686 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 687 interface = PHY_INTERFACE_MODE_SGMII; 688 break; 689 690 default: 691 phydev_warn(phydev, "unrecognised serdes mode %u\n", 692 serdes_mode); 693 interface = PHY_INTERFACE_MODE_NA; 694 break; 695 } 696 697 if (interface != PHY_INTERFACE_MODE_NA) 698 __set_bit(interface, possible); 699 } 700 701 return 0; 702 } 703 704 static int aqr113c_config_init(struct phy_device *phydev) 705 { 706 int ret; 707 708 ret = aqr107_config_init(phydev); 709 if (ret < 0) 710 return ret; 711 712 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 713 MDIO_PMD_TXDIS_GLOBAL); 714 if (ret) 715 return ret; 716 717 ret = aqr107_wait_processor_intensive_op(phydev); 718 if (ret) 719 return ret; 720 721 return aqr107_fill_interface_modes(phydev); 722 } 723 724 static int aqr107_probe(struct phy_device *phydev) 725 { 726 int ret; 727 728 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 729 sizeof(struct aqr107_priv), GFP_KERNEL); 730 if (!phydev->priv) 731 return -ENOMEM; 732 733 ret = aqr_firmware_load(phydev); 734 if (ret) 735 return ret; 736 737 return aqr_hwmon_probe(phydev); 738 } 739 740 static int aqr111_config_init(struct phy_device *phydev) 741 { 742 /* AQR111 reports supporting speed up to 10G, 743 * however only speeds up to 5G are supported. 744 */ 745 phy_set_max_speed(phydev, SPEED_5000); 746 747 return aqr107_config_init(phydev); 748 } 749 750 static struct phy_driver aqr_driver[] = { 751 { 752 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 753 .name = "Aquantia AQ1202", 754 .config_aneg = aqr_config_aneg, 755 .config_intr = aqr_config_intr, 756 .handle_interrupt = aqr_handle_interrupt, 757 .read_status = aqr_read_status, 758 }, 759 { 760 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 761 .name = "Aquantia AQ2104", 762 .config_aneg = aqr_config_aneg, 763 .config_intr = aqr_config_intr, 764 .handle_interrupt = aqr_handle_interrupt, 765 .read_status = aqr_read_status, 766 }, 767 { 768 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 769 .name = "Aquantia AQR105", 770 .config_aneg = aqr_config_aneg, 771 .config_intr = aqr_config_intr, 772 .handle_interrupt = aqr_handle_interrupt, 773 .read_status = aqr_read_status, 774 .suspend = aqr107_suspend, 775 .resume = aqr107_resume, 776 }, 777 { 778 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 779 .name = "Aquantia AQR106", 780 .config_aneg = aqr_config_aneg, 781 .config_intr = aqr_config_intr, 782 .handle_interrupt = aqr_handle_interrupt, 783 .read_status = aqr_read_status, 784 }, 785 { 786 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 787 .name = "Aquantia AQR107", 788 .probe = aqr107_probe, 789 .get_rate_matching = aqr107_get_rate_matching, 790 .config_init = aqr107_config_init, 791 .config_aneg = aqr_config_aneg, 792 .config_intr = aqr_config_intr, 793 .handle_interrupt = aqr_handle_interrupt, 794 .read_status = aqr107_read_status, 795 .get_tunable = aqr107_get_tunable, 796 .set_tunable = aqr107_set_tunable, 797 .suspend = aqr107_suspend, 798 .resume = aqr107_resume, 799 .get_sset_count = aqr107_get_sset_count, 800 .get_strings = aqr107_get_strings, 801 .get_stats = aqr107_get_stats, 802 .link_change_notify = aqr107_link_change_notify, 803 .led_brightness_set = aqr_phy_led_brightness_set, 804 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 805 .led_hw_control_set = aqr_phy_led_hw_control_set, 806 .led_hw_control_get = aqr_phy_led_hw_control_get, 807 .led_polarity_set = aqr_phy_led_polarity_set, 808 }, 809 { 810 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 811 .name = "Aquantia AQCS109", 812 .probe = aqr107_probe, 813 .get_rate_matching = aqr107_get_rate_matching, 814 .config_init = aqcs109_config_init, 815 .config_aneg = aqr_config_aneg, 816 .config_intr = aqr_config_intr, 817 .handle_interrupt = aqr_handle_interrupt, 818 .read_status = aqr107_read_status, 819 .get_tunable = aqr107_get_tunable, 820 .set_tunable = aqr107_set_tunable, 821 .suspend = aqr107_suspend, 822 .resume = aqr107_resume, 823 .get_sset_count = aqr107_get_sset_count, 824 .get_strings = aqr107_get_strings, 825 .get_stats = aqr107_get_stats, 826 .link_change_notify = aqr107_link_change_notify, 827 .led_brightness_set = aqr_phy_led_brightness_set, 828 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 829 .led_hw_control_set = aqr_phy_led_hw_control_set, 830 .led_hw_control_get = aqr_phy_led_hw_control_get, 831 .led_polarity_set = aqr_phy_led_polarity_set, 832 }, 833 { 834 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 835 .name = "Aquantia AQR111", 836 .probe = aqr107_probe, 837 .get_rate_matching = aqr107_get_rate_matching, 838 .config_init = aqr111_config_init, 839 .config_aneg = aqr_config_aneg, 840 .config_intr = aqr_config_intr, 841 .handle_interrupt = aqr_handle_interrupt, 842 .read_status = aqr107_read_status, 843 .get_tunable = aqr107_get_tunable, 844 .set_tunable = aqr107_set_tunable, 845 .suspend = aqr107_suspend, 846 .resume = aqr107_resume, 847 .get_sset_count = aqr107_get_sset_count, 848 .get_strings = aqr107_get_strings, 849 .get_stats = aqr107_get_stats, 850 .link_change_notify = aqr107_link_change_notify, 851 .led_brightness_set = aqr_phy_led_brightness_set, 852 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 853 .led_hw_control_set = aqr_phy_led_hw_control_set, 854 .led_hw_control_get = aqr_phy_led_hw_control_get, 855 .led_polarity_set = aqr_phy_led_polarity_set, 856 }, 857 { 858 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 859 .name = "Aquantia AQR111B0", 860 .probe = aqr107_probe, 861 .get_rate_matching = aqr107_get_rate_matching, 862 .config_init = aqr111_config_init, 863 .config_aneg = aqr_config_aneg, 864 .config_intr = aqr_config_intr, 865 .handle_interrupt = aqr_handle_interrupt, 866 .read_status = aqr107_read_status, 867 .get_tunable = aqr107_get_tunable, 868 .set_tunable = aqr107_set_tunable, 869 .suspend = aqr107_suspend, 870 .resume = aqr107_resume, 871 .get_sset_count = aqr107_get_sset_count, 872 .get_strings = aqr107_get_strings, 873 .get_stats = aqr107_get_stats, 874 .link_change_notify = aqr107_link_change_notify, 875 .led_brightness_set = aqr_phy_led_brightness_set, 876 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 877 .led_hw_control_set = aqr_phy_led_hw_control_set, 878 .led_hw_control_get = aqr_phy_led_hw_control_get, 879 .led_polarity_set = aqr_phy_led_polarity_set, 880 }, 881 { 882 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 883 .name = "Aquantia AQR405", 884 .config_aneg = aqr_config_aneg, 885 .config_intr = aqr_config_intr, 886 .handle_interrupt = aqr_handle_interrupt, 887 .read_status = aqr_read_status, 888 }, 889 { 890 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 891 .name = "Aquantia AQR112", 892 .probe = aqr107_probe, 893 .config_aneg = aqr_config_aneg, 894 .config_intr = aqr_config_intr, 895 .handle_interrupt = aqr_handle_interrupt, 896 .get_tunable = aqr107_get_tunable, 897 .set_tunable = aqr107_set_tunable, 898 .suspend = aqr107_suspend, 899 .resume = aqr107_resume, 900 .read_status = aqr107_read_status, 901 .get_rate_matching = aqr107_get_rate_matching, 902 .get_sset_count = aqr107_get_sset_count, 903 .get_strings = aqr107_get_strings, 904 .get_stats = aqr107_get_stats, 905 .link_change_notify = aqr107_link_change_notify, 906 .led_brightness_set = aqr_phy_led_brightness_set, 907 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 908 .led_hw_control_set = aqr_phy_led_hw_control_set, 909 .led_hw_control_get = aqr_phy_led_hw_control_get, 910 .led_polarity_set = aqr_phy_led_polarity_set, 911 }, 912 { 913 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 914 .name = "Aquantia AQR412", 915 .probe = aqr107_probe, 916 .config_aneg = aqr_config_aneg, 917 .config_intr = aqr_config_intr, 918 .handle_interrupt = aqr_handle_interrupt, 919 .get_tunable = aqr107_get_tunable, 920 .set_tunable = aqr107_set_tunable, 921 .suspend = aqr107_suspend, 922 .resume = aqr107_resume, 923 .read_status = aqr107_read_status, 924 .get_rate_matching = aqr107_get_rate_matching, 925 .get_sset_count = aqr107_get_sset_count, 926 .get_strings = aqr107_get_strings, 927 .get_stats = aqr107_get_stats, 928 .link_change_notify = aqr107_link_change_notify, 929 }, 930 { 931 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 932 .name = "Aquantia AQR113", 933 .probe = aqr107_probe, 934 .get_rate_matching = aqr107_get_rate_matching, 935 .config_init = aqr113c_config_init, 936 .config_aneg = aqr_config_aneg, 937 .config_intr = aqr_config_intr, 938 .handle_interrupt = aqr_handle_interrupt, 939 .read_status = aqr107_read_status, 940 .get_tunable = aqr107_get_tunable, 941 .set_tunable = aqr107_set_tunable, 942 .suspend = aqr107_suspend, 943 .resume = aqr107_resume, 944 .get_sset_count = aqr107_get_sset_count, 945 .get_strings = aqr107_get_strings, 946 .get_stats = aqr107_get_stats, 947 .link_change_notify = aqr107_link_change_notify, 948 .led_brightness_set = aqr_phy_led_brightness_set, 949 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 950 .led_hw_control_set = aqr_phy_led_hw_control_set, 951 .led_hw_control_get = aqr_phy_led_hw_control_get, 952 .led_polarity_set = aqr_phy_led_polarity_set, 953 }, 954 { 955 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 956 .name = "Aquantia AQR113C", 957 .probe = aqr107_probe, 958 .get_rate_matching = aqr107_get_rate_matching, 959 .config_init = aqr113c_config_init, 960 .config_aneg = aqr_config_aneg, 961 .config_intr = aqr_config_intr, 962 .handle_interrupt = aqr_handle_interrupt, 963 .read_status = aqr107_read_status, 964 .get_tunable = aqr107_get_tunable, 965 .set_tunable = aqr107_set_tunable, 966 .suspend = aqr107_suspend, 967 .resume = aqr107_resume, 968 .get_sset_count = aqr107_get_sset_count, 969 .get_strings = aqr107_get_strings, 970 .get_stats = aqr107_get_stats, 971 .link_change_notify = aqr107_link_change_notify, 972 .led_brightness_set = aqr_phy_led_brightness_set, 973 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 974 .led_hw_control_set = aqr_phy_led_hw_control_set, 975 .led_hw_control_get = aqr_phy_led_hw_control_get, 976 .led_polarity_set = aqr_phy_led_polarity_set, 977 }, 978 { 979 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 980 .name = "Aquantia AQR114C", 981 .probe = aqr107_probe, 982 .get_rate_matching = aqr107_get_rate_matching, 983 .config_init = aqr111_config_init, 984 .config_aneg = aqr_config_aneg, 985 .config_intr = aqr_config_intr, 986 .handle_interrupt = aqr_handle_interrupt, 987 .read_status = aqr107_read_status, 988 .get_tunable = aqr107_get_tunable, 989 .set_tunable = aqr107_set_tunable, 990 .suspend = aqr107_suspend, 991 .resume = aqr107_resume, 992 .get_sset_count = aqr107_get_sset_count, 993 .get_strings = aqr107_get_strings, 994 .get_stats = aqr107_get_stats, 995 .link_change_notify = aqr107_link_change_notify, 996 .led_brightness_set = aqr_phy_led_brightness_set, 997 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 998 .led_hw_control_set = aqr_phy_led_hw_control_set, 999 .led_hw_control_get = aqr_phy_led_hw_control_get, 1000 .led_polarity_set = aqr_phy_led_polarity_set, 1001 }, 1002 { 1003 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1004 .name = "Aquantia AQR813", 1005 .probe = aqr107_probe, 1006 .get_rate_matching = aqr107_get_rate_matching, 1007 .config_init = aqr107_config_init, 1008 .config_aneg = aqr_config_aneg, 1009 .config_intr = aqr_config_intr, 1010 .handle_interrupt = aqr_handle_interrupt, 1011 .read_status = aqr107_read_status, 1012 .get_tunable = aqr107_get_tunable, 1013 .set_tunable = aqr107_set_tunable, 1014 .suspend = aqr107_suspend, 1015 .resume = aqr107_resume, 1016 .get_sset_count = aqr107_get_sset_count, 1017 .get_strings = aqr107_get_strings, 1018 .get_stats = aqr107_get_stats, 1019 .link_change_notify = aqr107_link_change_notify, 1020 .led_brightness_set = aqr_phy_led_brightness_set, 1021 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1022 .led_hw_control_set = aqr_phy_led_hw_control_set, 1023 .led_hw_control_get = aqr_phy_led_hw_control_get, 1024 .led_polarity_set = aqr_phy_led_polarity_set, 1025 }, 1026 }; 1027 1028 module_phy_driver(aqr_driver); 1029 1030 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1031 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1032 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1033 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1034 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1035 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1036 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1037 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1038 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1039 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1040 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1041 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1042 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1043 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1044 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1045 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1046 { } 1047 }; 1048 1049 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1050 1051 MODULE_DESCRIPTION("Aquantia PHY driver"); 1052 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1053 MODULE_LICENSE("GPL v2"); 1054