1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR111 0x03a1b610 26 #define PHY_ID_AQR111B0 0x03a1b612 27 #define PHY_ID_AQR112 0x03a1b662 28 #define PHY_ID_AQR412 0x03a1b712 29 #define PHY_ID_AQR113 0x31c31c40 30 #define PHY_ID_AQR113C 0x31c31c12 31 #define PHY_ID_AQR813 0x31c31cb2 32 33 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 34 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 35 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 43 44 #define MDIO_AN_VEND_PROV 0xc400 45 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 46 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 47 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 48 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 49 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 50 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 51 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 52 53 #define MDIO_AN_TX_VEND_STATUS1 0xc800 54 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 55 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 56 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 57 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 58 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 59 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 60 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 61 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 62 63 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 64 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 65 66 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 67 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 68 69 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 70 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 71 72 #define MDIO_AN_RX_LP_STAT1 0xe820 73 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 74 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 75 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 76 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 77 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 78 79 #define MDIO_AN_RX_LP_STAT4 0xe823 80 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 81 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 82 83 #define MDIO_AN_RX_VEND_STAT3 0xe832 84 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 85 86 /* MDIO_MMD_C22EXT */ 87 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 88 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 89 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 90 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 91 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 92 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 93 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 94 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 95 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 96 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 97 98 /* Sleep and timeout for checking if the Processor-Intensive 99 * MDIO operation is finished 100 */ 101 #define AQR107_OP_IN_PROG_SLEEP 1000 102 #define AQR107_OP_IN_PROG_TIMEOUT 100000 103 104 struct aqr107_hw_stat { 105 const char *name; 106 int reg; 107 int size; 108 }; 109 110 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 111 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 112 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 113 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 114 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 115 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 116 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 117 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 118 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 119 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 120 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 121 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 122 }; 123 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 124 125 struct aqr107_priv { 126 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 127 }; 128 129 static int aqr107_get_sset_count(struct phy_device *phydev) 130 { 131 return AQR107_SGMII_STAT_SZ; 132 } 133 134 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 135 { 136 int i; 137 138 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 139 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 140 ETH_GSTRING_LEN); 141 } 142 143 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 144 { 145 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 146 int len_l = min(stat->size, 16); 147 int len_h = stat->size - len_l; 148 u64 ret; 149 int val; 150 151 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 152 if (val < 0) 153 return U64_MAX; 154 155 ret = val & GENMASK(len_l - 1, 0); 156 if (len_h) { 157 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 158 if (val < 0) 159 return U64_MAX; 160 161 ret += (val & GENMASK(len_h - 1, 0)) << 16; 162 } 163 164 return ret; 165 } 166 167 static void aqr107_get_stats(struct phy_device *phydev, 168 struct ethtool_stats *stats, u64 *data) 169 { 170 struct aqr107_priv *priv = phydev->priv; 171 u64 val; 172 int i; 173 174 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 175 val = aqr107_get_stat(phydev, i); 176 if (val == U64_MAX) 177 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 178 aqr107_hw_stats[i].name); 179 else 180 priv->sgmii_stats[i] += val; 181 182 data[i] = priv->sgmii_stats[i]; 183 } 184 } 185 186 static int aqr_config_aneg(struct phy_device *phydev) 187 { 188 bool changed = false; 189 u16 reg; 190 int ret; 191 192 if (phydev->autoneg == AUTONEG_DISABLE) 193 return genphy_c45_pma_setup_forced(phydev); 194 195 ret = genphy_c45_an_config_aneg(phydev); 196 if (ret < 0) 197 return ret; 198 if (ret > 0) 199 changed = true; 200 201 /* Clause 45 has no standardized support for 1000BaseT, therefore 202 * use vendor registers for this mode. 203 */ 204 reg = 0; 205 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 206 phydev->advertising)) 207 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 208 209 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 210 phydev->advertising)) 211 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 212 213 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 214 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 215 phydev->advertising)) 216 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 217 218 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 219 phydev->advertising)) 220 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 221 222 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 223 MDIO_AN_VEND_PROV_1000BASET_HALF | 224 MDIO_AN_VEND_PROV_1000BASET_FULL | 225 MDIO_AN_VEND_PROV_2500BASET_FULL | 226 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 227 if (ret < 0) 228 return ret; 229 if (ret > 0) 230 changed = true; 231 232 return genphy_c45_check_and_restart_aneg(phydev, changed); 233 } 234 235 static int aqr_config_intr(struct phy_device *phydev) 236 { 237 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 238 int err; 239 240 if (en) { 241 /* Clear any pending interrupts before enabling them */ 242 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 243 if (err < 0) 244 return err; 245 } 246 247 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 248 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 249 if (err < 0) 250 return err; 251 252 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 253 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 254 if (err < 0) 255 return err; 256 257 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 258 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 259 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 260 if (err < 0) 261 return err; 262 263 if (!en) { 264 /* Clear any pending interrupts after we have disabled them */ 265 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 266 if (err < 0) 267 return err; 268 } 269 270 return 0; 271 } 272 273 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 274 { 275 int irq_status; 276 277 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 278 MDIO_AN_TX_VEND_INT_STATUS2); 279 if (irq_status < 0) { 280 phy_error(phydev); 281 return IRQ_NONE; 282 } 283 284 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 285 return IRQ_NONE; 286 287 phy_trigger_machine(phydev); 288 289 return IRQ_HANDLED; 290 } 291 292 static int aqr_read_status(struct phy_device *phydev) 293 { 294 int val; 295 296 if (phydev->autoneg == AUTONEG_ENABLE) { 297 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 298 if (val < 0) 299 return val; 300 301 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 302 phydev->lp_advertising, 303 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 304 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 305 phydev->lp_advertising, 306 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 307 } 308 309 return genphy_c45_read_status(phydev); 310 } 311 312 static int aqr107_read_rate(struct phy_device *phydev) 313 { 314 u32 config_reg; 315 int val; 316 317 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 318 if (val < 0) 319 return val; 320 321 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 322 phydev->duplex = DUPLEX_FULL; 323 else 324 phydev->duplex = DUPLEX_HALF; 325 326 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 327 case MDIO_AN_TX_VEND_STATUS1_10BASET: 328 phydev->speed = SPEED_10; 329 config_reg = VEND1_GLOBAL_CFG_10M; 330 break; 331 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 332 phydev->speed = SPEED_100; 333 config_reg = VEND1_GLOBAL_CFG_100M; 334 break; 335 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 336 phydev->speed = SPEED_1000; 337 config_reg = VEND1_GLOBAL_CFG_1G; 338 break; 339 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 340 phydev->speed = SPEED_2500; 341 config_reg = VEND1_GLOBAL_CFG_2_5G; 342 break; 343 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 344 phydev->speed = SPEED_5000; 345 config_reg = VEND1_GLOBAL_CFG_5G; 346 break; 347 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 348 phydev->speed = SPEED_10000; 349 config_reg = VEND1_GLOBAL_CFG_10G; 350 break; 351 default: 352 phydev->speed = SPEED_UNKNOWN; 353 return 0; 354 } 355 356 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 357 if (val < 0) 358 return val; 359 360 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 361 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 362 phydev->rate_matching = RATE_MATCH_PAUSE; 363 else 364 phydev->rate_matching = RATE_MATCH_NONE; 365 366 return 0; 367 } 368 369 static int aqr107_read_status(struct phy_device *phydev) 370 { 371 int val, ret; 372 373 ret = aqr_read_status(phydev); 374 if (ret) 375 return ret; 376 377 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 378 return 0; 379 380 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 381 if (val < 0) 382 return val; 383 384 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 385 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 386 phydev->interface = PHY_INTERFACE_MODE_10GKR; 387 break; 388 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 389 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 390 break; 391 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 392 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 393 break; 394 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 395 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 396 break; 397 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 398 phydev->interface = PHY_INTERFACE_MODE_XAUI; 399 break; 400 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 401 phydev->interface = PHY_INTERFACE_MODE_SGMII; 402 break; 403 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 404 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 405 break; 406 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 407 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 408 break; 409 default: 410 phydev->interface = PHY_INTERFACE_MODE_NA; 411 break; 412 } 413 414 /* Read possibly downshifted rate from vendor register */ 415 return aqr107_read_rate(phydev); 416 } 417 418 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 419 { 420 int val, cnt, enable; 421 422 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 423 if (val < 0) 424 return val; 425 426 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 427 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 428 429 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 430 431 return 0; 432 } 433 434 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 435 { 436 int val = 0; 437 438 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 439 return -E2BIG; 440 441 if (cnt != DOWNSHIFT_DEV_DISABLE) { 442 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 443 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 444 } 445 446 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 447 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 448 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 449 } 450 451 static int aqr107_get_tunable(struct phy_device *phydev, 452 struct ethtool_tunable *tuna, void *data) 453 { 454 switch (tuna->id) { 455 case ETHTOOL_PHY_DOWNSHIFT: 456 return aqr107_get_downshift(phydev, data); 457 default: 458 return -EOPNOTSUPP; 459 } 460 } 461 462 static int aqr107_set_tunable(struct phy_device *phydev, 463 struct ethtool_tunable *tuna, const void *data) 464 { 465 switch (tuna->id) { 466 case ETHTOOL_PHY_DOWNSHIFT: 467 return aqr107_set_downshift(phydev, *(const u8 *)data); 468 default: 469 return -EOPNOTSUPP; 470 } 471 } 472 473 /* If we configure settings whilst firmware is still initializing the chip, 474 * then these settings may be overwritten. Therefore make sure chip 475 * initialization has completed. Use presence of the firmware ID as 476 * indicator for initialization having completed. 477 * The chip also provides a "reset completed" bit, but it's cleared after 478 * read. Therefore function would time out if called again. 479 */ 480 static int aqr107_wait_reset_complete(struct phy_device *phydev) 481 { 482 int val; 483 484 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 485 VEND1_GLOBAL_FW_ID, val, val != 0, 486 20000, 2000000, false); 487 } 488 489 static void aqr107_chip_info(struct phy_device *phydev) 490 { 491 u8 fw_major, fw_minor, build_id, prov_id; 492 int val; 493 494 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 495 if (val < 0) 496 return; 497 498 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 499 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 500 501 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 502 if (val < 0) 503 return; 504 505 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 506 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 507 508 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 509 fw_major, fw_minor, build_id, prov_id); 510 } 511 512 static int aqr107_config_init(struct phy_device *phydev) 513 { 514 int ret; 515 516 /* Check that the PHY interface type is compatible */ 517 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 518 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 519 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 520 phydev->interface != PHY_INTERFACE_MODE_XGMII && 521 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 522 phydev->interface != PHY_INTERFACE_MODE_10GKR && 523 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 524 phydev->interface != PHY_INTERFACE_MODE_XAUI && 525 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 526 return -ENODEV; 527 528 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 529 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 530 531 ret = aqr107_wait_reset_complete(phydev); 532 if (!ret) 533 aqr107_chip_info(phydev); 534 535 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 536 } 537 538 static int aqcs109_config_init(struct phy_device *phydev) 539 { 540 int ret; 541 542 /* Check that the PHY interface type is compatible */ 543 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 544 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 545 return -ENODEV; 546 547 ret = aqr107_wait_reset_complete(phydev); 548 if (!ret) 549 aqr107_chip_info(phydev); 550 551 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 552 * PMA speed ability bits are the same for all members of the family, 553 * AQCS109 however supports speeds up to 2.5G only. 554 */ 555 phy_set_max_speed(phydev, SPEED_2500); 556 557 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 558 } 559 560 static void aqr107_link_change_notify(struct phy_device *phydev) 561 { 562 u8 fw_major, fw_minor; 563 bool downshift, short_reach, afr; 564 int mode, val; 565 566 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 567 return; 568 569 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 570 /* call failed or link partner is no Aquantia PHY */ 571 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 572 return; 573 574 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 575 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 576 577 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 578 if (val < 0) 579 return; 580 581 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 582 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 583 584 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 585 if (val < 0) 586 return; 587 588 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 589 590 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 591 fw_major, fw_minor, 592 short_reach ? ", short reach mode" : "", 593 downshift ? ", fast-retrain downshift advertised" : "", 594 afr ? ", fast reframe advertised" : ""); 595 596 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 597 if (val < 0) 598 return; 599 600 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 601 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 602 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 603 } 604 605 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 606 { 607 int val, err; 608 609 /* The datasheet notes to wait at least 1ms after issuing a 610 * processor intensive operation before checking. 611 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 612 * because that just determines the maximum time slept, not the minimum. 613 */ 614 usleep_range(1000, 5000); 615 616 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 617 VEND1_GLOBAL_GEN_STAT2, val, 618 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 619 AQR107_OP_IN_PROG_SLEEP, 620 AQR107_OP_IN_PROG_TIMEOUT, false); 621 if (err) { 622 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 623 return err; 624 } 625 626 return 0; 627 } 628 629 static int aqr107_get_rate_matching(struct phy_device *phydev, 630 phy_interface_t iface) 631 { 632 if (iface == PHY_INTERFACE_MODE_10GBASER || 633 iface == PHY_INTERFACE_MODE_2500BASEX || 634 iface == PHY_INTERFACE_MODE_NA) 635 return RATE_MATCH_PAUSE; 636 return RATE_MATCH_NONE; 637 } 638 639 static int aqr107_suspend(struct phy_device *phydev) 640 { 641 int err; 642 643 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 644 MDIO_CTRL1_LPOWER); 645 if (err) 646 return err; 647 648 return aqr107_wait_processor_intensive_op(phydev); 649 } 650 651 static int aqr107_resume(struct phy_device *phydev) 652 { 653 int err; 654 655 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 656 MDIO_CTRL1_LPOWER); 657 if (err) 658 return err; 659 660 return aqr107_wait_processor_intensive_op(phydev); 661 } 662 663 static const u16 aqr_global_cfg_regs[] = { 664 VEND1_GLOBAL_CFG_10M, 665 VEND1_GLOBAL_CFG_100M, 666 VEND1_GLOBAL_CFG_1G, 667 VEND1_GLOBAL_CFG_2_5G, 668 VEND1_GLOBAL_CFG_5G, 669 VEND1_GLOBAL_CFG_10G 670 }; 671 672 static int aqr107_fill_interface_modes(struct phy_device *phydev) 673 { 674 unsigned long *possible = phydev->possible_interfaces; 675 unsigned int serdes_mode, rate_adapt; 676 phy_interface_t interface; 677 int i, val; 678 679 /* Walk the media-speed configuration registers to determine which 680 * host-side serdes modes may be used by the PHY depending on the 681 * negotiated media speed. 682 */ 683 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 684 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 685 aqr_global_cfg_regs[i]); 686 if (val < 0) 687 return val; 688 689 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 690 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 691 692 switch (serdes_mode) { 693 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 694 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 695 interface = PHY_INTERFACE_MODE_USXGMII; 696 else 697 interface = PHY_INTERFACE_MODE_10GBASER; 698 break; 699 700 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 701 interface = PHY_INTERFACE_MODE_5GBASER; 702 break; 703 704 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 705 interface = PHY_INTERFACE_MODE_2500BASEX; 706 break; 707 708 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 709 interface = PHY_INTERFACE_MODE_SGMII; 710 break; 711 712 default: 713 phydev_warn(phydev, "unrecognised serdes mode %u\n", 714 serdes_mode); 715 interface = PHY_INTERFACE_MODE_NA; 716 break; 717 } 718 719 if (interface != PHY_INTERFACE_MODE_NA) 720 __set_bit(interface, possible); 721 } 722 723 return 0; 724 } 725 726 static int aqr113c_config_init(struct phy_device *phydev) 727 { 728 int ret; 729 730 ret = aqr107_config_init(phydev); 731 if (ret < 0) 732 return ret; 733 734 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 735 MDIO_PMD_TXDIS_GLOBAL); 736 if (ret) 737 return ret; 738 739 ret = aqr107_wait_processor_intensive_op(phydev); 740 if (ret) 741 return ret; 742 743 return aqr107_fill_interface_modes(phydev); 744 } 745 746 static int aqr107_probe(struct phy_device *phydev) 747 { 748 int ret; 749 750 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 751 sizeof(struct aqr107_priv), GFP_KERNEL); 752 if (!phydev->priv) 753 return -ENOMEM; 754 755 ret = aqr_firmware_load(phydev); 756 if (ret) 757 return ret; 758 759 return aqr_hwmon_probe(phydev); 760 } 761 762 static int aqr111_config_init(struct phy_device *phydev) 763 { 764 /* AQR111 reports supporting speed up to 10G, 765 * however only speeds up to 5G are supported. 766 */ 767 phy_set_max_speed(phydev, SPEED_5000); 768 769 return aqr107_config_init(phydev); 770 } 771 772 static struct phy_driver aqr_driver[] = { 773 { 774 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 775 .name = "Aquantia AQ1202", 776 .config_aneg = aqr_config_aneg, 777 .config_intr = aqr_config_intr, 778 .handle_interrupt = aqr_handle_interrupt, 779 .read_status = aqr_read_status, 780 }, 781 { 782 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 783 .name = "Aquantia AQ2104", 784 .config_aneg = aqr_config_aneg, 785 .config_intr = aqr_config_intr, 786 .handle_interrupt = aqr_handle_interrupt, 787 .read_status = aqr_read_status, 788 }, 789 { 790 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 791 .name = "Aquantia AQR105", 792 .config_aneg = aqr_config_aneg, 793 .config_intr = aqr_config_intr, 794 .handle_interrupt = aqr_handle_interrupt, 795 .read_status = aqr_read_status, 796 .suspend = aqr107_suspend, 797 .resume = aqr107_resume, 798 }, 799 { 800 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 801 .name = "Aquantia AQR106", 802 .config_aneg = aqr_config_aneg, 803 .config_intr = aqr_config_intr, 804 .handle_interrupt = aqr_handle_interrupt, 805 .read_status = aqr_read_status, 806 }, 807 { 808 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 809 .name = "Aquantia AQR107", 810 .probe = aqr107_probe, 811 .get_rate_matching = aqr107_get_rate_matching, 812 .config_init = aqr107_config_init, 813 .config_aneg = aqr_config_aneg, 814 .config_intr = aqr_config_intr, 815 .handle_interrupt = aqr_handle_interrupt, 816 .read_status = aqr107_read_status, 817 .get_tunable = aqr107_get_tunable, 818 .set_tunable = aqr107_set_tunable, 819 .suspend = aqr107_suspend, 820 .resume = aqr107_resume, 821 .get_sset_count = aqr107_get_sset_count, 822 .get_strings = aqr107_get_strings, 823 .get_stats = aqr107_get_stats, 824 .link_change_notify = aqr107_link_change_notify, 825 }, 826 { 827 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 828 .name = "Aquantia AQCS109", 829 .probe = aqr107_probe, 830 .get_rate_matching = aqr107_get_rate_matching, 831 .config_init = aqcs109_config_init, 832 .config_aneg = aqr_config_aneg, 833 .config_intr = aqr_config_intr, 834 .handle_interrupt = aqr_handle_interrupt, 835 .read_status = aqr107_read_status, 836 .get_tunable = aqr107_get_tunable, 837 .set_tunable = aqr107_set_tunable, 838 .suspend = aqr107_suspend, 839 .resume = aqr107_resume, 840 .get_sset_count = aqr107_get_sset_count, 841 .get_strings = aqr107_get_strings, 842 .get_stats = aqr107_get_stats, 843 .link_change_notify = aqr107_link_change_notify, 844 }, 845 { 846 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 847 .name = "Aquantia AQR111", 848 .probe = aqr107_probe, 849 .get_rate_matching = aqr107_get_rate_matching, 850 .config_init = aqr111_config_init, 851 .config_aneg = aqr_config_aneg, 852 .config_intr = aqr_config_intr, 853 .handle_interrupt = aqr_handle_interrupt, 854 .read_status = aqr107_read_status, 855 .get_tunable = aqr107_get_tunable, 856 .set_tunable = aqr107_set_tunable, 857 .suspend = aqr107_suspend, 858 .resume = aqr107_resume, 859 .get_sset_count = aqr107_get_sset_count, 860 .get_strings = aqr107_get_strings, 861 .get_stats = aqr107_get_stats, 862 .link_change_notify = aqr107_link_change_notify, 863 }, 864 { 865 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 866 .name = "Aquantia AQR111B0", 867 .probe = aqr107_probe, 868 .get_rate_matching = aqr107_get_rate_matching, 869 .config_init = aqr111_config_init, 870 .config_aneg = aqr_config_aneg, 871 .config_intr = aqr_config_intr, 872 .handle_interrupt = aqr_handle_interrupt, 873 .read_status = aqr107_read_status, 874 .get_tunable = aqr107_get_tunable, 875 .set_tunable = aqr107_set_tunable, 876 .suspend = aqr107_suspend, 877 .resume = aqr107_resume, 878 .get_sset_count = aqr107_get_sset_count, 879 .get_strings = aqr107_get_strings, 880 .get_stats = aqr107_get_stats, 881 .link_change_notify = aqr107_link_change_notify, 882 }, 883 { 884 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 885 .name = "Aquantia AQR405", 886 .config_aneg = aqr_config_aneg, 887 .config_intr = aqr_config_intr, 888 .handle_interrupt = aqr_handle_interrupt, 889 .read_status = aqr_read_status, 890 }, 891 { 892 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 893 .name = "Aquantia AQR112", 894 .probe = aqr107_probe, 895 .config_aneg = aqr_config_aneg, 896 .config_intr = aqr_config_intr, 897 .handle_interrupt = aqr_handle_interrupt, 898 .get_tunable = aqr107_get_tunable, 899 .set_tunable = aqr107_set_tunable, 900 .suspend = aqr107_suspend, 901 .resume = aqr107_resume, 902 .read_status = aqr107_read_status, 903 .get_rate_matching = aqr107_get_rate_matching, 904 .get_sset_count = aqr107_get_sset_count, 905 .get_strings = aqr107_get_strings, 906 .get_stats = aqr107_get_stats, 907 .link_change_notify = aqr107_link_change_notify, 908 }, 909 { 910 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 911 .name = "Aquantia AQR412", 912 .probe = aqr107_probe, 913 .config_aneg = aqr_config_aneg, 914 .config_intr = aqr_config_intr, 915 .handle_interrupt = aqr_handle_interrupt, 916 .get_tunable = aqr107_get_tunable, 917 .set_tunable = aqr107_set_tunable, 918 .suspend = aqr107_suspend, 919 .resume = aqr107_resume, 920 .read_status = aqr107_read_status, 921 .get_rate_matching = aqr107_get_rate_matching, 922 .get_sset_count = aqr107_get_sset_count, 923 .get_strings = aqr107_get_strings, 924 .get_stats = aqr107_get_stats, 925 .link_change_notify = aqr107_link_change_notify, 926 }, 927 { 928 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 929 .name = "Aquantia AQR113", 930 .probe = aqr107_probe, 931 .get_rate_matching = aqr107_get_rate_matching, 932 .config_init = aqr113c_config_init, 933 .config_aneg = aqr_config_aneg, 934 .config_intr = aqr_config_intr, 935 .handle_interrupt = aqr_handle_interrupt, 936 .read_status = aqr107_read_status, 937 .get_tunable = aqr107_get_tunable, 938 .set_tunable = aqr107_set_tunable, 939 .suspend = aqr107_suspend, 940 .resume = aqr107_resume, 941 .get_sset_count = aqr107_get_sset_count, 942 .get_strings = aqr107_get_strings, 943 .get_stats = aqr107_get_stats, 944 .link_change_notify = aqr107_link_change_notify, 945 }, 946 { 947 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 948 .name = "Aquantia AQR113C", 949 .probe = aqr107_probe, 950 .get_rate_matching = aqr107_get_rate_matching, 951 .config_init = aqr113c_config_init, 952 .config_aneg = aqr_config_aneg, 953 .config_intr = aqr_config_intr, 954 .handle_interrupt = aqr_handle_interrupt, 955 .read_status = aqr107_read_status, 956 .get_tunable = aqr107_get_tunable, 957 .set_tunable = aqr107_set_tunable, 958 .suspend = aqr107_suspend, 959 .resume = aqr107_resume, 960 .get_sset_count = aqr107_get_sset_count, 961 .get_strings = aqr107_get_strings, 962 .get_stats = aqr107_get_stats, 963 .link_change_notify = aqr107_link_change_notify, 964 }, 965 { 966 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 967 .name = "Aquantia AQR813", 968 .probe = aqr107_probe, 969 .get_rate_matching = aqr107_get_rate_matching, 970 .config_init = aqr107_config_init, 971 .config_aneg = aqr_config_aneg, 972 .config_intr = aqr_config_intr, 973 .handle_interrupt = aqr_handle_interrupt, 974 .read_status = aqr107_read_status, 975 .get_tunable = aqr107_get_tunable, 976 .set_tunable = aqr107_set_tunable, 977 .suspend = aqr107_suspend, 978 .resume = aqr107_resume, 979 .get_sset_count = aqr107_get_sset_count, 980 .get_strings = aqr107_get_strings, 981 .get_stats = aqr107_get_stats, 982 .link_change_notify = aqr107_link_change_notify, 983 }, 984 }; 985 986 module_phy_driver(aqr_driver); 987 988 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 989 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 990 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 991 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 992 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 993 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 994 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 995 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 996 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 997 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 998 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 999 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1000 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1001 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1002 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1003 { } 1004 }; 1005 1006 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1007 1008 MODULE_DESCRIPTION("Aquantia PHY driver"); 1009 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1010 MODULE_LICENSE("GPL v2"); 1011