1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 17 #include "aquantia.h" 18 19 #define PHY_ID_AQ1202 0x03a1b445 20 #define PHY_ID_AQ2104 0x03a1b460 21 #define PHY_ID_AQR105 0x03a1b4a2 22 #define PHY_ID_AQR106 0x03a1b4d0 23 #define PHY_ID_AQR107 0x03a1b4e0 24 #define PHY_ID_AQCS109 0x03a1b5c2 25 #define PHY_ID_AQR405 0x03a1b4b0 26 #define PHY_ID_AQR111 0x03a1b610 27 #define PHY_ID_AQR111B0 0x03a1b612 28 #define PHY_ID_AQR112 0x03a1b662 29 #define PHY_ID_AQR412 0x03a1b712 30 #define PHY_ID_AQR113 0x31c31c40 31 #define PHY_ID_AQR113C 0x31c31c12 32 #define PHY_ID_AQR114C 0x31c31c22 33 #define PHY_ID_AQR115C 0x31c31c33 34 #define PHY_ID_AQR813 0x31c31cb2 35 36 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 46 47 #define MDIO_AN_VEND_PROV 0xc400 48 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 49 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 50 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 51 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 52 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 53 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 54 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 55 56 #define MDIO_AN_TX_VEND_STATUS1 0xc800 57 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 58 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 59 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 60 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 61 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 62 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 63 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 64 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 65 66 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 67 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 68 69 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 70 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 71 72 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 73 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 74 75 #define PMAPMD_RSVD_VEND_PROV 0xe400 76 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) 77 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) 78 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) 79 80 #define MDIO_AN_RX_LP_STAT1 0xe820 81 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 82 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 83 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 84 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 85 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 86 87 #define MDIO_AN_RX_LP_STAT4 0xe823 88 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 89 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 90 91 #define MDIO_AN_RX_VEND_STAT3 0xe832 92 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 93 94 /* Sleep and timeout for checking if the Processor-Intensive 95 * MDIO operation is finished 96 */ 97 #define AQR107_OP_IN_PROG_SLEEP 1000 98 #define AQR107_OP_IN_PROG_TIMEOUT 100000 99 100 static int aqr107_get_sset_count(struct phy_device *phydev) 101 { 102 return AQR107_SGMII_STAT_SZ; 103 } 104 105 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 106 { 107 int i; 108 109 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 110 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 111 ETH_GSTRING_LEN); 112 } 113 114 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 115 { 116 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 117 int len_l = min(stat->size, 16); 118 int len_h = stat->size - len_l; 119 u64 ret; 120 int val; 121 122 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 123 if (val < 0) 124 return U64_MAX; 125 126 ret = val & GENMASK(len_l - 1, 0); 127 if (len_h) { 128 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 129 if (val < 0) 130 return U64_MAX; 131 132 ret += (val & GENMASK(len_h - 1, 0)) << 16; 133 } 134 135 return ret; 136 } 137 138 static void aqr107_get_stats(struct phy_device *phydev, 139 struct ethtool_stats *stats, u64 *data) 140 { 141 struct aqr107_priv *priv = phydev->priv; 142 u64 val; 143 int i; 144 145 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 146 val = aqr107_get_stat(phydev, i); 147 if (val == U64_MAX) 148 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 149 aqr107_hw_stats[i].name); 150 else 151 priv->sgmii_stats[i] += val; 152 153 data[i] = priv->sgmii_stats[i]; 154 } 155 } 156 157 static int aqr_config_aneg(struct phy_device *phydev) 158 { 159 bool changed = false; 160 u16 reg; 161 int ret; 162 163 if (phydev->autoneg == AUTONEG_DISABLE) 164 return genphy_c45_pma_setup_forced(phydev); 165 166 ret = genphy_c45_an_config_aneg(phydev); 167 if (ret < 0) 168 return ret; 169 if (ret > 0) 170 changed = true; 171 172 /* Clause 45 has no standardized support for 1000BaseT, therefore 173 * use vendor registers for this mode. 174 */ 175 reg = 0; 176 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 177 phydev->advertising)) 178 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 179 180 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 181 phydev->advertising)) 182 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 183 184 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 185 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 186 phydev->advertising)) 187 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 188 189 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 190 phydev->advertising)) 191 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 192 193 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 194 MDIO_AN_VEND_PROV_1000BASET_HALF | 195 MDIO_AN_VEND_PROV_1000BASET_FULL | 196 MDIO_AN_VEND_PROV_2500BASET_FULL | 197 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 198 if (ret < 0) 199 return ret; 200 if (ret > 0) 201 changed = true; 202 203 return genphy_c45_check_and_restart_aneg(phydev, changed); 204 } 205 206 static int aqr_config_intr(struct phy_device *phydev) 207 { 208 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 209 int err; 210 211 if (en) { 212 /* Clear any pending interrupts before enabling them */ 213 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 214 if (err < 0) 215 return err; 216 } 217 218 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 219 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 220 if (err < 0) 221 return err; 222 223 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 224 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 225 if (err < 0) 226 return err; 227 228 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 229 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 230 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 231 if (err < 0) 232 return err; 233 234 if (!en) { 235 /* Clear any pending interrupts after we have disabled them */ 236 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 237 if (err < 0) 238 return err; 239 } 240 241 return 0; 242 } 243 244 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 245 { 246 int irq_status; 247 248 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 249 MDIO_AN_TX_VEND_INT_STATUS2); 250 if (irq_status < 0) { 251 phy_error(phydev); 252 return IRQ_NONE; 253 } 254 255 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 256 return IRQ_NONE; 257 258 phy_trigger_machine(phydev); 259 260 return IRQ_HANDLED; 261 } 262 263 static int aqr_read_status(struct phy_device *phydev) 264 { 265 int val; 266 267 if (phydev->autoneg == AUTONEG_ENABLE) { 268 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 269 if (val < 0) 270 return val; 271 272 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 273 phydev->lp_advertising, 274 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 275 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 276 phydev->lp_advertising, 277 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 278 } 279 280 return genphy_c45_read_status(phydev); 281 } 282 283 static int aqr107_read_rate(struct phy_device *phydev) 284 { 285 u32 config_reg; 286 int val; 287 288 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 289 if (val < 0) 290 return val; 291 292 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 293 phydev->duplex = DUPLEX_FULL; 294 else 295 phydev->duplex = DUPLEX_HALF; 296 297 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 298 case MDIO_AN_TX_VEND_STATUS1_10BASET: 299 phydev->speed = SPEED_10; 300 config_reg = VEND1_GLOBAL_CFG_10M; 301 break; 302 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 303 phydev->speed = SPEED_100; 304 config_reg = VEND1_GLOBAL_CFG_100M; 305 break; 306 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 307 phydev->speed = SPEED_1000; 308 config_reg = VEND1_GLOBAL_CFG_1G; 309 break; 310 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 311 phydev->speed = SPEED_2500; 312 config_reg = VEND1_GLOBAL_CFG_2_5G; 313 break; 314 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 315 phydev->speed = SPEED_5000; 316 config_reg = VEND1_GLOBAL_CFG_5G; 317 break; 318 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 319 phydev->speed = SPEED_10000; 320 config_reg = VEND1_GLOBAL_CFG_10G; 321 break; 322 default: 323 phydev->speed = SPEED_UNKNOWN; 324 return 0; 325 } 326 327 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 328 if (val < 0) 329 return val; 330 331 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 332 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 333 phydev->rate_matching = RATE_MATCH_PAUSE; 334 else 335 phydev->rate_matching = RATE_MATCH_NONE; 336 337 return 0; 338 } 339 340 static int aqr107_read_status(struct phy_device *phydev) 341 { 342 int val, ret; 343 344 ret = aqr_read_status(phydev); 345 if (ret) 346 return ret; 347 348 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 349 return 0; 350 351 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 352 if (val < 0) 353 return val; 354 355 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 356 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 357 phydev->interface = PHY_INTERFACE_MODE_10GKR; 358 break; 359 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 360 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 361 break; 362 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 363 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 364 break; 365 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 366 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 367 break; 368 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 369 phydev->interface = PHY_INTERFACE_MODE_XAUI; 370 break; 371 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 372 phydev->interface = PHY_INTERFACE_MODE_SGMII; 373 break; 374 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 375 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 376 break; 377 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 378 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 379 break; 380 default: 381 phydev->interface = PHY_INTERFACE_MODE_NA; 382 break; 383 } 384 385 /* Read possibly downshifted rate from vendor register */ 386 return aqr107_read_rate(phydev); 387 } 388 389 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 390 { 391 int val, cnt, enable; 392 393 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 394 if (val < 0) 395 return val; 396 397 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 398 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 399 400 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 401 402 return 0; 403 } 404 405 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 406 { 407 int val = 0; 408 409 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 410 return -E2BIG; 411 412 if (cnt != DOWNSHIFT_DEV_DISABLE) { 413 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 414 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 415 } 416 417 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 418 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 419 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 420 } 421 422 static int aqr107_get_tunable(struct phy_device *phydev, 423 struct ethtool_tunable *tuna, void *data) 424 { 425 switch (tuna->id) { 426 case ETHTOOL_PHY_DOWNSHIFT: 427 return aqr107_get_downshift(phydev, data); 428 default: 429 return -EOPNOTSUPP; 430 } 431 } 432 433 static int aqr107_set_tunable(struct phy_device *phydev, 434 struct ethtool_tunable *tuna, const void *data) 435 { 436 switch (tuna->id) { 437 case ETHTOOL_PHY_DOWNSHIFT: 438 return aqr107_set_downshift(phydev, *(const u8 *)data); 439 default: 440 return -EOPNOTSUPP; 441 } 442 } 443 444 #define AQR_FW_WAIT_SLEEP_US 20000 445 #define AQR_FW_WAIT_TIMEOUT_US 2000000 446 447 /* If we configure settings whilst firmware is still initializing the chip, 448 * then these settings may be overwritten. Therefore make sure chip 449 * initialization has completed. Use presence of the firmware ID as 450 * indicator for initialization having completed. 451 * The chip also provides a "reset completed" bit, but it's cleared after 452 * read. Therefore function would time out if called again. 453 */ 454 int aqr_wait_reset_complete(struct phy_device *phydev) 455 { 456 int ret, val; 457 458 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 459 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 460 false, phydev, MDIO_MMD_VEND1, 461 VEND1_GLOBAL_FW_ID); 462 if (val < 0) { 463 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 464 ERR_PTR(val)); 465 return val; 466 } 467 468 return ret; 469 } 470 471 static void aqr107_chip_info(struct phy_device *phydev) 472 { 473 u8 fw_major, fw_minor, build_id, prov_id; 474 int val; 475 476 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 477 if (val < 0) 478 return; 479 480 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 481 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 482 483 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 484 if (val < 0) 485 return; 486 487 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 488 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 489 490 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 491 fw_major, fw_minor, build_id, prov_id); 492 } 493 494 static int aqr107_config_mdi(struct phy_device *phydev) 495 { 496 struct device_node *np = phydev->mdio.dev.of_node; 497 u32 mdi_conf; 498 int ret; 499 500 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); 501 502 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ 503 if (ret == -ENOENT) 504 return 0; 505 506 if (ret) 507 return ret; 508 509 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) 510 return -EINVAL; 511 512 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, 513 PMAPMD_RSVD_VEND_PROV_MDI_CONF, 514 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); 515 } 516 517 static int aqr107_config_init(struct phy_device *phydev) 518 { 519 struct aqr107_priv *priv = phydev->priv; 520 u32 led_active_low; 521 int ret; 522 523 /* Check that the PHY interface type is compatible */ 524 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 525 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 526 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 527 phydev->interface != PHY_INTERFACE_MODE_XGMII && 528 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 529 phydev->interface != PHY_INTERFACE_MODE_10GKR && 530 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 531 phydev->interface != PHY_INTERFACE_MODE_XAUI && 532 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 533 return -ENODEV; 534 535 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 536 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 537 538 ret = aqr_wait_reset_complete(phydev); 539 if (!ret) 540 aqr107_chip_info(phydev); 541 542 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 543 if (ret) 544 return ret; 545 546 ret = aqr107_config_mdi(phydev); 547 if (ret) 548 return ret; 549 550 /* Restore LED polarity state after reset */ 551 for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { 552 ret = aqr_phy_led_active_low_set(phydev, led_active_low, true); 553 if (ret) 554 return ret; 555 } 556 557 return 0; 558 } 559 560 static int aqcs109_config_init(struct phy_device *phydev) 561 { 562 int ret; 563 564 /* Check that the PHY interface type is compatible */ 565 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 566 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 567 return -ENODEV; 568 569 ret = aqr_wait_reset_complete(phydev); 570 if (!ret) 571 aqr107_chip_info(phydev); 572 573 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 574 * PMA speed ability bits are the same for all members of the family, 575 * AQCS109 however supports speeds up to 2.5G only. 576 */ 577 phy_set_max_speed(phydev, SPEED_2500); 578 579 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 580 } 581 582 static void aqr107_link_change_notify(struct phy_device *phydev) 583 { 584 u8 fw_major, fw_minor; 585 bool downshift, short_reach, afr; 586 int mode, val; 587 588 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 589 return; 590 591 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 592 /* call failed or link partner is no Aquantia PHY */ 593 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 594 return; 595 596 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 597 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 598 599 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 600 if (val < 0) 601 return; 602 603 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 604 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 605 606 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 607 if (val < 0) 608 return; 609 610 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 611 612 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 613 fw_major, fw_minor, 614 short_reach ? ", short reach mode" : "", 615 downshift ? ", fast-retrain downshift advertised" : "", 616 afr ? ", fast reframe advertised" : ""); 617 618 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 619 if (val < 0) 620 return; 621 622 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 623 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 624 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 625 } 626 627 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 628 { 629 int val, err; 630 631 /* The datasheet notes to wait at least 1ms after issuing a 632 * processor intensive operation before checking. 633 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 634 * because that just determines the maximum time slept, not the minimum. 635 */ 636 usleep_range(1000, 5000); 637 638 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 639 VEND1_GLOBAL_GEN_STAT2, val, 640 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 641 AQR107_OP_IN_PROG_SLEEP, 642 AQR107_OP_IN_PROG_TIMEOUT, false); 643 if (err) { 644 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 645 return err; 646 } 647 648 return 0; 649 } 650 651 static int aqr107_get_rate_matching(struct phy_device *phydev, 652 phy_interface_t iface) 653 { 654 if (iface == PHY_INTERFACE_MODE_10GBASER || 655 iface == PHY_INTERFACE_MODE_2500BASEX || 656 iface == PHY_INTERFACE_MODE_NA) 657 return RATE_MATCH_PAUSE; 658 return RATE_MATCH_NONE; 659 } 660 661 static int aqr107_suspend(struct phy_device *phydev) 662 { 663 int err; 664 665 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 666 MDIO_CTRL1_LPOWER); 667 if (err) 668 return err; 669 670 return aqr107_wait_processor_intensive_op(phydev); 671 } 672 673 static int aqr107_resume(struct phy_device *phydev) 674 { 675 int err; 676 677 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 678 MDIO_CTRL1_LPOWER); 679 if (err) 680 return err; 681 682 return aqr107_wait_processor_intensive_op(phydev); 683 } 684 685 static const u16 aqr_global_cfg_regs[] = { 686 VEND1_GLOBAL_CFG_10M, 687 VEND1_GLOBAL_CFG_100M, 688 VEND1_GLOBAL_CFG_1G, 689 VEND1_GLOBAL_CFG_2_5G, 690 VEND1_GLOBAL_CFG_5G, 691 VEND1_GLOBAL_CFG_10G 692 }; 693 694 static int aqr107_fill_interface_modes(struct phy_device *phydev) 695 { 696 unsigned long *possible = phydev->possible_interfaces; 697 unsigned int serdes_mode, rate_adapt; 698 phy_interface_t interface; 699 int i, val; 700 701 /* Walk the media-speed configuration registers to determine which 702 * host-side serdes modes may be used by the PHY depending on the 703 * negotiated media speed. 704 */ 705 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 706 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 707 aqr_global_cfg_regs[i]); 708 if (val < 0) 709 return val; 710 711 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 712 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 713 714 switch (serdes_mode) { 715 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 716 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 717 interface = PHY_INTERFACE_MODE_USXGMII; 718 else 719 interface = PHY_INTERFACE_MODE_10GBASER; 720 break; 721 722 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 723 interface = PHY_INTERFACE_MODE_5GBASER; 724 break; 725 726 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 727 interface = PHY_INTERFACE_MODE_2500BASEX; 728 break; 729 730 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 731 interface = PHY_INTERFACE_MODE_SGMII; 732 break; 733 734 default: 735 phydev_warn(phydev, "unrecognised serdes mode %u\n", 736 serdes_mode); 737 interface = PHY_INTERFACE_MODE_NA; 738 break; 739 } 740 741 if (interface != PHY_INTERFACE_MODE_NA) 742 __set_bit(interface, possible); 743 } 744 745 return 0; 746 } 747 748 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 749 { 750 int val, ret; 751 752 /* It's been observed on some models that - when coming out of suspend 753 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 754 * continue on returning zeroes for some time. Let's poll the 100M 755 * register until it returns a real value as both 113c and 115c support 756 * this mode. 757 */ 758 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 759 VEND1_GLOBAL_CFG_100M, val, val != 0, 760 1000, 100000, false); 761 if (ret) 762 return ret; 763 764 return aqr107_fill_interface_modes(phydev); 765 } 766 767 static int aqr113c_config_init(struct phy_device *phydev) 768 { 769 int ret; 770 771 ret = aqr107_config_init(phydev); 772 if (ret < 0) 773 return ret; 774 775 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 776 MDIO_PMD_TXDIS_GLOBAL); 777 if (ret) 778 return ret; 779 780 ret = aqr107_wait_processor_intensive_op(phydev); 781 if (ret) 782 return ret; 783 784 return aqr113c_fill_interface_modes(phydev); 785 } 786 787 static int aqr107_probe(struct phy_device *phydev) 788 { 789 int ret; 790 791 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 792 sizeof(struct aqr107_priv), GFP_KERNEL); 793 if (!phydev->priv) 794 return -ENOMEM; 795 796 ret = aqr_firmware_load(phydev); 797 if (ret) 798 return ret; 799 800 return aqr_hwmon_probe(phydev); 801 } 802 803 static int aqr111_config_init(struct phy_device *phydev) 804 { 805 /* AQR111 reports supporting speed up to 10G, 806 * however only speeds up to 5G are supported. 807 */ 808 phy_set_max_speed(phydev, SPEED_5000); 809 810 return aqr107_config_init(phydev); 811 } 812 813 static struct phy_driver aqr_driver[] = { 814 { 815 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 816 .name = "Aquantia AQ1202", 817 .config_aneg = aqr_config_aneg, 818 .config_intr = aqr_config_intr, 819 .handle_interrupt = aqr_handle_interrupt, 820 .read_status = aqr_read_status, 821 }, 822 { 823 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 824 .name = "Aquantia AQ2104", 825 .config_aneg = aqr_config_aneg, 826 .config_intr = aqr_config_intr, 827 .handle_interrupt = aqr_handle_interrupt, 828 .read_status = aqr_read_status, 829 }, 830 { 831 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 832 .name = "Aquantia AQR105", 833 .config_aneg = aqr_config_aneg, 834 .config_intr = aqr_config_intr, 835 .handle_interrupt = aqr_handle_interrupt, 836 .read_status = aqr_read_status, 837 .suspend = aqr107_suspend, 838 .resume = aqr107_resume, 839 }, 840 { 841 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 842 .name = "Aquantia AQR106", 843 .config_aneg = aqr_config_aneg, 844 .config_intr = aqr_config_intr, 845 .handle_interrupt = aqr_handle_interrupt, 846 .read_status = aqr_read_status, 847 }, 848 { 849 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 850 .name = "Aquantia AQR107", 851 .probe = aqr107_probe, 852 .get_rate_matching = aqr107_get_rate_matching, 853 .config_init = aqr107_config_init, 854 .config_aneg = aqr_config_aneg, 855 .config_intr = aqr_config_intr, 856 .handle_interrupt = aqr_handle_interrupt, 857 .read_status = aqr107_read_status, 858 .get_tunable = aqr107_get_tunable, 859 .set_tunable = aqr107_set_tunable, 860 .suspend = aqr107_suspend, 861 .resume = aqr107_resume, 862 .get_sset_count = aqr107_get_sset_count, 863 .get_strings = aqr107_get_strings, 864 .get_stats = aqr107_get_stats, 865 .link_change_notify = aqr107_link_change_notify, 866 .led_brightness_set = aqr_phy_led_brightness_set, 867 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 868 .led_hw_control_set = aqr_phy_led_hw_control_set, 869 .led_hw_control_get = aqr_phy_led_hw_control_get, 870 .led_polarity_set = aqr_phy_led_polarity_set, 871 }, 872 { 873 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 874 .name = "Aquantia AQCS109", 875 .probe = aqr107_probe, 876 .get_rate_matching = aqr107_get_rate_matching, 877 .config_init = aqcs109_config_init, 878 .config_aneg = aqr_config_aneg, 879 .config_intr = aqr_config_intr, 880 .handle_interrupt = aqr_handle_interrupt, 881 .read_status = aqr107_read_status, 882 .get_tunable = aqr107_get_tunable, 883 .set_tunable = aqr107_set_tunable, 884 .suspend = aqr107_suspend, 885 .resume = aqr107_resume, 886 .get_sset_count = aqr107_get_sset_count, 887 .get_strings = aqr107_get_strings, 888 .get_stats = aqr107_get_stats, 889 .link_change_notify = aqr107_link_change_notify, 890 .led_brightness_set = aqr_phy_led_brightness_set, 891 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 892 .led_hw_control_set = aqr_phy_led_hw_control_set, 893 .led_hw_control_get = aqr_phy_led_hw_control_get, 894 .led_polarity_set = aqr_phy_led_polarity_set, 895 }, 896 { 897 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 898 .name = "Aquantia AQR111", 899 .probe = aqr107_probe, 900 .get_rate_matching = aqr107_get_rate_matching, 901 .config_init = aqr111_config_init, 902 .config_aneg = aqr_config_aneg, 903 .config_intr = aqr_config_intr, 904 .handle_interrupt = aqr_handle_interrupt, 905 .read_status = aqr107_read_status, 906 .get_tunable = aqr107_get_tunable, 907 .set_tunable = aqr107_set_tunable, 908 .suspend = aqr107_suspend, 909 .resume = aqr107_resume, 910 .get_sset_count = aqr107_get_sset_count, 911 .get_strings = aqr107_get_strings, 912 .get_stats = aqr107_get_stats, 913 .link_change_notify = aqr107_link_change_notify, 914 .led_brightness_set = aqr_phy_led_brightness_set, 915 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 916 .led_hw_control_set = aqr_phy_led_hw_control_set, 917 .led_hw_control_get = aqr_phy_led_hw_control_get, 918 .led_polarity_set = aqr_phy_led_polarity_set, 919 }, 920 { 921 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 922 .name = "Aquantia AQR111B0", 923 .probe = aqr107_probe, 924 .get_rate_matching = aqr107_get_rate_matching, 925 .config_init = aqr111_config_init, 926 .config_aneg = aqr_config_aneg, 927 .config_intr = aqr_config_intr, 928 .handle_interrupt = aqr_handle_interrupt, 929 .read_status = aqr107_read_status, 930 .get_tunable = aqr107_get_tunable, 931 .set_tunable = aqr107_set_tunable, 932 .suspend = aqr107_suspend, 933 .resume = aqr107_resume, 934 .get_sset_count = aqr107_get_sset_count, 935 .get_strings = aqr107_get_strings, 936 .get_stats = aqr107_get_stats, 937 .link_change_notify = aqr107_link_change_notify, 938 .led_brightness_set = aqr_phy_led_brightness_set, 939 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 940 .led_hw_control_set = aqr_phy_led_hw_control_set, 941 .led_hw_control_get = aqr_phy_led_hw_control_get, 942 .led_polarity_set = aqr_phy_led_polarity_set, 943 }, 944 { 945 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 946 .name = "Aquantia AQR405", 947 .config_aneg = aqr_config_aneg, 948 .config_intr = aqr_config_intr, 949 .handle_interrupt = aqr_handle_interrupt, 950 .read_status = aqr_read_status, 951 }, 952 { 953 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 954 .name = "Aquantia AQR112", 955 .probe = aqr107_probe, 956 .config_aneg = aqr_config_aneg, 957 .config_intr = aqr_config_intr, 958 .handle_interrupt = aqr_handle_interrupt, 959 .get_tunable = aqr107_get_tunable, 960 .set_tunable = aqr107_set_tunable, 961 .suspend = aqr107_suspend, 962 .resume = aqr107_resume, 963 .read_status = aqr107_read_status, 964 .get_rate_matching = aqr107_get_rate_matching, 965 .get_sset_count = aqr107_get_sset_count, 966 .get_strings = aqr107_get_strings, 967 .get_stats = aqr107_get_stats, 968 .link_change_notify = aqr107_link_change_notify, 969 .led_brightness_set = aqr_phy_led_brightness_set, 970 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 971 .led_hw_control_set = aqr_phy_led_hw_control_set, 972 .led_hw_control_get = aqr_phy_led_hw_control_get, 973 .led_polarity_set = aqr_phy_led_polarity_set, 974 }, 975 { 976 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 977 .name = "Aquantia AQR412", 978 .probe = aqr107_probe, 979 .config_aneg = aqr_config_aneg, 980 .config_intr = aqr_config_intr, 981 .handle_interrupt = aqr_handle_interrupt, 982 .get_tunable = aqr107_get_tunable, 983 .set_tunable = aqr107_set_tunable, 984 .suspend = aqr107_suspend, 985 .resume = aqr107_resume, 986 .read_status = aqr107_read_status, 987 .get_rate_matching = aqr107_get_rate_matching, 988 .get_sset_count = aqr107_get_sset_count, 989 .get_strings = aqr107_get_strings, 990 .get_stats = aqr107_get_stats, 991 .link_change_notify = aqr107_link_change_notify, 992 }, 993 { 994 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 995 .name = "Aquantia AQR113", 996 .probe = aqr107_probe, 997 .get_rate_matching = aqr107_get_rate_matching, 998 .config_init = aqr113c_config_init, 999 .config_aneg = aqr_config_aneg, 1000 .config_intr = aqr_config_intr, 1001 .handle_interrupt = aqr_handle_interrupt, 1002 .read_status = aqr107_read_status, 1003 .get_tunable = aqr107_get_tunable, 1004 .set_tunable = aqr107_set_tunable, 1005 .suspend = aqr107_suspend, 1006 .resume = aqr107_resume, 1007 .get_sset_count = aqr107_get_sset_count, 1008 .get_strings = aqr107_get_strings, 1009 .get_stats = aqr107_get_stats, 1010 .link_change_notify = aqr107_link_change_notify, 1011 .led_brightness_set = aqr_phy_led_brightness_set, 1012 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1013 .led_hw_control_set = aqr_phy_led_hw_control_set, 1014 .led_hw_control_get = aqr_phy_led_hw_control_get, 1015 .led_polarity_set = aqr_phy_led_polarity_set, 1016 }, 1017 { 1018 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 1019 .name = "Aquantia AQR113C", 1020 .probe = aqr107_probe, 1021 .get_rate_matching = aqr107_get_rate_matching, 1022 .config_init = aqr113c_config_init, 1023 .config_aneg = aqr_config_aneg, 1024 .config_intr = aqr_config_intr, 1025 .handle_interrupt = aqr_handle_interrupt, 1026 .read_status = aqr107_read_status, 1027 .get_tunable = aqr107_get_tunable, 1028 .set_tunable = aqr107_set_tunable, 1029 .suspend = aqr107_suspend, 1030 .resume = aqr107_resume, 1031 .get_sset_count = aqr107_get_sset_count, 1032 .get_strings = aqr107_get_strings, 1033 .get_stats = aqr107_get_stats, 1034 .link_change_notify = aqr107_link_change_notify, 1035 .led_brightness_set = aqr_phy_led_brightness_set, 1036 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1037 .led_hw_control_set = aqr_phy_led_hw_control_set, 1038 .led_hw_control_get = aqr_phy_led_hw_control_get, 1039 .led_polarity_set = aqr_phy_led_polarity_set, 1040 }, 1041 { 1042 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1043 .name = "Aquantia AQR114C", 1044 .probe = aqr107_probe, 1045 .get_rate_matching = aqr107_get_rate_matching, 1046 .config_init = aqr111_config_init, 1047 .config_aneg = aqr_config_aneg, 1048 .config_intr = aqr_config_intr, 1049 .handle_interrupt = aqr_handle_interrupt, 1050 .read_status = aqr107_read_status, 1051 .get_tunable = aqr107_get_tunable, 1052 .set_tunable = aqr107_set_tunable, 1053 .suspend = aqr107_suspend, 1054 .resume = aqr107_resume, 1055 .get_sset_count = aqr107_get_sset_count, 1056 .get_strings = aqr107_get_strings, 1057 .get_stats = aqr107_get_stats, 1058 .link_change_notify = aqr107_link_change_notify, 1059 .led_brightness_set = aqr_phy_led_brightness_set, 1060 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1061 .led_hw_control_set = aqr_phy_led_hw_control_set, 1062 .led_hw_control_get = aqr_phy_led_hw_control_get, 1063 .led_polarity_set = aqr_phy_led_polarity_set, 1064 }, 1065 { 1066 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1067 .name = "Aquantia AQR115C", 1068 .probe = aqr107_probe, 1069 .get_rate_matching = aqr107_get_rate_matching, 1070 .config_init = aqr113c_config_init, 1071 .config_aneg = aqr_config_aneg, 1072 .config_intr = aqr_config_intr, 1073 .handle_interrupt = aqr_handle_interrupt, 1074 .read_status = aqr107_read_status, 1075 .get_tunable = aqr107_get_tunable, 1076 .set_tunable = aqr107_set_tunable, 1077 .suspend = aqr107_suspend, 1078 .resume = aqr107_resume, 1079 .get_sset_count = aqr107_get_sset_count, 1080 .get_strings = aqr107_get_strings, 1081 .get_stats = aqr107_get_stats, 1082 .link_change_notify = aqr107_link_change_notify, 1083 .led_brightness_set = aqr_phy_led_brightness_set, 1084 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1085 .led_hw_control_set = aqr_phy_led_hw_control_set, 1086 .led_hw_control_get = aqr_phy_led_hw_control_get, 1087 .led_polarity_set = aqr_phy_led_polarity_set, 1088 }, 1089 { 1090 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1091 .name = "Aquantia AQR813", 1092 .probe = aqr107_probe, 1093 .get_rate_matching = aqr107_get_rate_matching, 1094 .config_init = aqr107_config_init, 1095 .config_aneg = aqr_config_aneg, 1096 .config_intr = aqr_config_intr, 1097 .handle_interrupt = aqr_handle_interrupt, 1098 .read_status = aqr107_read_status, 1099 .get_tunable = aqr107_get_tunable, 1100 .set_tunable = aqr107_set_tunable, 1101 .suspend = aqr107_suspend, 1102 .resume = aqr107_resume, 1103 .get_sset_count = aqr107_get_sset_count, 1104 .get_strings = aqr107_get_strings, 1105 .get_stats = aqr107_get_stats, 1106 .link_change_notify = aqr107_link_change_notify, 1107 .led_brightness_set = aqr_phy_led_brightness_set, 1108 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1109 .led_hw_control_set = aqr_phy_led_hw_control_set, 1110 .led_hw_control_get = aqr_phy_led_hw_control_get, 1111 .led_polarity_set = aqr_phy_led_polarity_set, 1112 }, 1113 }; 1114 1115 module_phy_driver(aqr_driver); 1116 1117 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1118 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1119 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1120 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1121 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1122 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1123 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1124 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1125 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1126 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1127 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1128 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1129 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1130 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1131 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1132 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1133 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1134 { } 1135 }; 1136 1137 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1138 1139 MODULE_DESCRIPTION("Aquantia PHY driver"); 1140 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1141 MODULE_LICENSE("GPL v2"); 1142