1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR112 0x03a1b662 26 #define PHY_ID_AQR412 0x03a1b712 27 #define PHY_ID_AQR113C 0x31c31c12 28 29 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 33 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 34 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 35 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 39 40 #define MDIO_AN_VEND_PROV 0xc400 41 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 42 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 43 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 44 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 45 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 46 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 47 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 48 49 #define MDIO_AN_TX_VEND_STATUS1 0xc800 50 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 51 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 52 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 53 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 54 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 55 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 56 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 57 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 58 59 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 60 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 61 62 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 63 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 64 65 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 66 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 67 68 #define MDIO_AN_RX_LP_STAT1 0xe820 69 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 70 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 71 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 72 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 73 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 74 75 #define MDIO_AN_RX_LP_STAT4 0xe823 76 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 77 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 78 79 #define MDIO_AN_RX_VEND_STAT3 0xe832 80 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 81 82 /* MDIO_MMD_C22EXT */ 83 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 84 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 85 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 86 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 87 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 88 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 89 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 90 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 91 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 92 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 93 94 /* Sleep and timeout for checking if the Processor-Intensive 95 * MDIO operation is finished 96 */ 97 #define AQR107_OP_IN_PROG_SLEEP 1000 98 #define AQR107_OP_IN_PROG_TIMEOUT 100000 99 100 struct aqr107_hw_stat { 101 const char *name; 102 int reg; 103 int size; 104 }; 105 106 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 107 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 108 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 109 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 110 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 111 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 112 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 113 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 114 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 115 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 116 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 117 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 118 }; 119 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 120 121 struct aqr107_priv { 122 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 123 }; 124 125 static int aqr107_get_sset_count(struct phy_device *phydev) 126 { 127 return AQR107_SGMII_STAT_SZ; 128 } 129 130 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 131 { 132 int i; 133 134 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 135 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 136 ETH_GSTRING_LEN); 137 } 138 139 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 140 { 141 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 142 int len_l = min(stat->size, 16); 143 int len_h = stat->size - len_l; 144 u64 ret; 145 int val; 146 147 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 148 if (val < 0) 149 return U64_MAX; 150 151 ret = val & GENMASK(len_l - 1, 0); 152 if (len_h) { 153 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 154 if (val < 0) 155 return U64_MAX; 156 157 ret += (val & GENMASK(len_h - 1, 0)) << 16; 158 } 159 160 return ret; 161 } 162 163 static void aqr107_get_stats(struct phy_device *phydev, 164 struct ethtool_stats *stats, u64 *data) 165 { 166 struct aqr107_priv *priv = phydev->priv; 167 u64 val; 168 int i; 169 170 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 171 val = aqr107_get_stat(phydev, i); 172 if (val == U64_MAX) 173 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 174 aqr107_hw_stats[i].name); 175 else 176 priv->sgmii_stats[i] += val; 177 178 data[i] = priv->sgmii_stats[i]; 179 } 180 } 181 182 static int aqr_config_aneg(struct phy_device *phydev) 183 { 184 bool changed = false; 185 u16 reg; 186 int ret; 187 188 if (phydev->autoneg == AUTONEG_DISABLE) 189 return genphy_c45_pma_setup_forced(phydev); 190 191 ret = genphy_c45_an_config_aneg(phydev); 192 if (ret < 0) 193 return ret; 194 if (ret > 0) 195 changed = true; 196 197 /* Clause 45 has no standardized support for 1000BaseT, therefore 198 * use vendor registers for this mode. 199 */ 200 reg = 0; 201 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 202 phydev->advertising)) 203 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 204 205 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 206 phydev->advertising)) 207 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 208 209 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 210 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 211 phydev->advertising)) 212 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 213 214 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 215 phydev->advertising)) 216 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 217 218 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 219 MDIO_AN_VEND_PROV_1000BASET_HALF | 220 MDIO_AN_VEND_PROV_1000BASET_FULL | 221 MDIO_AN_VEND_PROV_2500BASET_FULL | 222 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 223 if (ret < 0) 224 return ret; 225 if (ret > 0) 226 changed = true; 227 228 return genphy_c45_check_and_restart_aneg(phydev, changed); 229 } 230 231 static int aqr_config_intr(struct phy_device *phydev) 232 { 233 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 234 int err; 235 236 if (en) { 237 /* Clear any pending interrupts before enabling them */ 238 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 239 if (err < 0) 240 return err; 241 } 242 243 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 244 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 245 if (err < 0) 246 return err; 247 248 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 249 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 250 if (err < 0) 251 return err; 252 253 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 254 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 255 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 256 if (err < 0) 257 return err; 258 259 if (!en) { 260 /* Clear any pending interrupts after we have disabled them */ 261 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 262 if (err < 0) 263 return err; 264 } 265 266 return 0; 267 } 268 269 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 270 { 271 int irq_status; 272 273 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 274 MDIO_AN_TX_VEND_INT_STATUS2); 275 if (irq_status < 0) { 276 phy_error(phydev); 277 return IRQ_NONE; 278 } 279 280 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 281 return IRQ_NONE; 282 283 phy_trigger_machine(phydev); 284 285 return IRQ_HANDLED; 286 } 287 288 static int aqr_read_status(struct phy_device *phydev) 289 { 290 int val; 291 292 if (phydev->autoneg == AUTONEG_ENABLE) { 293 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 294 if (val < 0) 295 return val; 296 297 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 298 phydev->lp_advertising, 299 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 300 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 301 phydev->lp_advertising, 302 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 303 } 304 305 return genphy_c45_read_status(phydev); 306 } 307 308 static int aqr107_read_rate(struct phy_device *phydev) 309 { 310 u32 config_reg; 311 int val; 312 313 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 314 if (val < 0) 315 return val; 316 317 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 318 phydev->duplex = DUPLEX_FULL; 319 else 320 phydev->duplex = DUPLEX_HALF; 321 322 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 323 case MDIO_AN_TX_VEND_STATUS1_10BASET: 324 phydev->speed = SPEED_10; 325 config_reg = VEND1_GLOBAL_CFG_10M; 326 break; 327 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 328 phydev->speed = SPEED_100; 329 config_reg = VEND1_GLOBAL_CFG_100M; 330 break; 331 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 332 phydev->speed = SPEED_1000; 333 config_reg = VEND1_GLOBAL_CFG_1G; 334 break; 335 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 336 phydev->speed = SPEED_2500; 337 config_reg = VEND1_GLOBAL_CFG_2_5G; 338 break; 339 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 340 phydev->speed = SPEED_5000; 341 config_reg = VEND1_GLOBAL_CFG_5G; 342 break; 343 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 344 phydev->speed = SPEED_10000; 345 config_reg = VEND1_GLOBAL_CFG_10G; 346 break; 347 default: 348 phydev->speed = SPEED_UNKNOWN; 349 return 0; 350 } 351 352 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 353 if (val < 0) 354 return val; 355 356 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 357 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 358 phydev->rate_matching = RATE_MATCH_PAUSE; 359 else 360 phydev->rate_matching = RATE_MATCH_NONE; 361 362 return 0; 363 } 364 365 static int aqr107_read_status(struct phy_device *phydev) 366 { 367 int val, ret; 368 369 ret = aqr_read_status(phydev); 370 if (ret) 371 return ret; 372 373 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 374 return 0; 375 376 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 377 if (val < 0) 378 return val; 379 380 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 381 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 382 phydev->interface = PHY_INTERFACE_MODE_10GKR; 383 break; 384 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 385 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 386 break; 387 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 388 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 389 break; 390 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 391 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 392 break; 393 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 394 phydev->interface = PHY_INTERFACE_MODE_XAUI; 395 break; 396 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 397 phydev->interface = PHY_INTERFACE_MODE_SGMII; 398 break; 399 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 400 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 401 break; 402 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 403 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 404 break; 405 default: 406 phydev->interface = PHY_INTERFACE_MODE_NA; 407 break; 408 } 409 410 /* Read possibly downshifted rate from vendor register */ 411 return aqr107_read_rate(phydev); 412 } 413 414 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 415 { 416 int val, cnt, enable; 417 418 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 419 if (val < 0) 420 return val; 421 422 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 423 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 424 425 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 426 427 return 0; 428 } 429 430 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 431 { 432 int val = 0; 433 434 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 435 return -E2BIG; 436 437 if (cnt != DOWNSHIFT_DEV_DISABLE) { 438 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 439 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 440 } 441 442 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 443 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 444 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 445 } 446 447 static int aqr107_get_tunable(struct phy_device *phydev, 448 struct ethtool_tunable *tuna, void *data) 449 { 450 switch (tuna->id) { 451 case ETHTOOL_PHY_DOWNSHIFT: 452 return aqr107_get_downshift(phydev, data); 453 default: 454 return -EOPNOTSUPP; 455 } 456 } 457 458 static int aqr107_set_tunable(struct phy_device *phydev, 459 struct ethtool_tunable *tuna, const void *data) 460 { 461 switch (tuna->id) { 462 case ETHTOOL_PHY_DOWNSHIFT: 463 return aqr107_set_downshift(phydev, *(const u8 *)data); 464 default: 465 return -EOPNOTSUPP; 466 } 467 } 468 469 /* If we configure settings whilst firmware is still initializing the chip, 470 * then these settings may be overwritten. Therefore make sure chip 471 * initialization has completed. Use presence of the firmware ID as 472 * indicator for initialization having completed. 473 * The chip also provides a "reset completed" bit, but it's cleared after 474 * read. Therefore function would time out if called again. 475 */ 476 static int aqr107_wait_reset_complete(struct phy_device *phydev) 477 { 478 int val; 479 480 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 481 VEND1_GLOBAL_FW_ID, val, val != 0, 482 20000, 2000000, false); 483 } 484 485 static void aqr107_chip_info(struct phy_device *phydev) 486 { 487 u8 fw_major, fw_minor, build_id, prov_id; 488 int val; 489 490 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 491 if (val < 0) 492 return; 493 494 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 495 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 496 497 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 498 if (val < 0) 499 return; 500 501 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 502 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 503 504 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 505 fw_major, fw_minor, build_id, prov_id); 506 } 507 508 static int aqr107_config_init(struct phy_device *phydev) 509 { 510 int ret; 511 512 /* Check that the PHY interface type is compatible */ 513 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 514 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 515 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 516 phydev->interface != PHY_INTERFACE_MODE_XGMII && 517 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 518 phydev->interface != PHY_INTERFACE_MODE_10GKR && 519 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 520 phydev->interface != PHY_INTERFACE_MODE_XAUI && 521 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 522 return -ENODEV; 523 524 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 525 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 526 527 ret = aqr107_wait_reset_complete(phydev); 528 if (!ret) 529 aqr107_chip_info(phydev); 530 531 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 532 } 533 534 static int aqcs109_config_init(struct phy_device *phydev) 535 { 536 int ret; 537 538 /* Check that the PHY interface type is compatible */ 539 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 540 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 541 return -ENODEV; 542 543 ret = aqr107_wait_reset_complete(phydev); 544 if (!ret) 545 aqr107_chip_info(phydev); 546 547 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 548 * PMA speed ability bits are the same for all members of the family, 549 * AQCS109 however supports speeds up to 2.5G only. 550 */ 551 phy_set_max_speed(phydev, SPEED_2500); 552 553 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 554 } 555 556 static void aqr107_link_change_notify(struct phy_device *phydev) 557 { 558 u8 fw_major, fw_minor; 559 bool downshift, short_reach, afr; 560 int mode, val; 561 562 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 563 return; 564 565 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 566 /* call failed or link partner is no Aquantia PHY */ 567 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 568 return; 569 570 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 571 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 572 573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 574 if (val < 0) 575 return; 576 577 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 578 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 579 580 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 581 if (val < 0) 582 return; 583 584 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 585 586 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 587 fw_major, fw_minor, 588 short_reach ? ", short reach mode" : "", 589 downshift ? ", fast-retrain downshift advertised" : "", 590 afr ? ", fast reframe advertised" : ""); 591 592 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 593 if (val < 0) 594 return; 595 596 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 597 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 598 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 599 } 600 601 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 602 { 603 int val, err; 604 605 /* The datasheet notes to wait at least 1ms after issuing a 606 * processor intensive operation before checking. 607 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 608 * because that just determines the maximum time slept, not the minimum. 609 */ 610 usleep_range(1000, 5000); 611 612 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 613 VEND1_GLOBAL_GEN_STAT2, val, 614 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 615 AQR107_OP_IN_PROG_SLEEP, 616 AQR107_OP_IN_PROG_TIMEOUT, false); 617 if (err) { 618 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 619 return err; 620 } 621 622 return 0; 623 } 624 625 static int aqr107_get_rate_matching(struct phy_device *phydev, 626 phy_interface_t iface) 627 { 628 if (iface == PHY_INTERFACE_MODE_10GBASER || 629 iface == PHY_INTERFACE_MODE_2500BASEX || 630 iface == PHY_INTERFACE_MODE_NA) 631 return RATE_MATCH_PAUSE; 632 return RATE_MATCH_NONE; 633 } 634 635 static int aqr107_suspend(struct phy_device *phydev) 636 { 637 int err; 638 639 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 640 MDIO_CTRL1_LPOWER); 641 if (err) 642 return err; 643 644 return aqr107_wait_processor_intensive_op(phydev); 645 } 646 647 static int aqr107_resume(struct phy_device *phydev) 648 { 649 int err; 650 651 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 652 MDIO_CTRL1_LPOWER); 653 if (err) 654 return err; 655 656 return aqr107_wait_processor_intensive_op(phydev); 657 } 658 659 static const u16 aqr_global_cfg_regs[] = { 660 VEND1_GLOBAL_CFG_10M, 661 VEND1_GLOBAL_CFG_100M, 662 VEND1_GLOBAL_CFG_1G, 663 VEND1_GLOBAL_CFG_2_5G, 664 VEND1_GLOBAL_CFG_5G, 665 VEND1_GLOBAL_CFG_10G 666 }; 667 668 static int aqr107_fill_interface_modes(struct phy_device *phydev) 669 { 670 unsigned long *possible = phydev->possible_interfaces; 671 unsigned int serdes_mode, rate_adapt; 672 phy_interface_t interface; 673 int i, val; 674 675 /* Walk the media-speed configuration registers to determine which 676 * host-side serdes modes may be used by the PHY depending on the 677 * negotiated media speed. 678 */ 679 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 680 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 681 aqr_global_cfg_regs[i]); 682 if (val < 0) 683 return val; 684 685 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 686 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 687 688 switch (serdes_mode) { 689 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 690 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 691 interface = PHY_INTERFACE_MODE_USXGMII; 692 else 693 interface = PHY_INTERFACE_MODE_10GBASER; 694 break; 695 696 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 697 interface = PHY_INTERFACE_MODE_5GBASER; 698 break; 699 700 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 701 interface = PHY_INTERFACE_MODE_2500BASEX; 702 break; 703 704 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 705 interface = PHY_INTERFACE_MODE_SGMII; 706 break; 707 708 default: 709 phydev_warn(phydev, "unrecognised serdes mode %u\n", 710 serdes_mode); 711 interface = PHY_INTERFACE_MODE_NA; 712 break; 713 } 714 715 if (interface != PHY_INTERFACE_MODE_NA) 716 __set_bit(interface, possible); 717 } 718 719 return 0; 720 } 721 722 static int aqr113c_config_init(struct phy_device *phydev) 723 { 724 int ret; 725 726 ret = aqr107_config_init(phydev); 727 if (ret < 0) 728 return ret; 729 730 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 731 MDIO_PMD_TXDIS_GLOBAL); 732 if (ret) 733 return ret; 734 735 ret = aqr107_wait_processor_intensive_op(phydev); 736 if (ret) 737 return ret; 738 739 return aqr107_fill_interface_modes(phydev); 740 } 741 742 static int aqr107_probe(struct phy_device *phydev) 743 { 744 int ret; 745 746 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 747 sizeof(struct aqr107_priv), GFP_KERNEL); 748 if (!phydev->priv) 749 return -ENOMEM; 750 751 ret = aqr_firmware_load(phydev); 752 if (ret) 753 return ret; 754 755 return aqr_hwmon_probe(phydev); 756 } 757 758 static struct phy_driver aqr_driver[] = { 759 { 760 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 761 .name = "Aquantia AQ1202", 762 .config_aneg = aqr_config_aneg, 763 .config_intr = aqr_config_intr, 764 .handle_interrupt = aqr_handle_interrupt, 765 .read_status = aqr_read_status, 766 }, 767 { 768 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 769 .name = "Aquantia AQ2104", 770 .config_aneg = aqr_config_aneg, 771 .config_intr = aqr_config_intr, 772 .handle_interrupt = aqr_handle_interrupt, 773 .read_status = aqr_read_status, 774 }, 775 { 776 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 777 .name = "Aquantia AQR105", 778 .config_aneg = aqr_config_aneg, 779 .config_intr = aqr_config_intr, 780 .handle_interrupt = aqr_handle_interrupt, 781 .read_status = aqr_read_status, 782 .suspend = aqr107_suspend, 783 .resume = aqr107_resume, 784 }, 785 { 786 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 787 .name = "Aquantia AQR106", 788 .config_aneg = aqr_config_aneg, 789 .config_intr = aqr_config_intr, 790 .handle_interrupt = aqr_handle_interrupt, 791 .read_status = aqr_read_status, 792 }, 793 { 794 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 795 .name = "Aquantia AQR107", 796 .probe = aqr107_probe, 797 .get_rate_matching = aqr107_get_rate_matching, 798 .config_init = aqr107_config_init, 799 .config_aneg = aqr_config_aneg, 800 .config_intr = aqr_config_intr, 801 .handle_interrupt = aqr_handle_interrupt, 802 .read_status = aqr107_read_status, 803 .get_tunable = aqr107_get_tunable, 804 .set_tunable = aqr107_set_tunable, 805 .suspend = aqr107_suspend, 806 .resume = aqr107_resume, 807 .get_sset_count = aqr107_get_sset_count, 808 .get_strings = aqr107_get_strings, 809 .get_stats = aqr107_get_stats, 810 .link_change_notify = aqr107_link_change_notify, 811 }, 812 { 813 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 814 .name = "Aquantia AQCS109", 815 .probe = aqr107_probe, 816 .get_rate_matching = aqr107_get_rate_matching, 817 .config_init = aqcs109_config_init, 818 .config_aneg = aqr_config_aneg, 819 .config_intr = aqr_config_intr, 820 .handle_interrupt = aqr_handle_interrupt, 821 .read_status = aqr107_read_status, 822 .get_tunable = aqr107_get_tunable, 823 .set_tunable = aqr107_set_tunable, 824 .suspend = aqr107_suspend, 825 .resume = aqr107_resume, 826 .get_sset_count = aqr107_get_sset_count, 827 .get_strings = aqr107_get_strings, 828 .get_stats = aqr107_get_stats, 829 .link_change_notify = aqr107_link_change_notify, 830 }, 831 { 832 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 833 .name = "Aquantia AQR405", 834 .config_aneg = aqr_config_aneg, 835 .config_intr = aqr_config_intr, 836 .handle_interrupt = aqr_handle_interrupt, 837 .read_status = aqr_read_status, 838 }, 839 { 840 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 841 .name = "Aquantia AQR112", 842 .probe = aqr107_probe, 843 .config_aneg = aqr_config_aneg, 844 .config_intr = aqr_config_intr, 845 .handle_interrupt = aqr_handle_interrupt, 846 .get_tunable = aqr107_get_tunable, 847 .set_tunable = aqr107_set_tunable, 848 .suspend = aqr107_suspend, 849 .resume = aqr107_resume, 850 .read_status = aqr107_read_status, 851 .get_rate_matching = aqr107_get_rate_matching, 852 .get_sset_count = aqr107_get_sset_count, 853 .get_strings = aqr107_get_strings, 854 .get_stats = aqr107_get_stats, 855 .link_change_notify = aqr107_link_change_notify, 856 }, 857 { 858 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 859 .name = "Aquantia AQR412", 860 .probe = aqr107_probe, 861 .config_aneg = aqr_config_aneg, 862 .config_intr = aqr_config_intr, 863 .handle_interrupt = aqr_handle_interrupt, 864 .get_tunable = aqr107_get_tunable, 865 .set_tunable = aqr107_set_tunable, 866 .suspend = aqr107_suspend, 867 .resume = aqr107_resume, 868 .read_status = aqr107_read_status, 869 .get_rate_matching = aqr107_get_rate_matching, 870 .get_sset_count = aqr107_get_sset_count, 871 .get_strings = aqr107_get_strings, 872 .get_stats = aqr107_get_stats, 873 .link_change_notify = aqr107_link_change_notify, 874 }, 875 { 876 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 877 .name = "Aquantia AQR113C", 878 .probe = aqr107_probe, 879 .get_rate_matching = aqr107_get_rate_matching, 880 .config_init = aqr113c_config_init, 881 .config_aneg = aqr_config_aneg, 882 .config_intr = aqr_config_intr, 883 .handle_interrupt = aqr_handle_interrupt, 884 .read_status = aqr107_read_status, 885 .get_tunable = aqr107_get_tunable, 886 .set_tunable = aqr107_set_tunable, 887 .suspend = aqr107_suspend, 888 .resume = aqr107_resume, 889 .get_sset_count = aqr107_get_sset_count, 890 .get_strings = aqr107_get_strings, 891 .get_stats = aqr107_get_stats, 892 .link_change_notify = aqr107_link_change_notify, 893 }, 894 }; 895 896 module_phy_driver(aqr_driver); 897 898 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 899 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 900 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 901 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 902 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 903 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 904 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 905 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 906 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 907 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 908 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 909 { } 910 }; 911 912 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 913 914 MODULE_DESCRIPTION("Aquantia PHY driver"); 915 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 916 MODULE_LICENSE("GPL v2"); 917