1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 17 #include "aquantia.h" 18 19 #define PHY_ID_AQ1202 0x03a1b445 20 #define PHY_ID_AQ2104 0x03a1b460 21 #define PHY_ID_AQR105 0x03a1b4a2 22 #define PHY_ID_AQR106 0x03a1b4d0 23 #define PHY_ID_AQR107 0x03a1b4e0 24 #define PHY_ID_AQCS109 0x03a1b5c2 25 #define PHY_ID_AQR405 0x03a1b4b0 26 #define PHY_ID_AQR111 0x03a1b610 27 #define PHY_ID_AQR111B0 0x03a1b612 28 #define PHY_ID_AQR112 0x03a1b662 29 #define PHY_ID_AQR412 0x03a1b6f2 30 #define PHY_ID_AQR412C 0x03a1b712 31 #define PHY_ID_AQR113 0x31c31c40 32 #define PHY_ID_AQR113C 0x31c31c12 33 #define PHY_ID_AQR114C 0x31c31c22 34 #define PHY_ID_AQR115 0x31c31c63 35 #define PHY_ID_AQR115C 0x31c31c33 36 #define PHY_ID_AQR813 0x31c31cb2 37 38 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 46 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 47 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9 48 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 49 50 #define MDIO_AN_VEND_PROV 0xc400 51 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 52 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 53 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 54 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 55 #define MDIO_AN_VEND_PROV_EXC_PHYID_INFO BIT(6) 56 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 57 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 58 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 59 60 #define MDIO_AN_RESVD_VEND_PROV 0xc410 61 #define MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO 0 62 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDI 1 63 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX 2 64 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK GENMASK(1, 0) 65 66 #define MDIO_AN_TX_VEND_STATUS1 0xc800 67 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 68 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 69 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 70 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 71 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 72 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 73 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 74 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 75 76 #define MDIO_AN_RESVD_VEND_STATUS1 0xc810 77 #define MDIO_AN_RESVD_VEND_STATUS1_MDIX BIT(8) 78 79 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 80 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 81 82 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 83 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 84 85 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 86 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 87 88 #define PMAPMD_RSVD_VEND_PROV 0xe400 89 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) 90 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) 91 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) 92 93 #define MDIO_AN_RX_LP_STAT1 0xe820 94 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 95 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 96 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 97 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 98 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 99 100 #define MDIO_AN_RX_LP_STAT4 0xe823 101 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 102 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 103 104 #define MDIO_AN_RX_VEND_STAT3 0xe832 105 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 106 107 /* Sleep and timeout for checking if the Processor-Intensive 108 * MDIO operation is finished 109 */ 110 #define AQR107_OP_IN_PROG_SLEEP 1000 111 #define AQR107_OP_IN_PROG_TIMEOUT 100000 112 113 static int aqr107_get_sset_count(struct phy_device *phydev) 114 { 115 return AQR107_SGMII_STAT_SZ; 116 } 117 118 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 119 { 120 int i; 121 122 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 123 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 124 ETH_GSTRING_LEN); 125 } 126 127 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 128 { 129 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 130 int len_l = min(stat->size, 16); 131 int len_h = stat->size - len_l; 132 u64 ret; 133 int val; 134 135 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 136 if (val < 0) 137 return U64_MAX; 138 139 ret = val & GENMASK(len_l - 1, 0); 140 if (len_h) { 141 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 142 if (val < 0) 143 return U64_MAX; 144 145 ret += (val & GENMASK(len_h - 1, 0)) << 16; 146 } 147 148 return ret; 149 } 150 151 static void aqr107_get_stats(struct phy_device *phydev, 152 struct ethtool_stats *stats, u64 *data) 153 { 154 struct aqr107_priv *priv = phydev->priv; 155 u64 val; 156 int i; 157 158 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 159 val = aqr107_get_stat(phydev, i); 160 if (val == U64_MAX) 161 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 162 aqr107_hw_stats[i].name); 163 else 164 priv->sgmii_stats[i] += val; 165 166 data[i] = priv->sgmii_stats[i]; 167 } 168 } 169 170 static int aqr_set_mdix(struct phy_device *phydev, int mdix) 171 { 172 u16 val = 0; 173 174 switch (mdix) { 175 case ETH_TP_MDI: 176 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDI; 177 break; 178 case ETH_TP_MDI_X: 179 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX; 180 break; 181 case ETH_TP_MDI_AUTO: 182 case ETH_TP_MDI_INVALID: 183 default: 184 val = MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO; 185 break; 186 } 187 188 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_PROV, 189 MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val); 190 } 191 192 static int aqr_config_aneg(struct phy_device *phydev) 193 { 194 bool changed = false; 195 u16 reg; 196 int ret; 197 198 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 199 if (ret < 0) 200 return ret; 201 if (ret > 0) 202 changed = true; 203 204 if (phydev->autoneg == AUTONEG_DISABLE) 205 return genphy_c45_pma_setup_forced(phydev); 206 207 ret = genphy_c45_an_config_aneg(phydev); 208 if (ret < 0) 209 return ret; 210 if (ret > 0) 211 changed = true; 212 213 /* Clause 45 has no standardized support for 1000BaseT, therefore 214 * use vendor registers for this mode. 215 */ 216 reg = 0; 217 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 218 phydev->advertising)) 219 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 220 221 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 222 phydev->advertising)) 223 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 224 225 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 226 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 227 phydev->advertising)) 228 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 229 230 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 231 phydev->advertising)) 232 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 233 234 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 235 MDIO_AN_VEND_PROV_1000BASET_HALF | 236 MDIO_AN_VEND_PROV_1000BASET_FULL | 237 MDIO_AN_VEND_PROV_2500BASET_FULL | 238 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 239 if (ret < 0) 240 return ret; 241 if (ret > 0) 242 changed = true; 243 244 return genphy_c45_check_and_restart_aneg(phydev, changed); 245 } 246 247 static int aqr_config_intr(struct phy_device *phydev) 248 { 249 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 250 int err; 251 252 if (en) { 253 /* Clear any pending interrupts before enabling them */ 254 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 255 if (err < 0) 256 return err; 257 } 258 259 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 260 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 261 if (err < 0) 262 return err; 263 264 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 265 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 266 if (err < 0) 267 return err; 268 269 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 270 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 271 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 272 if (err < 0) 273 return err; 274 275 if (!en) { 276 /* Clear any pending interrupts after we have disabled them */ 277 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 278 if (err < 0) 279 return err; 280 } 281 282 return 0; 283 } 284 285 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 286 { 287 int irq_status; 288 289 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 290 MDIO_AN_TX_VEND_INT_STATUS2); 291 if (irq_status < 0) { 292 phy_error(phydev); 293 return IRQ_NONE; 294 } 295 296 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 297 return IRQ_NONE; 298 299 phy_trigger_machine(phydev); 300 301 return IRQ_HANDLED; 302 } 303 304 static int aqr_read_status(struct phy_device *phydev) 305 { 306 int val; 307 308 if (phydev->autoneg == AUTONEG_ENABLE) { 309 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 310 if (val < 0) 311 return val; 312 313 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 314 phydev->lp_advertising, 315 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 316 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 317 phydev->lp_advertising, 318 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 319 } 320 321 val = genphy_c45_aneg_done(phydev); 322 if (val < 0) 323 return val; 324 if (val) { 325 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_STATUS1); 326 if (val < 0) 327 return val; 328 if (val & MDIO_AN_RESVD_VEND_STATUS1_MDIX) 329 phydev->mdix = ETH_TP_MDI_X; 330 else 331 phydev->mdix = ETH_TP_MDI; 332 } else { 333 phydev->mdix = ETH_TP_MDI_INVALID; 334 } 335 336 return genphy_c45_read_status(phydev); 337 } 338 339 static int aqr105_get_features(struct phy_device *phydev) 340 { 341 int ret; 342 343 /* Normal feature discovery */ 344 ret = genphy_c45_pma_read_abilities(phydev); 345 if (ret) 346 return ret; 347 348 /* The AQR105 PHY misses to indicate the 2.5G and 5G modes, so add them 349 * here 350 */ 351 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 352 phydev->supported); 353 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 354 phydev->supported); 355 356 /* The AQR105 PHY suppports both RJ45 and SFP+ interfaces */ 357 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); 358 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 359 360 return 0; 361 } 362 363 static int aqr105_setup_forced(struct phy_device *phydev) 364 { 365 int vend = MDIO_AN_VEND_PROV_EXC_PHYID_INFO; 366 int ctrl10 = 0; 367 int adv = ADVERTISE_CSMA; 368 int ret; 369 370 switch (phydev->speed) { 371 case SPEED_100: 372 adv |= ADVERTISE_100FULL; 373 break; 374 case SPEED_1000: 375 adv |= ADVERTISE_NPAGE; 376 if (phydev->duplex == DUPLEX_FULL) 377 vend |= MDIO_AN_VEND_PROV_1000BASET_FULL; 378 else 379 vend |= MDIO_AN_VEND_PROV_1000BASET_HALF; 380 break; 381 case SPEED_2500: 382 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 383 vend |= MDIO_AN_VEND_PROV_2500BASET_FULL; 384 break; 385 case SPEED_5000: 386 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 387 vend |= MDIO_AN_VEND_PROV_5000BASET_FULL; 388 break; 389 case SPEED_10000: 390 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 391 ctrl10 |= MDIO_AN_10GBT_CTRL_ADV10G; 392 break; 393 default: 394 return -EINVAL; 395 } 396 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); 397 if (ret < 0) 398 return ret; 399 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend); 400 if (ret < 0) 401 return ret; 402 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10); 403 if (ret < 0) 404 return ret; 405 406 /* set by vendor driver, but should be on by default */ 407 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 408 MDIO_AN_CTRL1_XNP); 409 if (ret < 0) 410 return ret; 411 412 return genphy_c45_an_disable_aneg(phydev); 413 } 414 415 static int aqr105_config_aneg(struct phy_device *phydev) 416 { 417 bool changed = false; 418 u16 reg; 419 int ret; 420 421 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 422 if (ret < 0) 423 return ret; 424 if (ret > 0) 425 changed = true; 426 427 if (phydev->autoneg == AUTONEG_DISABLE) 428 return aqr105_setup_forced(phydev); 429 430 ret = genphy_c45_an_config_aneg(phydev); 431 if (ret < 0) 432 return ret; 433 if (ret > 0) 434 changed = true; 435 436 /* Clause 45 has no standardized support for 1000BaseT, therefore 437 * use vendor registers for this mode. 438 */ 439 reg = 0; 440 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 441 phydev->advertising)) 442 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 443 444 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 445 phydev->advertising)) 446 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 447 448 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 449 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 450 phydev->advertising)) 451 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 452 453 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 454 phydev->advertising)) 455 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 456 457 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 458 MDIO_AN_VEND_PROV_1000BASET_HALF | 459 MDIO_AN_VEND_PROV_1000BASET_FULL | 460 MDIO_AN_VEND_PROV_2500BASET_FULL | 461 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 462 if (ret < 0) 463 return ret; 464 if (ret > 0) 465 changed = true; 466 467 return genphy_c45_check_and_restart_aneg(phydev, changed); 468 } 469 470 static int aqr_gen1_read_rate(struct phy_device *phydev) 471 { 472 int val; 473 474 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 475 if (val < 0) 476 return val; 477 478 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 479 phydev->duplex = DUPLEX_FULL; 480 else 481 phydev->duplex = DUPLEX_HALF; 482 483 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 484 case MDIO_AN_TX_VEND_STATUS1_10BASET: 485 phydev->speed = SPEED_10; 486 break; 487 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 488 phydev->speed = SPEED_100; 489 break; 490 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 491 phydev->speed = SPEED_1000; 492 break; 493 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 494 phydev->speed = SPEED_2500; 495 break; 496 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 497 phydev->speed = SPEED_5000; 498 break; 499 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 500 phydev->speed = SPEED_10000; 501 break; 502 default: 503 phydev->speed = SPEED_UNKNOWN; 504 } 505 506 return 0; 507 } 508 509 static int aqr_gen1_read_status(struct phy_device *phydev) 510 { 511 int ret; 512 int val; 513 514 ret = aqr_read_status(phydev); 515 if (ret) 516 return ret; 517 518 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 519 return 0; 520 521 /* The status register is not immediately correct on line side link up. 522 * Poll periodically until it reflects the correct ON state. 523 * Only return fail for read error, timeout defaults to OFF state. 524 */ 525 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 526 MDIO_PHYXS_VEND_IF_STATUS, val, 527 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 528 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 529 AQR107_OP_IN_PROG_SLEEP, 530 AQR107_OP_IN_PROG_TIMEOUT, false); 531 if (ret && ret != -ETIMEDOUT) 532 return ret; 533 534 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 535 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 536 phydev->interface = PHY_INTERFACE_MODE_10GKR; 537 break; 538 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 539 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 540 break; 541 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 542 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 543 break; 544 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 545 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 546 break; 547 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 548 phydev->interface = PHY_INTERFACE_MODE_XAUI; 549 break; 550 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 551 phydev->interface = PHY_INTERFACE_MODE_SGMII; 552 break; 553 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 554 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 555 break; 556 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 557 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 558 break; 559 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 560 default: 561 phydev->link = false; 562 phydev->interface = PHY_INTERFACE_MODE_NA; 563 break; 564 } 565 566 /* Read rate from vendor register */ 567 return aqr_gen1_read_rate(phydev); 568 } 569 570 static int aqr_gen2_read_status(struct phy_device *phydev) 571 { 572 struct aqr107_priv *priv = phydev->priv; 573 int i, ret; 574 575 ret = aqr_gen1_read_status(phydev); 576 if (ret) 577 return ret; 578 579 for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) { 580 struct aqr_global_syscfg *syscfg = &priv->global_cfg[i]; 581 582 if (syscfg->speed != phydev->speed) 583 continue; 584 585 if (syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE) 586 phydev->rate_matching = RATE_MATCH_PAUSE; 587 else 588 phydev->rate_matching = RATE_MATCH_NONE; 589 break; 590 } 591 592 return 0; 593 } 594 595 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 596 { 597 int val, cnt, enable; 598 599 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 600 if (val < 0) 601 return val; 602 603 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 604 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 605 606 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 607 608 return 0; 609 } 610 611 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 612 { 613 int val = 0; 614 615 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 616 return -E2BIG; 617 618 if (cnt != DOWNSHIFT_DEV_DISABLE) { 619 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 620 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 621 } 622 623 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 624 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 625 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 626 } 627 628 static int aqr107_get_tunable(struct phy_device *phydev, 629 struct ethtool_tunable *tuna, void *data) 630 { 631 switch (tuna->id) { 632 case ETHTOOL_PHY_DOWNSHIFT: 633 return aqr107_get_downshift(phydev, data); 634 default: 635 return -EOPNOTSUPP; 636 } 637 } 638 639 static int aqr107_set_tunable(struct phy_device *phydev, 640 struct ethtool_tunable *tuna, const void *data) 641 { 642 switch (tuna->id) { 643 case ETHTOOL_PHY_DOWNSHIFT: 644 return aqr107_set_downshift(phydev, *(const u8 *)data); 645 default: 646 return -EOPNOTSUPP; 647 } 648 } 649 650 #define AQR_FW_WAIT_SLEEP_US 20000 651 #define AQR_FW_WAIT_TIMEOUT_US 2000000 652 653 /* If we configure settings whilst firmware is still initializing the chip, 654 * then these settings may be overwritten. Therefore make sure chip 655 * initialization has completed. Use presence of the firmware ID as 656 * indicator for initialization having completed. 657 * The chip also provides a "reset completed" bit, but it's cleared after 658 * read. Therefore function would time out if called again. 659 */ 660 int aqr_wait_reset_complete(struct phy_device *phydev) 661 { 662 int ret, val; 663 664 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 665 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 666 false, phydev, MDIO_MMD_VEND1, 667 VEND1_GLOBAL_FW_ID); 668 if (val < 0) { 669 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 670 ERR_PTR(val)); 671 return val; 672 } 673 674 return ret; 675 } 676 677 static void aqr107_chip_info(struct phy_device *phydev) 678 { 679 u8 fw_major, fw_minor, build_id, prov_id; 680 int val; 681 682 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 683 if (val < 0) 684 return; 685 686 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 687 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 688 689 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 690 if (val < 0) 691 return; 692 693 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 694 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 695 696 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 697 fw_major, fw_minor, build_id, prov_id); 698 } 699 700 static int aqr107_config_mdi(struct phy_device *phydev) 701 { 702 struct device_node *np = phydev->mdio.dev.of_node; 703 u32 mdi_conf; 704 int ret; 705 706 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); 707 708 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ 709 if (ret == -EINVAL || ret == -ENOSYS) 710 return 0; 711 712 if (ret) 713 return ret; 714 715 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) 716 return -EINVAL; 717 718 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, 719 PMAPMD_RSVD_VEND_PROV_MDI_CONF, 720 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); 721 } 722 723 static int aqr_gen1_config_init(struct phy_device *phydev) 724 { 725 struct aqr107_priv *priv = phydev->priv; 726 u32 led_idx; 727 int ret; 728 729 /* Check that the PHY interface type is compatible */ 730 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 731 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 732 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 733 phydev->interface != PHY_INTERFACE_MODE_XGMII && 734 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 735 phydev->interface != PHY_INTERFACE_MODE_10GKR && 736 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 737 phydev->interface != PHY_INTERFACE_MODE_XAUI && 738 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 739 return -ENODEV; 740 741 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 742 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 743 744 ret = aqr_wait_reset_complete(phydev); 745 if (!ret) 746 aqr107_chip_info(phydev); 747 748 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 749 if (ret) 750 return ret; 751 752 ret = aqr107_config_mdi(phydev); 753 if (ret) 754 return ret; 755 756 /* Restore LED polarity state after reset */ 757 for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) { 758 ret = aqr_phy_led_active_low_set(phydev, led_idx, true); 759 if (ret) 760 return ret; 761 } 762 763 for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) { 764 ret = aqr_phy_led_active_low_set(phydev, led_idx, false); 765 if (ret) 766 return ret; 767 } 768 769 return 0; 770 } 771 772 /* Walk the media-speed configuration registers to determine which 773 * host-side serdes modes may be used by the PHY depending on the 774 * negotiated media speed. 775 */ 776 static int aqr_gen2_read_global_syscfg(struct phy_device *phydev) 777 { 778 struct aqr107_priv *priv = phydev->priv; 779 unsigned int serdes_mode, rate_adapt; 780 phy_interface_t interface; 781 int i, val; 782 783 for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) { 784 struct aqr_global_syscfg *syscfg = &priv->global_cfg[i]; 785 786 syscfg->speed = aqr_global_cfg_regs[i].speed; 787 788 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 789 aqr_global_cfg_regs[i].reg); 790 if (val < 0) 791 return val; 792 793 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 794 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 795 796 switch (serdes_mode) { 797 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 798 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 799 interface = PHY_INTERFACE_MODE_USXGMII; 800 else 801 interface = PHY_INTERFACE_MODE_10GBASER; 802 break; 803 804 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 805 interface = PHY_INTERFACE_MODE_5GBASER; 806 break; 807 808 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 809 interface = PHY_INTERFACE_MODE_2500BASEX; 810 break; 811 812 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 813 interface = PHY_INTERFACE_MODE_SGMII; 814 break; 815 816 default: 817 phydev_warn(phydev, "unrecognised serdes mode %u\n", 818 serdes_mode); 819 interface = PHY_INTERFACE_MODE_NA; 820 break; 821 } 822 823 syscfg->interface = interface; 824 825 switch (rate_adapt) { 826 case VEND1_GLOBAL_CFG_RATE_ADAPT_NONE: 827 syscfg->rate_adapt = AQR_RATE_ADAPT_NONE; 828 break; 829 case VEND1_GLOBAL_CFG_RATE_ADAPT_USX: 830 syscfg->rate_adapt = AQR_RATE_ADAPT_USX; 831 break; 832 case VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE: 833 syscfg->rate_adapt = AQR_RATE_ADAPT_PAUSE; 834 break; 835 default: 836 phydev_warn(phydev, "unrecognized rate adapt mode %u\n", 837 rate_adapt); 838 break; 839 } 840 } 841 842 return 0; 843 } 844 845 static int aqr_gen2_fill_interface_modes(struct phy_device *phydev) 846 { 847 unsigned long *possible = phydev->possible_interfaces; 848 struct aqr107_priv *priv = phydev->priv; 849 phy_interface_t interface; 850 int i, val, ret; 851 852 /* It's been observed on some models that - when coming out of suspend 853 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 854 * continue on returning zeroes for some time. Let's poll the 100M 855 * register until it returns a real value as both 113c and 115c support 856 * this mode. 857 */ 858 if (priv->wait_on_global_cfg) { 859 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 860 VEND1_GLOBAL_CFG_100M, val, 861 val != 0, 1000, 100000, false); 862 if (ret) 863 return ret; 864 } 865 866 ret = aqr_gen2_read_global_syscfg(phydev); 867 if (ret) 868 return ret; 869 870 for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) { 871 interface = priv->global_cfg[i].interface; 872 if (interface != PHY_INTERFACE_MODE_NA) 873 __set_bit(interface, possible); 874 } 875 876 return 0; 877 } 878 879 static int aqr_gen2_config_init(struct phy_device *phydev) 880 { 881 int ret; 882 883 ret = aqr_gen1_config_init(phydev); 884 if (ret) 885 return ret; 886 887 return aqr_gen2_fill_interface_modes(phydev); 888 } 889 890 static int aqr_gen3_config_init(struct phy_device *phydev) 891 { 892 return aqr_gen2_config_init(phydev); 893 } 894 895 static int aqcs109_config_init(struct phy_device *phydev) 896 { 897 /* Check that the PHY interface type is compatible */ 898 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 899 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 900 return -ENODEV; 901 902 return aqr_gen2_config_init(phydev); 903 } 904 905 static void aqr107_link_change_notify(struct phy_device *phydev) 906 { 907 u8 fw_major, fw_minor; 908 bool downshift, short_reach, afr; 909 int mode, val; 910 911 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 912 return; 913 914 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 915 /* call failed or link partner is no Aquantia PHY */ 916 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 917 return; 918 919 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 920 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 921 922 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 923 if (val < 0) 924 return; 925 926 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 927 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 928 929 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 930 if (val < 0) 931 return; 932 933 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 934 935 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 936 fw_major, fw_minor, 937 short_reach ? ", short reach mode" : "", 938 downshift ? ", fast-retrain downshift advertised" : "", 939 afr ? ", fast reframe advertised" : ""); 940 941 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 942 if (val < 0) 943 return; 944 945 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 946 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 947 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 948 } 949 950 static int aqr_gen1_wait_processor_intensive_op(struct phy_device *phydev) 951 { 952 int val, err; 953 954 /* The datasheet notes to wait at least 1ms after issuing a 955 * processor intensive operation before checking. 956 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 957 * because that just determines the maximum time slept, not the minimum. 958 */ 959 usleep_range(1000, 5000); 960 961 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 962 VEND1_GLOBAL_GEN_STAT2, val, 963 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 964 AQR107_OP_IN_PROG_SLEEP, 965 AQR107_OP_IN_PROG_TIMEOUT, false); 966 if (err) { 967 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 968 return err; 969 } 970 971 return 0; 972 } 973 974 static int aqr_gen2_get_rate_matching(struct phy_device *phydev, 975 phy_interface_t iface) 976 { 977 if (iface == PHY_INTERFACE_MODE_10GBASER || 978 iface == PHY_INTERFACE_MODE_2500BASEX) 979 return RATE_MATCH_PAUSE; 980 return RATE_MATCH_NONE; 981 } 982 983 static int aqr_gen1_suspend(struct phy_device *phydev) 984 { 985 int err; 986 987 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 988 MDIO_CTRL1_LPOWER); 989 if (err) 990 return err; 991 992 return aqr_gen1_wait_processor_intensive_op(phydev); 993 } 994 995 static int aqr_gen1_resume(struct phy_device *phydev) 996 { 997 int err; 998 999 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 1000 MDIO_CTRL1_LPOWER); 1001 if (err) 1002 return err; 1003 1004 return aqr_gen1_wait_processor_intensive_op(phydev); 1005 } 1006 1007 static int aqr115c_get_features(struct phy_device *phydev) 1008 { 1009 unsigned long *supported = phydev->supported; 1010 1011 /* PHY supports speeds up to 2.5G with autoneg. PMA capabilities 1012 * are not useful. 1013 */ 1014 linkmode_or(supported, supported, phy_gbit_features); 1015 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported); 1016 1017 return 0; 1018 } 1019 1020 static int aqr111_get_features(struct phy_device *phydev) 1021 { 1022 /* PHY supports speeds up to 5G with autoneg. PMA capabilities 1023 * are not useful. 1024 */ 1025 aqr115c_get_features(phydev); 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1027 phydev->supported); 1028 1029 return 0; 1030 } 1031 1032 static int aqr_gen4_config_init(struct phy_device *phydev) 1033 { 1034 struct aqr107_priv *priv = phydev->priv; 1035 int ret; 1036 1037 priv->wait_on_global_cfg = true; 1038 1039 ret = aqr_gen3_config_init(phydev); 1040 if (ret < 0) 1041 return ret; 1042 1043 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 1044 MDIO_PMD_TXDIS_GLOBAL); 1045 if (ret) 1046 return ret; 1047 1048 return aqr_gen1_wait_processor_intensive_op(phydev); 1049 } 1050 1051 static int aqr107_probe(struct phy_device *phydev) 1052 { 1053 int ret; 1054 1055 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 1056 sizeof(struct aqr107_priv), GFP_KERNEL); 1057 if (!phydev->priv) 1058 return -ENOMEM; 1059 1060 ret = aqr_firmware_load(phydev); 1061 if (ret) 1062 return ret; 1063 1064 return aqr_hwmon_probe(phydev); 1065 } 1066 1067 1068 static struct phy_driver aqr_driver[] = { 1069 { 1070 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 1071 .name = "Aquantia AQ1202", 1072 .config_aneg = aqr_config_aneg, 1073 .config_intr = aqr_config_intr, 1074 .handle_interrupt = aqr_handle_interrupt, 1075 .read_status = aqr_read_status, 1076 }, 1077 { 1078 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 1079 .name = "Aquantia AQ2104", 1080 .config_aneg = aqr_config_aneg, 1081 .config_intr = aqr_config_intr, 1082 .handle_interrupt = aqr_handle_interrupt, 1083 .read_status = aqr_read_status, 1084 }, 1085 { 1086 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 1087 .name = "Aquantia AQR105", 1088 .get_features = aqr105_get_features, 1089 .probe = aqr107_probe, 1090 .config_init = aqr_gen1_config_init, 1091 .config_aneg = aqr105_config_aneg, 1092 .config_intr = aqr_config_intr, 1093 .handle_interrupt = aqr_handle_interrupt, 1094 .read_status = aqr_gen1_read_status, 1095 .suspend = aqr_gen1_suspend, 1096 .resume = aqr_gen1_resume, 1097 }, 1098 { 1099 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 1100 .name = "Aquantia AQR106", 1101 .config_aneg = aqr_config_aneg, 1102 .config_intr = aqr_config_intr, 1103 .handle_interrupt = aqr_handle_interrupt, 1104 .read_status = aqr_read_status, 1105 }, 1106 { 1107 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 1108 .name = "Aquantia AQR107", 1109 .probe = aqr107_probe, 1110 .get_rate_matching = aqr_gen2_get_rate_matching, 1111 .config_init = aqr_gen2_config_init, 1112 .config_aneg = aqr_config_aneg, 1113 .config_intr = aqr_config_intr, 1114 .handle_interrupt = aqr_handle_interrupt, 1115 .read_status = aqr_gen2_read_status, 1116 .get_tunable = aqr107_get_tunable, 1117 .set_tunable = aqr107_set_tunable, 1118 .suspend = aqr_gen1_suspend, 1119 .resume = aqr_gen1_resume, 1120 .get_sset_count = aqr107_get_sset_count, 1121 .get_strings = aqr107_get_strings, 1122 .get_stats = aqr107_get_stats, 1123 .link_change_notify = aqr107_link_change_notify, 1124 .led_brightness_set = aqr_phy_led_brightness_set, 1125 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1126 .led_hw_control_set = aqr_phy_led_hw_control_set, 1127 .led_hw_control_get = aqr_phy_led_hw_control_get, 1128 .led_polarity_set = aqr_phy_led_polarity_set, 1129 }, 1130 { 1131 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 1132 .name = "Aquantia AQCS109", 1133 .probe = aqr107_probe, 1134 .get_rate_matching = aqr_gen2_get_rate_matching, 1135 .config_init = aqcs109_config_init, 1136 .config_aneg = aqr_config_aneg, 1137 .config_intr = aqr_config_intr, 1138 .handle_interrupt = aqr_handle_interrupt, 1139 .read_status = aqr_gen2_read_status, 1140 .get_tunable = aqr107_get_tunable, 1141 .set_tunable = aqr107_set_tunable, 1142 .suspend = aqr_gen1_suspend, 1143 .resume = aqr_gen1_resume, 1144 .get_sset_count = aqr107_get_sset_count, 1145 .get_strings = aqr107_get_strings, 1146 .get_stats = aqr107_get_stats, 1147 .get_features = aqr115c_get_features, 1148 .link_change_notify = aqr107_link_change_notify, 1149 .led_brightness_set = aqr_phy_led_brightness_set, 1150 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1151 .led_hw_control_set = aqr_phy_led_hw_control_set, 1152 .led_hw_control_get = aqr_phy_led_hw_control_get, 1153 .led_polarity_set = aqr_phy_led_polarity_set, 1154 }, 1155 { 1156 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 1157 .name = "Aquantia AQR111", 1158 .probe = aqr107_probe, 1159 .get_rate_matching = aqr_gen2_get_rate_matching, 1160 .config_init = aqr_gen3_config_init, 1161 .config_aneg = aqr_config_aneg, 1162 .config_intr = aqr_config_intr, 1163 .handle_interrupt = aqr_handle_interrupt, 1164 .read_status = aqr_gen2_read_status, 1165 .get_tunable = aqr107_get_tunable, 1166 .set_tunable = aqr107_set_tunable, 1167 .suspend = aqr_gen1_suspend, 1168 .resume = aqr_gen1_resume, 1169 .get_sset_count = aqr107_get_sset_count, 1170 .get_strings = aqr107_get_strings, 1171 .get_stats = aqr107_get_stats, 1172 .get_features = aqr111_get_features, 1173 .link_change_notify = aqr107_link_change_notify, 1174 .led_brightness_set = aqr_phy_led_brightness_set, 1175 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1176 .led_hw_control_set = aqr_phy_led_hw_control_set, 1177 .led_hw_control_get = aqr_phy_led_hw_control_get, 1178 .led_polarity_set = aqr_phy_led_polarity_set, 1179 }, 1180 { 1181 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 1182 .name = "Aquantia AQR111B0", 1183 .probe = aqr107_probe, 1184 .get_rate_matching = aqr_gen2_get_rate_matching, 1185 .config_init = aqr_gen3_config_init, 1186 .config_aneg = aqr_config_aneg, 1187 .config_intr = aqr_config_intr, 1188 .handle_interrupt = aqr_handle_interrupt, 1189 .read_status = aqr_gen2_read_status, 1190 .get_tunable = aqr107_get_tunable, 1191 .set_tunable = aqr107_set_tunable, 1192 .suspend = aqr_gen1_suspend, 1193 .resume = aqr_gen1_resume, 1194 .get_sset_count = aqr107_get_sset_count, 1195 .get_strings = aqr107_get_strings, 1196 .get_stats = aqr107_get_stats, 1197 .get_features = aqr111_get_features, 1198 .link_change_notify = aqr107_link_change_notify, 1199 .led_brightness_set = aqr_phy_led_brightness_set, 1200 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1201 .led_hw_control_set = aqr_phy_led_hw_control_set, 1202 .led_hw_control_get = aqr_phy_led_hw_control_get, 1203 .led_polarity_set = aqr_phy_led_polarity_set, 1204 }, 1205 { 1206 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 1207 .name = "Aquantia AQR405", 1208 .config_aneg = aqr_config_aneg, 1209 .config_intr = aqr_config_intr, 1210 .handle_interrupt = aqr_handle_interrupt, 1211 .read_status = aqr_read_status, 1212 }, 1213 { 1214 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 1215 .name = "Aquantia AQR112", 1216 .probe = aqr107_probe, 1217 .config_init = aqr_gen3_config_init, 1218 .config_aneg = aqr_config_aneg, 1219 .config_intr = aqr_config_intr, 1220 .handle_interrupt = aqr_handle_interrupt, 1221 .get_tunable = aqr107_get_tunable, 1222 .set_tunable = aqr107_set_tunable, 1223 .suspend = aqr_gen1_suspend, 1224 .resume = aqr_gen1_resume, 1225 .read_status = aqr_gen2_read_status, 1226 .get_rate_matching = aqr_gen2_get_rate_matching, 1227 .get_sset_count = aqr107_get_sset_count, 1228 .get_strings = aqr107_get_strings, 1229 .get_stats = aqr107_get_stats, 1230 .link_change_notify = aqr107_link_change_notify, 1231 .led_brightness_set = aqr_phy_led_brightness_set, 1232 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1233 .led_hw_control_set = aqr_phy_led_hw_control_set, 1234 .led_hw_control_get = aqr_phy_led_hw_control_get, 1235 .led_polarity_set = aqr_phy_led_polarity_set, 1236 }, 1237 { 1238 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 1239 .name = "Aquantia AQR412", 1240 .probe = aqr107_probe, 1241 .config_init = aqr_gen3_config_init, 1242 .config_aneg = aqr_config_aneg, 1243 .config_intr = aqr_config_intr, 1244 .handle_interrupt = aqr_handle_interrupt, 1245 .get_tunable = aqr107_get_tunable, 1246 .set_tunable = aqr107_set_tunable, 1247 .suspend = aqr_gen1_suspend, 1248 .resume = aqr_gen1_resume, 1249 .read_status = aqr_gen2_read_status, 1250 .get_rate_matching = aqr_gen2_get_rate_matching, 1251 .get_sset_count = aqr107_get_sset_count, 1252 .get_strings = aqr107_get_strings, 1253 .get_stats = aqr107_get_stats, 1254 .link_change_notify = aqr107_link_change_notify, 1255 }, 1256 { 1257 PHY_ID_MATCH_MODEL(PHY_ID_AQR412C), 1258 .name = "Aquantia AQR412C", 1259 .probe = aqr107_probe, 1260 .config_init = aqr_gen3_config_init, 1261 .config_aneg = aqr_config_aneg, 1262 .config_intr = aqr_config_intr, 1263 .handle_interrupt = aqr_handle_interrupt, 1264 .get_tunable = aqr107_get_tunable, 1265 .set_tunable = aqr107_set_tunable, 1266 .suspend = aqr_gen1_suspend, 1267 .resume = aqr_gen1_resume, 1268 .read_status = aqr_gen2_read_status, 1269 .get_rate_matching = aqr_gen2_get_rate_matching, 1270 .get_sset_count = aqr107_get_sset_count, 1271 .get_strings = aqr107_get_strings, 1272 .get_stats = aqr107_get_stats, 1273 .link_change_notify = aqr107_link_change_notify, 1274 }, 1275 { 1276 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 1277 .name = "Aquantia AQR113", 1278 .probe = aqr107_probe, 1279 .get_rate_matching = aqr_gen2_get_rate_matching, 1280 .config_init = aqr_gen4_config_init, 1281 .config_aneg = aqr_config_aneg, 1282 .config_intr = aqr_config_intr, 1283 .handle_interrupt = aqr_handle_interrupt, 1284 .read_status = aqr_gen2_read_status, 1285 .get_tunable = aqr107_get_tunable, 1286 .set_tunable = aqr107_set_tunable, 1287 .suspend = aqr_gen1_suspend, 1288 .resume = aqr_gen1_resume, 1289 .get_sset_count = aqr107_get_sset_count, 1290 .get_strings = aqr107_get_strings, 1291 .get_stats = aqr107_get_stats, 1292 .link_change_notify = aqr107_link_change_notify, 1293 .led_brightness_set = aqr_phy_led_brightness_set, 1294 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1295 .led_hw_control_set = aqr_phy_led_hw_control_set, 1296 .led_hw_control_get = aqr_phy_led_hw_control_get, 1297 .led_polarity_set = aqr_phy_led_polarity_set, 1298 }, 1299 { 1300 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 1301 .name = "Aquantia AQR113C", 1302 .probe = aqr107_probe, 1303 .get_rate_matching = aqr_gen2_get_rate_matching, 1304 .config_init = aqr_gen4_config_init, 1305 .config_aneg = aqr_config_aneg, 1306 .config_intr = aqr_config_intr, 1307 .handle_interrupt = aqr_handle_interrupt, 1308 .read_status = aqr_gen2_read_status, 1309 .get_tunable = aqr107_get_tunable, 1310 .set_tunable = aqr107_set_tunable, 1311 .suspend = aqr_gen1_suspend, 1312 .resume = aqr_gen1_resume, 1313 .get_sset_count = aqr107_get_sset_count, 1314 .get_strings = aqr107_get_strings, 1315 .get_stats = aqr107_get_stats, 1316 .link_change_notify = aqr107_link_change_notify, 1317 .led_brightness_set = aqr_phy_led_brightness_set, 1318 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1319 .led_hw_control_set = aqr_phy_led_hw_control_set, 1320 .led_hw_control_get = aqr_phy_led_hw_control_get, 1321 .led_polarity_set = aqr_phy_led_polarity_set, 1322 }, 1323 { 1324 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1325 .name = "Aquantia AQR114C", 1326 .probe = aqr107_probe, 1327 .get_rate_matching = aqr_gen2_get_rate_matching, 1328 .config_init = aqr_gen4_config_init, 1329 .config_aneg = aqr_config_aneg, 1330 .config_intr = aqr_config_intr, 1331 .handle_interrupt = aqr_handle_interrupt, 1332 .read_status = aqr_gen2_read_status, 1333 .get_tunable = aqr107_get_tunable, 1334 .set_tunable = aqr107_set_tunable, 1335 .suspend = aqr_gen1_suspend, 1336 .resume = aqr_gen1_resume, 1337 .get_sset_count = aqr107_get_sset_count, 1338 .get_strings = aqr107_get_strings, 1339 .get_stats = aqr107_get_stats, 1340 .get_features = aqr111_get_features, 1341 .link_change_notify = aqr107_link_change_notify, 1342 .led_brightness_set = aqr_phy_led_brightness_set, 1343 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1344 .led_hw_control_set = aqr_phy_led_hw_control_set, 1345 .led_hw_control_get = aqr_phy_led_hw_control_get, 1346 .led_polarity_set = aqr_phy_led_polarity_set, 1347 }, 1348 { 1349 PHY_ID_MATCH_MODEL(PHY_ID_AQR115), 1350 .name = "Aquantia AQR115", 1351 .probe = aqr107_probe, 1352 .get_rate_matching = aqr_gen2_get_rate_matching, 1353 .config_init = aqr_gen4_config_init, 1354 .config_aneg = aqr_config_aneg, 1355 .config_intr = aqr_config_intr, 1356 .handle_interrupt = aqr_handle_interrupt, 1357 .read_status = aqr_gen2_read_status, 1358 .get_tunable = aqr107_get_tunable, 1359 .set_tunable = aqr107_set_tunable, 1360 .suspend = aqr_gen1_suspend, 1361 .resume = aqr_gen1_resume, 1362 .get_sset_count = aqr107_get_sset_count, 1363 .get_strings = aqr107_get_strings, 1364 .get_stats = aqr107_get_stats, 1365 .get_features = aqr115c_get_features, 1366 .link_change_notify = aqr107_link_change_notify, 1367 .led_brightness_set = aqr_phy_led_brightness_set, 1368 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1369 .led_hw_control_set = aqr_phy_led_hw_control_set, 1370 .led_hw_control_get = aqr_phy_led_hw_control_get, 1371 .led_polarity_set = aqr_phy_led_polarity_set, 1372 }, 1373 { 1374 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1375 .name = "Aquantia AQR115C", 1376 .probe = aqr107_probe, 1377 .get_rate_matching = aqr_gen2_get_rate_matching, 1378 .config_init = aqr_gen4_config_init, 1379 .config_aneg = aqr_config_aneg, 1380 .config_intr = aqr_config_intr, 1381 .handle_interrupt = aqr_handle_interrupt, 1382 .read_status = aqr_gen2_read_status, 1383 .get_tunable = aqr107_get_tunable, 1384 .set_tunable = aqr107_set_tunable, 1385 .suspend = aqr_gen1_suspend, 1386 .resume = aqr_gen1_resume, 1387 .get_sset_count = aqr107_get_sset_count, 1388 .get_strings = aqr107_get_strings, 1389 .get_stats = aqr107_get_stats, 1390 .get_features = aqr115c_get_features, 1391 .link_change_notify = aqr107_link_change_notify, 1392 .led_brightness_set = aqr_phy_led_brightness_set, 1393 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1394 .led_hw_control_set = aqr_phy_led_hw_control_set, 1395 .led_hw_control_get = aqr_phy_led_hw_control_get, 1396 .led_polarity_set = aqr_phy_led_polarity_set, 1397 }, 1398 { 1399 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1400 .name = "Aquantia AQR813", 1401 .probe = aqr107_probe, 1402 .get_rate_matching = aqr_gen2_get_rate_matching, 1403 .config_init = aqr_gen4_config_init, 1404 .config_aneg = aqr_config_aneg, 1405 .config_intr = aqr_config_intr, 1406 .handle_interrupt = aqr_handle_interrupt, 1407 .read_status = aqr_gen2_read_status, 1408 .get_tunable = aqr107_get_tunable, 1409 .set_tunable = aqr107_set_tunable, 1410 .suspend = aqr_gen1_suspend, 1411 .resume = aqr_gen1_resume, 1412 .get_sset_count = aqr107_get_sset_count, 1413 .get_strings = aqr107_get_strings, 1414 .get_stats = aqr107_get_stats, 1415 .link_change_notify = aqr107_link_change_notify, 1416 .led_brightness_set = aqr_phy_led_brightness_set, 1417 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1418 .led_hw_control_set = aqr_phy_led_hw_control_set, 1419 .led_hw_control_get = aqr_phy_led_hw_control_get, 1420 .led_polarity_set = aqr_phy_led_polarity_set, 1421 }, 1422 }; 1423 1424 module_phy_driver(aqr_driver); 1425 1426 static const struct mdio_device_id __maybe_unused aqr_tbl[] = { 1427 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1428 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1429 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1430 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1431 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1432 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1433 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1434 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1435 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1436 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1437 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1438 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412C) }, 1439 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1440 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1441 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1442 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115) }, 1443 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1444 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1445 { } 1446 }; 1447 1448 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1449 1450 MODULE_DESCRIPTION("Aquantia PHY driver"); 1451 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1452 MODULE_LICENSE("GPL v2"); 1453