1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/of.h> 15 #include <linux/phy.h> 16 17 #include "aquantia.h" 18 19 #define PHY_ID_AQ1202 0x03a1b445 20 #define PHY_ID_AQ2104 0x03a1b460 21 #define PHY_ID_AQR105 0x03a1b4a2 22 #define PHY_ID_AQR106 0x03a1b4d0 23 #define PHY_ID_AQR107 0x03a1b4e0 24 #define PHY_ID_AQCS109 0x03a1b5c2 25 #define PHY_ID_AQR405 0x03a1b4b0 26 #define PHY_ID_AQR111 0x03a1b610 27 #define PHY_ID_AQR111B0 0x03a1b612 28 #define PHY_ID_AQR112 0x03a1b662 29 #define PHY_ID_AQR412 0x03a1b712 30 #define PHY_ID_AQR113 0x31c31c40 31 #define PHY_ID_AQR113C 0x31c31c12 32 #define PHY_ID_AQR114C 0x31c31c22 33 #define PHY_ID_AQR115C 0x31c31c33 34 #define PHY_ID_AQR813 0x31c31cb2 35 36 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 37 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 39 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 40 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 41 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9 46 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 47 48 #define MDIO_AN_VEND_PROV 0xc400 49 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 50 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 51 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 52 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 53 #define MDIO_AN_VEND_PROV_EXC_PHYID_INFO BIT(6) 54 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 55 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 56 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 57 58 #define MDIO_AN_RESVD_VEND_PROV 0xc410 59 #define MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO 0 60 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDI 1 61 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX 2 62 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK GENMASK(1, 0) 63 64 #define MDIO_AN_TX_VEND_STATUS1 0xc800 65 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 66 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 67 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 68 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 69 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 70 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 71 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 72 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 73 74 #define MDIO_AN_RESVD_VEND_STATUS1 0xc810 75 #define MDIO_AN_RESVD_VEND_STATUS1_MDIX BIT(8) 76 77 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 78 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 79 80 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 81 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 82 83 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 84 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 85 86 #define PMAPMD_RSVD_VEND_PROV 0xe400 87 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) 88 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0) 89 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1) 90 91 #define MDIO_AN_RX_LP_STAT1 0xe820 92 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 93 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 94 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 95 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 96 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 97 98 #define MDIO_AN_RX_LP_STAT4 0xe823 99 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 100 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 101 102 #define MDIO_AN_RX_VEND_STAT3 0xe832 103 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 104 105 /* Sleep and timeout for checking if the Processor-Intensive 106 * MDIO operation is finished 107 */ 108 #define AQR107_OP_IN_PROG_SLEEP 1000 109 #define AQR107_OP_IN_PROG_TIMEOUT 100000 110 111 static int aqr107_get_sset_count(struct phy_device *phydev) 112 { 113 return AQR107_SGMII_STAT_SZ; 114 } 115 116 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 117 { 118 int i; 119 120 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 121 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 122 ETH_GSTRING_LEN); 123 } 124 125 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 126 { 127 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 128 int len_l = min(stat->size, 16); 129 int len_h = stat->size - len_l; 130 u64 ret; 131 int val; 132 133 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 134 if (val < 0) 135 return U64_MAX; 136 137 ret = val & GENMASK(len_l - 1, 0); 138 if (len_h) { 139 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 140 if (val < 0) 141 return U64_MAX; 142 143 ret += (val & GENMASK(len_h - 1, 0)) << 16; 144 } 145 146 return ret; 147 } 148 149 static void aqr107_get_stats(struct phy_device *phydev, 150 struct ethtool_stats *stats, u64 *data) 151 { 152 struct aqr107_priv *priv = phydev->priv; 153 u64 val; 154 int i; 155 156 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 157 val = aqr107_get_stat(phydev, i); 158 if (val == U64_MAX) 159 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 160 aqr107_hw_stats[i].name); 161 else 162 priv->sgmii_stats[i] += val; 163 164 data[i] = priv->sgmii_stats[i]; 165 } 166 } 167 168 static int aqr_set_mdix(struct phy_device *phydev, int mdix) 169 { 170 u16 val = 0; 171 172 switch (mdix) { 173 case ETH_TP_MDI: 174 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDI; 175 break; 176 case ETH_TP_MDI_X: 177 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX; 178 break; 179 case ETH_TP_MDI_AUTO: 180 case ETH_TP_MDI_INVALID: 181 default: 182 val = MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO; 183 break; 184 } 185 186 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_PROV, 187 MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val); 188 } 189 190 static int aqr_config_aneg(struct phy_device *phydev) 191 { 192 bool changed = false; 193 u16 reg; 194 int ret; 195 196 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 197 if (ret < 0) 198 return ret; 199 if (ret > 0) 200 changed = true; 201 202 if (phydev->autoneg == AUTONEG_DISABLE) 203 return genphy_c45_pma_setup_forced(phydev); 204 205 ret = genphy_c45_an_config_aneg(phydev); 206 if (ret < 0) 207 return ret; 208 if (ret > 0) 209 changed = true; 210 211 /* Clause 45 has no standardized support for 1000BaseT, therefore 212 * use vendor registers for this mode. 213 */ 214 reg = 0; 215 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 216 phydev->advertising)) 217 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 218 219 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 220 phydev->advertising)) 221 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 222 223 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 224 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 225 phydev->advertising)) 226 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 227 228 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 229 phydev->advertising)) 230 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 231 232 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 233 MDIO_AN_VEND_PROV_1000BASET_HALF | 234 MDIO_AN_VEND_PROV_1000BASET_FULL | 235 MDIO_AN_VEND_PROV_2500BASET_FULL | 236 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 237 if (ret < 0) 238 return ret; 239 if (ret > 0) 240 changed = true; 241 242 return genphy_c45_check_and_restart_aneg(phydev, changed); 243 } 244 245 static int aqr_config_intr(struct phy_device *phydev) 246 { 247 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 248 int err; 249 250 if (en) { 251 /* Clear any pending interrupts before enabling them */ 252 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 253 if (err < 0) 254 return err; 255 } 256 257 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 258 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 259 if (err < 0) 260 return err; 261 262 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 263 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 264 if (err < 0) 265 return err; 266 267 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 268 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 269 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 270 if (err < 0) 271 return err; 272 273 if (!en) { 274 /* Clear any pending interrupts after we have disabled them */ 275 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 276 if (err < 0) 277 return err; 278 } 279 280 return 0; 281 } 282 283 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 284 { 285 int irq_status; 286 287 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 288 MDIO_AN_TX_VEND_INT_STATUS2); 289 if (irq_status < 0) { 290 phy_error(phydev); 291 return IRQ_NONE; 292 } 293 294 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 295 return IRQ_NONE; 296 297 phy_trigger_machine(phydev); 298 299 return IRQ_HANDLED; 300 } 301 302 static int aqr_read_status(struct phy_device *phydev) 303 { 304 int val; 305 306 if (phydev->autoneg == AUTONEG_ENABLE) { 307 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 308 if (val < 0) 309 return val; 310 311 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 312 phydev->lp_advertising, 313 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 314 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 315 phydev->lp_advertising, 316 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 317 } 318 319 val = genphy_c45_aneg_done(phydev); 320 if (val < 0) 321 return val; 322 if (val) { 323 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_STATUS1); 324 if (val < 0) 325 return val; 326 if (val & MDIO_AN_RESVD_VEND_STATUS1_MDIX) 327 phydev->mdix = ETH_TP_MDI_X; 328 else 329 phydev->mdix = ETH_TP_MDI; 330 } else { 331 phydev->mdix = ETH_TP_MDI_INVALID; 332 } 333 334 return genphy_c45_read_status(phydev); 335 } 336 337 static int aqr105_get_features(struct phy_device *phydev) 338 { 339 int ret; 340 341 /* Normal feature discovery */ 342 ret = genphy_c45_pma_read_abilities(phydev); 343 if (ret) 344 return ret; 345 346 /* The AQR105 PHY misses to indicate the 2.5G and 5G modes, so add them 347 * here 348 */ 349 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 350 phydev->supported); 351 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 352 phydev->supported); 353 354 /* The AQR105 PHY suppports both RJ45 and SFP+ interfaces */ 355 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); 356 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 357 358 return 0; 359 } 360 361 static int aqr105_setup_forced(struct phy_device *phydev) 362 { 363 int vend = MDIO_AN_VEND_PROV_EXC_PHYID_INFO; 364 int ctrl10 = 0; 365 int adv = ADVERTISE_CSMA; 366 int ret; 367 368 switch (phydev->speed) { 369 case SPEED_100: 370 adv |= ADVERTISE_100FULL; 371 break; 372 case SPEED_1000: 373 adv |= ADVERTISE_NPAGE; 374 if (phydev->duplex == DUPLEX_FULL) 375 vend |= MDIO_AN_VEND_PROV_1000BASET_FULL; 376 else 377 vend |= MDIO_AN_VEND_PROV_1000BASET_HALF; 378 break; 379 case SPEED_2500: 380 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 381 vend |= MDIO_AN_VEND_PROV_2500BASET_FULL; 382 break; 383 case SPEED_5000: 384 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 385 vend |= MDIO_AN_VEND_PROV_5000BASET_FULL; 386 break; 387 case SPEED_10000: 388 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV); 389 ctrl10 |= MDIO_AN_10GBT_CTRL_ADV10G; 390 break; 391 default: 392 return -EINVAL; 393 } 394 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); 395 if (ret < 0) 396 return ret; 397 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend); 398 if (ret < 0) 399 return ret; 400 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10); 401 if (ret < 0) 402 return ret; 403 404 /* set by vendor driver, but should be on by default */ 405 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 406 MDIO_AN_CTRL1_XNP); 407 if (ret < 0) 408 return ret; 409 410 return genphy_c45_an_disable_aneg(phydev); 411 } 412 413 static int aqr105_config_aneg(struct phy_device *phydev) 414 { 415 bool changed = false; 416 u16 reg; 417 int ret; 418 419 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl); 420 if (ret < 0) 421 return ret; 422 if (ret > 0) 423 changed = true; 424 425 if (phydev->autoneg == AUTONEG_DISABLE) 426 return aqr105_setup_forced(phydev); 427 428 ret = genphy_c45_an_config_aneg(phydev); 429 if (ret < 0) 430 return ret; 431 if (ret > 0) 432 changed = true; 433 434 /* Clause 45 has no standardized support for 1000BaseT, therefore 435 * use vendor registers for this mode. 436 */ 437 reg = 0; 438 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 439 phydev->advertising)) 440 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 441 442 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 443 phydev->advertising)) 444 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 445 446 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 447 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 448 phydev->advertising)) 449 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 450 451 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 452 phydev->advertising)) 453 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 454 455 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 456 MDIO_AN_VEND_PROV_1000BASET_HALF | 457 MDIO_AN_VEND_PROV_1000BASET_FULL | 458 MDIO_AN_VEND_PROV_2500BASET_FULL | 459 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 460 if (ret < 0) 461 return ret; 462 if (ret > 0) 463 changed = true; 464 465 return genphy_c45_check_and_restart_aneg(phydev, changed); 466 } 467 468 static int aqr105_read_rate(struct phy_device *phydev) 469 { 470 int val; 471 472 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 473 if (val < 0) 474 return val; 475 476 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 477 phydev->duplex = DUPLEX_FULL; 478 else 479 phydev->duplex = DUPLEX_HALF; 480 481 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 482 case MDIO_AN_TX_VEND_STATUS1_10BASET: 483 phydev->speed = SPEED_10; 484 break; 485 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 486 phydev->speed = SPEED_100; 487 break; 488 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 489 phydev->speed = SPEED_1000; 490 break; 491 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 492 phydev->speed = SPEED_2500; 493 break; 494 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 495 phydev->speed = SPEED_5000; 496 break; 497 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 498 phydev->speed = SPEED_10000; 499 break; 500 default: 501 phydev->speed = SPEED_UNKNOWN; 502 } 503 504 return 0; 505 } 506 507 static int aqr105_read_status(struct phy_device *phydev) 508 { 509 int ret; 510 int val; 511 512 ret = aqr_read_status(phydev); 513 if (ret) 514 return ret; 515 516 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 517 return 0; 518 519 /** 520 * The status register is not immediately correct on line side link up. 521 * Poll periodically until it reflects the correct ON state. 522 * Only return fail for read error, timeout defaults to OFF state. 523 */ 524 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 525 MDIO_PHYXS_VEND_IF_STATUS, val, 526 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 527 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 528 AQR107_OP_IN_PROG_SLEEP, 529 AQR107_OP_IN_PROG_TIMEOUT, false); 530 if (ret && ret != -ETIMEDOUT) 531 return ret; 532 533 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 534 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 535 phydev->interface = PHY_INTERFACE_MODE_10GKR; 536 break; 537 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 538 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 539 break; 540 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 541 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 542 break; 543 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 544 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 545 break; 546 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 547 phydev->interface = PHY_INTERFACE_MODE_XAUI; 548 break; 549 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 550 phydev->interface = PHY_INTERFACE_MODE_SGMII; 551 break; 552 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 553 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 554 break; 555 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 556 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 557 break; 558 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 559 default: 560 phydev->link = false; 561 phydev->interface = PHY_INTERFACE_MODE_NA; 562 break; 563 } 564 565 /* Read rate from vendor register */ 566 return aqr105_read_rate(phydev); 567 } 568 569 static int aqr107_read_rate(struct phy_device *phydev) 570 { 571 u32 config_reg; 572 int val; 573 574 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 575 if (val < 0) 576 return val; 577 578 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 579 phydev->duplex = DUPLEX_FULL; 580 else 581 phydev->duplex = DUPLEX_HALF; 582 583 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 584 case MDIO_AN_TX_VEND_STATUS1_10BASET: 585 phydev->speed = SPEED_10; 586 config_reg = VEND1_GLOBAL_CFG_10M; 587 break; 588 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 589 phydev->speed = SPEED_100; 590 config_reg = VEND1_GLOBAL_CFG_100M; 591 break; 592 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 593 phydev->speed = SPEED_1000; 594 config_reg = VEND1_GLOBAL_CFG_1G; 595 break; 596 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 597 phydev->speed = SPEED_2500; 598 config_reg = VEND1_GLOBAL_CFG_2_5G; 599 break; 600 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 601 phydev->speed = SPEED_5000; 602 config_reg = VEND1_GLOBAL_CFG_5G; 603 break; 604 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 605 phydev->speed = SPEED_10000; 606 config_reg = VEND1_GLOBAL_CFG_10G; 607 break; 608 default: 609 phydev->speed = SPEED_UNKNOWN; 610 return 0; 611 } 612 613 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 614 if (val < 0) 615 return val; 616 617 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 618 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 619 phydev->rate_matching = RATE_MATCH_PAUSE; 620 else 621 phydev->rate_matching = RATE_MATCH_NONE; 622 623 return 0; 624 } 625 626 static int aqr107_read_status(struct phy_device *phydev) 627 { 628 int val, ret; 629 630 ret = aqr_read_status(phydev); 631 if (ret) 632 return ret; 633 634 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 635 return 0; 636 637 /** 638 * The status register is not immediately correct on line side link up. 639 * Poll periodically until it reflects the correct ON state. 640 * Only return fail for read error, timeout defaults to OFF state. 641 */ 642 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS, 643 MDIO_PHYXS_VEND_IF_STATUS, val, 644 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) != 645 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF), 646 AQR107_OP_IN_PROG_SLEEP, 647 AQR107_OP_IN_PROG_TIMEOUT, false); 648 if (ret && ret != -ETIMEDOUT) 649 return ret; 650 651 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 652 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 653 phydev->interface = PHY_INTERFACE_MODE_10GKR; 654 break; 655 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 656 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 657 break; 658 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 659 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 660 break; 661 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 662 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 663 break; 664 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 665 phydev->interface = PHY_INTERFACE_MODE_XAUI; 666 break; 667 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 668 phydev->interface = PHY_INTERFACE_MODE_SGMII; 669 break; 670 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 671 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 672 break; 673 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 674 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 675 break; 676 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 677 default: 678 phydev->link = false; 679 phydev->interface = PHY_INTERFACE_MODE_NA; 680 break; 681 } 682 683 /* Read possibly downshifted rate from vendor register */ 684 return aqr107_read_rate(phydev); 685 } 686 687 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 688 { 689 int val, cnt, enable; 690 691 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 692 if (val < 0) 693 return val; 694 695 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 696 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 697 698 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 699 700 return 0; 701 } 702 703 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 704 { 705 int val = 0; 706 707 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 708 return -E2BIG; 709 710 if (cnt != DOWNSHIFT_DEV_DISABLE) { 711 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 712 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 713 } 714 715 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 716 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 717 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 718 } 719 720 static int aqr107_get_tunable(struct phy_device *phydev, 721 struct ethtool_tunable *tuna, void *data) 722 { 723 switch (tuna->id) { 724 case ETHTOOL_PHY_DOWNSHIFT: 725 return aqr107_get_downshift(phydev, data); 726 default: 727 return -EOPNOTSUPP; 728 } 729 } 730 731 static int aqr107_set_tunable(struct phy_device *phydev, 732 struct ethtool_tunable *tuna, const void *data) 733 { 734 switch (tuna->id) { 735 case ETHTOOL_PHY_DOWNSHIFT: 736 return aqr107_set_downshift(phydev, *(const u8 *)data); 737 default: 738 return -EOPNOTSUPP; 739 } 740 } 741 742 #define AQR_FW_WAIT_SLEEP_US 20000 743 #define AQR_FW_WAIT_TIMEOUT_US 2000000 744 745 /* If we configure settings whilst firmware is still initializing the chip, 746 * then these settings may be overwritten. Therefore make sure chip 747 * initialization has completed. Use presence of the firmware ID as 748 * indicator for initialization having completed. 749 * The chip also provides a "reset completed" bit, but it's cleared after 750 * read. Therefore function would time out if called again. 751 */ 752 int aqr_wait_reset_complete(struct phy_device *phydev) 753 { 754 int ret, val; 755 756 ret = read_poll_timeout(phy_read_mmd, val, val != 0, 757 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US, 758 false, phydev, MDIO_MMD_VEND1, 759 VEND1_GLOBAL_FW_ID); 760 if (val < 0) { 761 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", 762 ERR_PTR(val)); 763 return val; 764 } 765 766 return ret; 767 } 768 769 static void aqr107_chip_info(struct phy_device *phydev) 770 { 771 u8 fw_major, fw_minor, build_id, prov_id; 772 int val; 773 774 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 775 if (val < 0) 776 return; 777 778 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 779 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 780 781 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 782 if (val < 0) 783 return; 784 785 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 786 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 787 788 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 789 fw_major, fw_minor, build_id, prov_id); 790 } 791 792 static int aqr107_config_mdi(struct phy_device *phydev) 793 { 794 struct device_node *np = phydev->mdio.dev.of_node; 795 u32 mdi_conf; 796 int ret; 797 798 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); 799 800 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ 801 if (ret == -EINVAL || ret == -ENOSYS) 802 return 0; 803 804 if (ret) 805 return ret; 806 807 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE) 808 return -EINVAL; 809 810 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV, 811 PMAPMD_RSVD_VEND_PROV_MDI_CONF, 812 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE); 813 } 814 815 static int aqr107_config_init(struct phy_device *phydev) 816 { 817 struct aqr107_priv *priv = phydev->priv; 818 u32 led_idx; 819 int ret; 820 821 /* Check that the PHY interface type is compatible */ 822 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 823 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 824 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 825 phydev->interface != PHY_INTERFACE_MODE_XGMII && 826 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 827 phydev->interface != PHY_INTERFACE_MODE_10GKR && 828 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 829 phydev->interface != PHY_INTERFACE_MODE_XAUI && 830 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 831 return -ENODEV; 832 833 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 834 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 835 836 ret = aqr_wait_reset_complete(phydev); 837 if (!ret) 838 aqr107_chip_info(phydev); 839 840 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 841 if (ret) 842 return ret; 843 844 ret = aqr107_config_mdi(phydev); 845 if (ret) 846 return ret; 847 848 /* Restore LED polarity state after reset */ 849 for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) { 850 ret = aqr_phy_led_active_low_set(phydev, led_idx, true); 851 if (ret) 852 return ret; 853 } 854 855 for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) { 856 ret = aqr_phy_led_active_low_set(phydev, led_idx, false); 857 if (ret) 858 return ret; 859 } 860 861 return 0; 862 } 863 864 static int aqcs109_config_init(struct phy_device *phydev) 865 { 866 int ret; 867 868 /* Check that the PHY interface type is compatible */ 869 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 870 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 871 return -ENODEV; 872 873 ret = aqr_wait_reset_complete(phydev); 874 if (!ret) 875 aqr107_chip_info(phydev); 876 877 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 878 } 879 880 static void aqr107_link_change_notify(struct phy_device *phydev) 881 { 882 u8 fw_major, fw_minor; 883 bool downshift, short_reach, afr; 884 int mode, val; 885 886 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 887 return; 888 889 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 890 /* call failed or link partner is no Aquantia PHY */ 891 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 892 return; 893 894 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 895 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 896 897 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 898 if (val < 0) 899 return; 900 901 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 902 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 903 904 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 905 if (val < 0) 906 return; 907 908 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 909 910 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 911 fw_major, fw_minor, 912 short_reach ? ", short reach mode" : "", 913 downshift ? ", fast-retrain downshift advertised" : "", 914 afr ? ", fast reframe advertised" : ""); 915 916 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 917 if (val < 0) 918 return; 919 920 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 921 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 922 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 923 } 924 925 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 926 { 927 int val, err; 928 929 /* The datasheet notes to wait at least 1ms after issuing a 930 * processor intensive operation before checking. 931 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 932 * because that just determines the maximum time slept, not the minimum. 933 */ 934 usleep_range(1000, 5000); 935 936 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 937 VEND1_GLOBAL_GEN_STAT2, val, 938 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 939 AQR107_OP_IN_PROG_SLEEP, 940 AQR107_OP_IN_PROG_TIMEOUT, false); 941 if (err) { 942 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 943 return err; 944 } 945 946 return 0; 947 } 948 949 static int aqr107_get_rate_matching(struct phy_device *phydev, 950 phy_interface_t iface) 951 { 952 if (iface == PHY_INTERFACE_MODE_10GBASER || 953 iface == PHY_INTERFACE_MODE_2500BASEX || 954 iface == PHY_INTERFACE_MODE_NA) 955 return RATE_MATCH_PAUSE; 956 return RATE_MATCH_NONE; 957 } 958 959 static int aqr107_suspend(struct phy_device *phydev) 960 { 961 int err; 962 963 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 964 MDIO_CTRL1_LPOWER); 965 if (err) 966 return err; 967 968 return aqr107_wait_processor_intensive_op(phydev); 969 } 970 971 static int aqr107_resume(struct phy_device *phydev) 972 { 973 int err; 974 975 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 976 MDIO_CTRL1_LPOWER); 977 if (err) 978 return err; 979 980 return aqr107_wait_processor_intensive_op(phydev); 981 } 982 983 static const u16 aqr_global_cfg_regs[] = { 984 VEND1_GLOBAL_CFG_10M, 985 VEND1_GLOBAL_CFG_100M, 986 VEND1_GLOBAL_CFG_1G, 987 VEND1_GLOBAL_CFG_2_5G, 988 VEND1_GLOBAL_CFG_5G, 989 VEND1_GLOBAL_CFG_10G 990 }; 991 992 static int aqr107_fill_interface_modes(struct phy_device *phydev) 993 { 994 unsigned long *possible = phydev->possible_interfaces; 995 unsigned int serdes_mode, rate_adapt; 996 phy_interface_t interface; 997 int i, val; 998 999 /* Walk the media-speed configuration registers to determine which 1000 * host-side serdes modes may be used by the PHY depending on the 1001 * negotiated media speed. 1002 */ 1003 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 1004 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1005 aqr_global_cfg_regs[i]); 1006 if (val < 0) 1007 return val; 1008 1009 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 1010 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 1011 1012 switch (serdes_mode) { 1013 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 1014 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 1015 interface = PHY_INTERFACE_MODE_USXGMII; 1016 else 1017 interface = PHY_INTERFACE_MODE_10GBASER; 1018 break; 1019 1020 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 1021 interface = PHY_INTERFACE_MODE_5GBASER; 1022 break; 1023 1024 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 1025 interface = PHY_INTERFACE_MODE_2500BASEX; 1026 break; 1027 1028 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 1029 interface = PHY_INTERFACE_MODE_SGMII; 1030 break; 1031 1032 default: 1033 phydev_warn(phydev, "unrecognised serdes mode %u\n", 1034 serdes_mode); 1035 interface = PHY_INTERFACE_MODE_NA; 1036 break; 1037 } 1038 1039 if (interface != PHY_INTERFACE_MODE_NA) 1040 __set_bit(interface, possible); 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int aqr113c_fill_interface_modes(struct phy_device *phydev) 1047 { 1048 int val, ret; 1049 1050 /* It's been observed on some models that - when coming out of suspend 1051 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers 1052 * continue on returning zeroes for some time. Let's poll the 100M 1053 * register until it returns a real value as both 113c and 115c support 1054 * this mode. 1055 */ 1056 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 1057 VEND1_GLOBAL_CFG_100M, val, val != 0, 1058 1000, 100000, false); 1059 if (ret) 1060 return ret; 1061 1062 return aqr107_fill_interface_modes(phydev); 1063 } 1064 1065 static int aqr115c_get_features(struct phy_device *phydev) 1066 { 1067 unsigned long *supported = phydev->supported; 1068 1069 /* PHY supports speeds up to 2.5G with autoneg. PMA capabilities 1070 * are not useful. 1071 */ 1072 linkmode_or(supported, supported, phy_gbit_features); 1073 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported); 1074 1075 return 0; 1076 } 1077 1078 static int aqr111_get_features(struct phy_device *phydev) 1079 { 1080 /* PHY supports speeds up to 5G with autoneg. PMA capabilities 1081 * are not useful. 1082 */ 1083 aqr115c_get_features(phydev); 1084 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 1085 phydev->supported); 1086 1087 return 0; 1088 } 1089 1090 static int aqr113c_config_init(struct phy_device *phydev) 1091 { 1092 int ret; 1093 1094 ret = aqr107_config_init(phydev); 1095 if (ret < 0) 1096 return ret; 1097 1098 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 1099 MDIO_PMD_TXDIS_GLOBAL); 1100 if (ret) 1101 return ret; 1102 1103 ret = aqr107_wait_processor_intensive_op(phydev); 1104 if (ret) 1105 return ret; 1106 1107 return aqr113c_fill_interface_modes(phydev); 1108 } 1109 1110 static int aqr107_probe(struct phy_device *phydev) 1111 { 1112 int ret; 1113 1114 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 1115 sizeof(struct aqr107_priv), GFP_KERNEL); 1116 if (!phydev->priv) 1117 return -ENOMEM; 1118 1119 ret = aqr_firmware_load(phydev); 1120 if (ret) 1121 return ret; 1122 1123 return aqr_hwmon_probe(phydev); 1124 } 1125 1126 1127 static struct phy_driver aqr_driver[] = { 1128 { 1129 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 1130 .name = "Aquantia AQ1202", 1131 .config_aneg = aqr_config_aneg, 1132 .config_intr = aqr_config_intr, 1133 .handle_interrupt = aqr_handle_interrupt, 1134 .read_status = aqr_read_status, 1135 }, 1136 { 1137 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 1138 .name = "Aquantia AQ2104", 1139 .config_aneg = aqr_config_aneg, 1140 .config_intr = aqr_config_intr, 1141 .handle_interrupt = aqr_handle_interrupt, 1142 .read_status = aqr_read_status, 1143 }, 1144 { 1145 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 1146 .name = "Aquantia AQR105", 1147 .get_features = aqr105_get_features, 1148 .probe = aqr107_probe, 1149 .config_init = aqr107_config_init, 1150 .config_aneg = aqr105_config_aneg, 1151 .config_intr = aqr_config_intr, 1152 .handle_interrupt = aqr_handle_interrupt, 1153 .read_status = aqr105_read_status, 1154 .suspend = aqr107_suspend, 1155 .resume = aqr107_resume, 1156 }, 1157 { 1158 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 1159 .name = "Aquantia AQR106", 1160 .config_aneg = aqr_config_aneg, 1161 .config_intr = aqr_config_intr, 1162 .handle_interrupt = aqr_handle_interrupt, 1163 .read_status = aqr_read_status, 1164 }, 1165 { 1166 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 1167 .name = "Aquantia AQR107", 1168 .probe = aqr107_probe, 1169 .get_rate_matching = aqr107_get_rate_matching, 1170 .config_init = aqr107_config_init, 1171 .config_aneg = aqr_config_aneg, 1172 .config_intr = aqr_config_intr, 1173 .handle_interrupt = aqr_handle_interrupt, 1174 .read_status = aqr107_read_status, 1175 .get_tunable = aqr107_get_tunable, 1176 .set_tunable = aqr107_set_tunable, 1177 .suspend = aqr107_suspend, 1178 .resume = aqr107_resume, 1179 .get_sset_count = aqr107_get_sset_count, 1180 .get_strings = aqr107_get_strings, 1181 .get_stats = aqr107_get_stats, 1182 .link_change_notify = aqr107_link_change_notify, 1183 .led_brightness_set = aqr_phy_led_brightness_set, 1184 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1185 .led_hw_control_set = aqr_phy_led_hw_control_set, 1186 .led_hw_control_get = aqr_phy_led_hw_control_get, 1187 .led_polarity_set = aqr_phy_led_polarity_set, 1188 }, 1189 { 1190 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 1191 .name = "Aquantia AQCS109", 1192 .probe = aqr107_probe, 1193 .get_rate_matching = aqr107_get_rate_matching, 1194 .config_init = aqcs109_config_init, 1195 .config_aneg = aqr_config_aneg, 1196 .config_intr = aqr_config_intr, 1197 .handle_interrupt = aqr_handle_interrupt, 1198 .read_status = aqr107_read_status, 1199 .get_tunable = aqr107_get_tunable, 1200 .set_tunable = aqr107_set_tunable, 1201 .suspend = aqr107_suspend, 1202 .resume = aqr107_resume, 1203 .get_sset_count = aqr107_get_sset_count, 1204 .get_strings = aqr107_get_strings, 1205 .get_stats = aqr107_get_stats, 1206 .get_features = aqr115c_get_features, 1207 .link_change_notify = aqr107_link_change_notify, 1208 .led_brightness_set = aqr_phy_led_brightness_set, 1209 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1210 .led_hw_control_set = aqr_phy_led_hw_control_set, 1211 .led_hw_control_get = aqr_phy_led_hw_control_get, 1212 .led_polarity_set = aqr_phy_led_polarity_set, 1213 }, 1214 { 1215 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 1216 .name = "Aquantia AQR111", 1217 .probe = aqr107_probe, 1218 .get_rate_matching = aqr107_get_rate_matching, 1219 .config_init = aqr107_config_init, 1220 .config_aneg = aqr_config_aneg, 1221 .config_intr = aqr_config_intr, 1222 .handle_interrupt = aqr_handle_interrupt, 1223 .read_status = aqr107_read_status, 1224 .get_tunable = aqr107_get_tunable, 1225 .set_tunable = aqr107_set_tunable, 1226 .suspend = aqr107_suspend, 1227 .resume = aqr107_resume, 1228 .get_sset_count = aqr107_get_sset_count, 1229 .get_strings = aqr107_get_strings, 1230 .get_stats = aqr107_get_stats, 1231 .get_features = aqr111_get_features, 1232 .link_change_notify = aqr107_link_change_notify, 1233 .led_brightness_set = aqr_phy_led_brightness_set, 1234 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1235 .led_hw_control_set = aqr_phy_led_hw_control_set, 1236 .led_hw_control_get = aqr_phy_led_hw_control_get, 1237 .led_polarity_set = aqr_phy_led_polarity_set, 1238 }, 1239 { 1240 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 1241 .name = "Aquantia AQR111B0", 1242 .probe = aqr107_probe, 1243 .get_rate_matching = aqr107_get_rate_matching, 1244 .config_init = aqr107_config_init, 1245 .config_aneg = aqr_config_aneg, 1246 .config_intr = aqr_config_intr, 1247 .handle_interrupt = aqr_handle_interrupt, 1248 .read_status = aqr107_read_status, 1249 .get_tunable = aqr107_get_tunable, 1250 .set_tunable = aqr107_set_tunable, 1251 .suspend = aqr107_suspend, 1252 .resume = aqr107_resume, 1253 .get_sset_count = aqr107_get_sset_count, 1254 .get_strings = aqr107_get_strings, 1255 .get_stats = aqr107_get_stats, 1256 .get_features = aqr111_get_features, 1257 .link_change_notify = aqr107_link_change_notify, 1258 .led_brightness_set = aqr_phy_led_brightness_set, 1259 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1260 .led_hw_control_set = aqr_phy_led_hw_control_set, 1261 .led_hw_control_get = aqr_phy_led_hw_control_get, 1262 .led_polarity_set = aqr_phy_led_polarity_set, 1263 }, 1264 { 1265 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 1266 .name = "Aquantia AQR405", 1267 .config_aneg = aqr_config_aneg, 1268 .config_intr = aqr_config_intr, 1269 .handle_interrupt = aqr_handle_interrupt, 1270 .read_status = aqr_read_status, 1271 }, 1272 { 1273 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 1274 .name = "Aquantia AQR112", 1275 .probe = aqr107_probe, 1276 .config_aneg = aqr_config_aneg, 1277 .config_intr = aqr_config_intr, 1278 .handle_interrupt = aqr_handle_interrupt, 1279 .get_tunable = aqr107_get_tunable, 1280 .set_tunable = aqr107_set_tunable, 1281 .suspend = aqr107_suspend, 1282 .resume = aqr107_resume, 1283 .read_status = aqr107_read_status, 1284 .get_rate_matching = aqr107_get_rate_matching, 1285 .get_sset_count = aqr107_get_sset_count, 1286 .get_strings = aqr107_get_strings, 1287 .get_stats = aqr107_get_stats, 1288 .link_change_notify = aqr107_link_change_notify, 1289 .led_brightness_set = aqr_phy_led_brightness_set, 1290 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1291 .led_hw_control_set = aqr_phy_led_hw_control_set, 1292 .led_hw_control_get = aqr_phy_led_hw_control_get, 1293 .led_polarity_set = aqr_phy_led_polarity_set, 1294 }, 1295 { 1296 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 1297 .name = "Aquantia AQR412", 1298 .probe = aqr107_probe, 1299 .config_aneg = aqr_config_aneg, 1300 .config_intr = aqr_config_intr, 1301 .handle_interrupt = aqr_handle_interrupt, 1302 .get_tunable = aqr107_get_tunable, 1303 .set_tunable = aqr107_set_tunable, 1304 .suspend = aqr107_suspend, 1305 .resume = aqr107_resume, 1306 .read_status = aqr107_read_status, 1307 .get_rate_matching = aqr107_get_rate_matching, 1308 .get_sset_count = aqr107_get_sset_count, 1309 .get_strings = aqr107_get_strings, 1310 .get_stats = aqr107_get_stats, 1311 .link_change_notify = aqr107_link_change_notify, 1312 }, 1313 { 1314 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 1315 .name = "Aquantia AQR113", 1316 .probe = aqr107_probe, 1317 .get_rate_matching = aqr107_get_rate_matching, 1318 .config_init = aqr113c_config_init, 1319 .config_aneg = aqr_config_aneg, 1320 .config_intr = aqr_config_intr, 1321 .handle_interrupt = aqr_handle_interrupt, 1322 .read_status = aqr107_read_status, 1323 .get_tunable = aqr107_get_tunable, 1324 .set_tunable = aqr107_set_tunable, 1325 .suspend = aqr107_suspend, 1326 .resume = aqr107_resume, 1327 .get_sset_count = aqr107_get_sset_count, 1328 .get_strings = aqr107_get_strings, 1329 .get_stats = aqr107_get_stats, 1330 .link_change_notify = aqr107_link_change_notify, 1331 .led_brightness_set = aqr_phy_led_brightness_set, 1332 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1333 .led_hw_control_set = aqr_phy_led_hw_control_set, 1334 .led_hw_control_get = aqr_phy_led_hw_control_get, 1335 .led_polarity_set = aqr_phy_led_polarity_set, 1336 }, 1337 { 1338 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 1339 .name = "Aquantia AQR113C", 1340 .probe = aqr107_probe, 1341 .get_rate_matching = aqr107_get_rate_matching, 1342 .config_init = aqr113c_config_init, 1343 .config_aneg = aqr_config_aneg, 1344 .config_intr = aqr_config_intr, 1345 .handle_interrupt = aqr_handle_interrupt, 1346 .read_status = aqr107_read_status, 1347 .get_tunable = aqr107_get_tunable, 1348 .set_tunable = aqr107_set_tunable, 1349 .suspend = aqr107_suspend, 1350 .resume = aqr107_resume, 1351 .get_sset_count = aqr107_get_sset_count, 1352 .get_strings = aqr107_get_strings, 1353 .get_stats = aqr107_get_stats, 1354 .link_change_notify = aqr107_link_change_notify, 1355 .led_brightness_set = aqr_phy_led_brightness_set, 1356 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1357 .led_hw_control_set = aqr_phy_led_hw_control_set, 1358 .led_hw_control_get = aqr_phy_led_hw_control_get, 1359 .led_polarity_set = aqr_phy_led_polarity_set, 1360 }, 1361 { 1362 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 1363 .name = "Aquantia AQR114C", 1364 .probe = aqr107_probe, 1365 .get_rate_matching = aqr107_get_rate_matching, 1366 .config_init = aqr107_config_init, 1367 .config_aneg = aqr_config_aneg, 1368 .config_intr = aqr_config_intr, 1369 .handle_interrupt = aqr_handle_interrupt, 1370 .read_status = aqr107_read_status, 1371 .get_tunable = aqr107_get_tunable, 1372 .set_tunable = aqr107_set_tunable, 1373 .suspend = aqr107_suspend, 1374 .resume = aqr107_resume, 1375 .get_sset_count = aqr107_get_sset_count, 1376 .get_strings = aqr107_get_strings, 1377 .get_stats = aqr107_get_stats, 1378 .get_features = aqr111_get_features, 1379 .link_change_notify = aqr107_link_change_notify, 1380 .led_brightness_set = aqr_phy_led_brightness_set, 1381 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1382 .led_hw_control_set = aqr_phy_led_hw_control_set, 1383 .led_hw_control_get = aqr_phy_led_hw_control_get, 1384 .led_polarity_set = aqr_phy_led_polarity_set, 1385 }, 1386 { 1387 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), 1388 .name = "Aquantia AQR115C", 1389 .probe = aqr107_probe, 1390 .get_rate_matching = aqr107_get_rate_matching, 1391 .config_init = aqr113c_config_init, 1392 .config_aneg = aqr_config_aneg, 1393 .config_intr = aqr_config_intr, 1394 .handle_interrupt = aqr_handle_interrupt, 1395 .read_status = aqr107_read_status, 1396 .get_tunable = aqr107_get_tunable, 1397 .set_tunable = aqr107_set_tunable, 1398 .suspend = aqr107_suspend, 1399 .resume = aqr107_resume, 1400 .get_sset_count = aqr107_get_sset_count, 1401 .get_strings = aqr107_get_strings, 1402 .get_stats = aqr107_get_stats, 1403 .get_features = aqr115c_get_features, 1404 .link_change_notify = aqr107_link_change_notify, 1405 .led_brightness_set = aqr_phy_led_brightness_set, 1406 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1407 .led_hw_control_set = aqr_phy_led_hw_control_set, 1408 .led_hw_control_get = aqr_phy_led_hw_control_get, 1409 .led_polarity_set = aqr_phy_led_polarity_set, 1410 }, 1411 { 1412 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 1413 .name = "Aquantia AQR813", 1414 .probe = aqr107_probe, 1415 .get_rate_matching = aqr107_get_rate_matching, 1416 .config_init = aqr107_config_init, 1417 .config_aneg = aqr_config_aneg, 1418 .config_intr = aqr_config_intr, 1419 .handle_interrupt = aqr_handle_interrupt, 1420 .read_status = aqr107_read_status, 1421 .get_tunable = aqr107_get_tunable, 1422 .set_tunable = aqr107_set_tunable, 1423 .suspend = aqr107_suspend, 1424 .resume = aqr107_resume, 1425 .get_sset_count = aqr107_get_sset_count, 1426 .get_strings = aqr107_get_strings, 1427 .get_stats = aqr107_get_stats, 1428 .link_change_notify = aqr107_link_change_notify, 1429 .led_brightness_set = aqr_phy_led_brightness_set, 1430 .led_hw_is_supported = aqr_phy_led_hw_is_supported, 1431 .led_hw_control_set = aqr_phy_led_hw_control_set, 1432 .led_hw_control_get = aqr_phy_led_hw_control_get, 1433 .led_polarity_set = aqr_phy_led_polarity_set, 1434 }, 1435 }; 1436 1437 module_phy_driver(aqr_driver); 1438 1439 static const struct mdio_device_id __maybe_unused aqr_tbl[] = { 1440 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1441 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1442 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1443 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1444 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1445 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1446 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1447 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1448 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1449 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1450 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1451 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1452 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1453 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1454 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, 1455 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1456 { } 1457 }; 1458 1459 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1460 1461 MODULE_DESCRIPTION("Aquantia PHY driver"); 1462 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1463 MODULE_LICENSE("GPL v2"); 1464