1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* HWMON driver for Aquantia PHY 3 * 4 * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com> 5 * Author: Andrew Lunn <andrew@lunn.ch> 6 * Author: Heiner Kallweit <hkallweit1@gmail.com> 7 */ 8 9 #ifndef AQUANTIA_H 10 #define AQUANTIA_H 11 12 #include <linux/device.h> 13 #include <linux/phy.h> 14 15 /* Vendor specific 1, MDIO_MMD_VEND1 */ 16 #define VEND1_GLOBAL_SC 0x0 17 #define VEND1_GLOBAL_SC_SOFT_RESET BIT(15) 18 #define VEND1_GLOBAL_SC_LOW_POWER BIT(11) 19 20 #define VEND1_GLOBAL_FW_ID 0x0020 21 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 22 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 23 24 #define VEND1_GLOBAL_MAILBOX_INTERFACE1 0x0200 25 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE BIT(15) 26 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE BIT(14) 27 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET BIT(12) 28 #define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY BIT(8) 29 30 #define VEND1_GLOBAL_MAILBOX_INTERFACE2 0x0201 31 #define VEND1_GLOBAL_MAILBOX_INTERFACE3 0x0202 32 #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0) 33 #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16)) 34 #define VEND1_GLOBAL_MAILBOX_INTERFACE4 0x0203 35 #define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK GENMASK(15, 2) 36 #define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x)) 37 38 #define VEND1_GLOBAL_MAILBOX_INTERFACE5 0x0204 39 #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0) 40 #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16)) 41 #define VEND1_GLOBAL_MAILBOX_INTERFACE6 0x0205 42 #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0) 43 #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x)) 44 45 /* The following registers all have similar layouts; first the registers... */ 46 #define VEND1_GLOBAL_CFG_10M 0x0310 47 #define VEND1_GLOBAL_CFG_100M 0x031b 48 #define VEND1_GLOBAL_CFG_1G 0x031c 49 #define VEND1_GLOBAL_CFG_2_5G 0x031d 50 #define VEND1_GLOBAL_CFG_5G 0x031e 51 #define VEND1_GLOBAL_CFG_10G 0x031f 52 /* ...and now the fields */ 53 #define VEND1_GLOBAL_CFG_SERDES_MODE GENMASK(2, 0) 54 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI 0 55 #define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII 3 56 #define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII 4 57 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G 6 58 #define VEND1_GLOBAL_CFG_AUTONEG_ENA BIT(3) 59 #define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7) 60 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0 61 #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1 62 #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2 63 64 /* Vendor specific 1, MDIO_MMD_VEND2 */ 65 #define VEND1_GLOBAL_CONTROL2 0xc001 66 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST BIT(15) 67 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD BIT(6) 68 #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL BIT(0) 69 70 #define VEND1_GLOBAL_LED_PROV 0xc430 71 #define AQR_LED_PROV(x) (VEND1_GLOBAL_LED_PROV + (x)) 72 #define VEND1_GLOBAL_LED_PROV_LINK2500 BIT(14) 73 #define VEND1_GLOBAL_LED_PROV_LINK5000 BIT(15) 74 #define VEND1_GLOBAL_LED_PROV_FORCE_ON BIT(8) 75 #define VEND1_GLOBAL_LED_PROV_LINK10000 BIT(7) 76 #define VEND1_GLOBAL_LED_PROV_LINK1000 BIT(6) 77 #define VEND1_GLOBAL_LED_PROV_LINK100 BIT(5) 78 #define VEND1_GLOBAL_LED_PROV_RX_ACT BIT(3) 79 #define VEND1_GLOBAL_LED_PROV_TX_ACT BIT(2) 80 #define VEND1_GLOBAL_LED_PROV_ACT_STRETCH GENMASK(0, 1) 81 82 #define VEND1_GLOBAL_LED_PROV_LINK_MASK (VEND1_GLOBAL_LED_PROV_LINK100 | \ 83 VEND1_GLOBAL_LED_PROV_LINK1000 | \ 84 VEND1_GLOBAL_LED_PROV_LINK10000 | \ 85 VEND1_GLOBAL_LED_PROV_LINK5000 | \ 86 VEND1_GLOBAL_LED_PROV_LINK2500) 87 88 #define VEND1_GLOBAL_LED_DRIVE 0xc438 89 #define VEND1_GLOBAL_LED_DRIVE_VDD BIT(1) 90 #define AQR_LED_DRIVE(x) (VEND1_GLOBAL_LED_DRIVE + (x)) 91 92 #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421 93 #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422 94 #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423 95 #define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424 96 #define VEND1_THERMAL_STAT1 0xc820 97 #define VEND1_THERMAL_STAT2 0xc821 98 #define VEND1_THERMAL_STAT2_VALID BIT(0) 99 #define VEND1_GENERAL_STAT1 0xc830 100 #define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14) 101 #define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13) 102 #define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12) 103 #define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11) 104 105 #define VEND1_GLOBAL_GEN_STAT2 0xc831 106 #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15) 107 108 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 109 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 110 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 111 112 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 113 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 114 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 115 116 /* MDIO_MMD_C22EXT */ 117 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 118 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 119 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 120 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 121 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 122 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 123 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 124 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 125 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 126 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 127 128 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 129 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 130 131 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 132 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 133 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 134 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 135 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 136 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 137 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 138 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 139 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 140 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 141 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 142 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 143 144 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 145 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 146 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 147 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 148 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 149 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 150 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 151 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 152 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 153 154 #define AQR_MAX_LEDS 3 155 156 /* Custom driver definitions for constructing a single variable out of 157 * aggregate firmware build information. These do not represent hardware 158 * fields. 159 */ 160 #define AQR_FW_FINGERPRINT_MAJOR GENMASK_ULL(63, 56) 161 #define AQR_FW_FINGERPRINT_MINOR GENMASK_ULL(55, 48) 162 #define AQR_FW_FINGERPRINT_BUILD_ID GENMASK_ULL(47, 40) 163 #define AQR_FW_FINGERPRINT_PROV_ID GENMASK_ULL(39, 32) 164 #define AQR_FW_FINGERPRINT_MISC_ID GENMASK_ULL(31, 16) 165 #define AQR_FW_FINGERPRINT_MISC_VER GENMASK_ULL(15, 0) 166 #define AQR_FW_FINGERPRINT(major, minor, build_id, prov_id, misc_id, misc_ver) \ 167 (FIELD_PREP(AQR_FW_FINGERPRINT_MAJOR, major) | \ 168 FIELD_PREP(AQR_FW_FINGERPRINT_MINOR, minor) | \ 169 FIELD_PREP(AQR_FW_FINGERPRINT_BUILD_ID, build_id) | \ 170 FIELD_PREP(AQR_FW_FINGERPRINT_PROV_ID, prov_id) | \ 171 FIELD_PREP(AQR_FW_FINGERPRINT_MISC_ID, misc_id) | \ 172 FIELD_PREP(AQR_FW_FINGERPRINT_MISC_VER, misc_ver)) 173 174 /* 10G-QXGMII firmware for NXP SPF-30841 riser board (AQR412C) */ 175 #define AQR_G3_V4_3_C_AQR_NXP_SPF_30841_MUSX_ID40019_VER1198 \ 176 AQR_FW_FINGERPRINT(4, 3, 0xc, 1, 40019, 1198) 177 178 struct aqr107_hw_stat { 179 const char *name; 180 int reg; 181 int size; 182 }; 183 184 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 185 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 186 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 187 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 188 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 189 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 190 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 191 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 192 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 193 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 194 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 195 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 196 }; 197 198 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 199 200 static const struct { 201 int speed; 202 u16 reg; 203 } aqr_global_cfg_regs[] = { 204 { SPEED_10, VEND1_GLOBAL_CFG_10M, }, 205 { SPEED_100, VEND1_GLOBAL_CFG_100M, }, 206 { SPEED_1000, VEND1_GLOBAL_CFG_1G, }, 207 { SPEED_2500, VEND1_GLOBAL_CFG_2_5G, }, 208 { SPEED_5000, VEND1_GLOBAL_CFG_5G, }, 209 { SPEED_10000, VEND1_GLOBAL_CFG_10G, }, 210 }; 211 212 #define AQR_NUM_GLOBAL_CFG ARRAY_SIZE(aqr_global_cfg_regs) 213 214 enum aqr_rate_adaptation { 215 AQR_RATE_ADAPT_NONE, 216 AQR_RATE_ADAPT_USX, 217 AQR_RATE_ADAPT_PAUSE, 218 }; 219 220 struct aqr_global_syscfg { 221 int speed; 222 phy_interface_t interface; 223 enum aqr_rate_adaptation rate_adapt; 224 }; 225 226 struct aqr107_priv { 227 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 228 u64 fingerprint; 229 unsigned long leds_active_low; 230 unsigned long leds_active_high; 231 bool wait_on_global_cfg; 232 struct aqr_global_syscfg global_cfg[AQR_NUM_GLOBAL_CFG]; 233 }; 234 235 #if IS_REACHABLE(CONFIG_HWMON) 236 int aqr_hwmon_probe(struct phy_device *phydev); 237 #else 238 static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; } 239 #endif 240 241 int aqr_firmware_load(struct phy_device *phydev); 242 243 int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index, 244 unsigned long *delay_on, 245 unsigned long *delay_off); 246 int aqr_phy_led_brightness_set(struct phy_device *phydev, 247 u8 index, enum led_brightness value); 248 int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 249 unsigned long rules); 250 int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 251 unsigned long *rules); 252 int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 253 unsigned long rules); 254 int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable); 255 int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, 256 unsigned long modes); 257 int aqr_wait_reset_complete(struct phy_device *phydev); 258 259 #endif /* AQUANTIA_H */ 260