1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the Airoha EN8811H 2.5 Gigabit PHY. 4 * 5 * Limitations of the EN8811H: 6 * - Only full duplex supported 7 * - Forced speed (AN off) is not supported by hardware (100Mbps) 8 * 9 * Source originated from airoha's en8811h.c and en8811h.h v1.2.1 10 * 11 * Copyright (C) 2023 Airoha Technology Corp. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/phy.h> 16 #include <linux/firmware.h> 17 #include <linux/property.h> 18 #include <linux/wordpart.h> 19 #include <linux/unaligned.h> 20 21 #define EN8811H_PHY_ID 0x03a2a411 22 23 #define EN8811H_MD32_DM "airoha/EthMD32.dm.bin" 24 #define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin" 25 26 #define AIR_FW_ADDR_DM 0x00000000 27 #define AIR_FW_ADDR_DSP 0x00100000 28 29 /* MII Registers */ 30 #define AIR_AUX_CTRL_STATUS 0x1d 31 #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) 32 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 33 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 34 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc 35 36 #define AIR_EXT_PAGE_ACCESS 0x1f 37 #define AIR_PHY_PAGE_STANDARD 0x0000 38 #define AIR_PHY_PAGE_EXTENDED_4 0x0004 39 40 /* MII Registers Page 4*/ 41 #define AIR_BPBUS_MODE 0x10 42 #define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 43 #define AIR_BPBUS_MODE_ADDR_INCR BIT(15) 44 #define AIR_BPBUS_WR_ADDR_HIGH 0x11 45 #define AIR_BPBUS_WR_ADDR_LOW 0x12 46 #define AIR_BPBUS_WR_DATA_HIGH 0x13 47 #define AIR_BPBUS_WR_DATA_LOW 0x14 48 #define AIR_BPBUS_RD_ADDR_HIGH 0x15 49 #define AIR_BPBUS_RD_ADDR_LOW 0x16 50 #define AIR_BPBUS_RD_DATA_HIGH 0x17 51 #define AIR_BPBUS_RD_DATA_LOW 0x18 52 53 /* Registers on MDIO_MMD_VEND1 */ 54 #define EN8811H_PHY_FW_STATUS 0x8009 55 #define EN8811H_PHY_READY 0x02 56 57 #define AIR_PHY_MCU_CMD_1 0x800c 58 #define AIR_PHY_MCU_CMD_1_MODE1 0x0 59 #define AIR_PHY_MCU_CMD_2 0x800d 60 #define AIR_PHY_MCU_CMD_2_MODE1 0x0 61 #define AIR_PHY_MCU_CMD_3 0x800e 62 #define AIR_PHY_MCU_CMD_3_MODE1 0x1101 63 #define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 64 #define AIR_PHY_MCU_CMD_4 0x800f 65 #define AIR_PHY_MCU_CMD_4_MODE1 0x0002 66 #define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 67 68 /* Registers on MDIO_MMD_VEND2 */ 69 #define AIR_PHY_LED_BCR 0x021 70 #define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0) 71 #define AIR_PHY_LED_BCR_TIME_TEST BIT(2) 72 #define AIR_PHY_LED_BCR_CLK_EN BIT(3) 73 #define AIR_PHY_LED_BCR_EXT_CTRL BIT(15) 74 75 #define AIR_PHY_LED_DUR_ON 0x022 76 77 #define AIR_PHY_LED_DUR_BLINK 0x023 78 79 #define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) 80 #define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8)) 81 #define AIR_PHY_LED_ON_LINK1000 BIT(0) 82 #define AIR_PHY_LED_ON_LINK100 BIT(1) 83 #define AIR_PHY_LED_ON_LINK10 BIT(2) 84 #define AIR_PHY_LED_ON_LINKDOWN BIT(3) 85 #define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 86 #define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 87 #define AIR_PHY_LED_ON_FORCE_ON BIT(6) 88 #define AIR_PHY_LED_ON_LINK2500 BIT(8) 89 #define AIR_PHY_LED_ON_POLARITY BIT(14) 90 #define AIR_PHY_LED_ON_ENABLE BIT(15) 91 92 #define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) 93 #define AIR_PHY_LED_BLINK_1000TX BIT(0) 94 #define AIR_PHY_LED_BLINK_1000RX BIT(1) 95 #define AIR_PHY_LED_BLINK_100TX BIT(2) 96 #define AIR_PHY_LED_BLINK_100RX BIT(3) 97 #define AIR_PHY_LED_BLINK_10TX BIT(4) 98 #define AIR_PHY_LED_BLINK_10RX BIT(5) 99 #define AIR_PHY_LED_BLINK_COLLISION BIT(6) 100 #define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 101 #define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 102 #define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9) 103 #define AIR_PHY_LED_BLINK_2500TX BIT(10) 104 #define AIR_PHY_LED_BLINK_2500RX BIT(11) 105 106 /* Registers on BUCKPBUS */ 107 #define EN8811H_2P5G_LPA 0x3b30 108 #define EN8811H_2P5G_LPA_2P5G BIT(0) 109 110 #define EN8811H_FW_VERSION 0x3b3c 111 112 #define EN8811H_POLARITY 0xca0f8 113 #define EN8811H_POLARITY_TX_NORMAL BIT(0) 114 #define EN8811H_POLARITY_RX_REVERSE BIT(1) 115 116 #define EN8811H_GPIO_OUTPUT 0xcf8b8 117 #define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) 118 119 #define EN8811H_HWTRAP1 0xcf914 120 #define EN8811H_HWTRAP1_CKO BIT(12) 121 #define EN8811H_CLK_CGM 0xcf958 122 #define EN8811H_CLK_CGM_CKO BIT(26) 123 124 #define EN8811H_FW_CTRL_1 0x0f0018 125 #define EN8811H_FW_CTRL_1_START 0x0 126 #define EN8811H_FW_CTRL_1_FINISH 0x1 127 #define EN8811H_FW_CTRL_2 0x800000 128 #define EN8811H_FW_CTRL_2_LOADING BIT(11) 129 130 /* Led definitions */ 131 #define EN8811H_LED_COUNT 3 132 133 /* Default LED setup: 134 * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx 135 * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps 136 * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps 137 */ 138 #define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \ 139 BIT(TRIGGER_NETDEV_RX) | \ 140 BIT(TRIGGER_NETDEV_TX)) 141 #define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \ 142 BIT(TRIGGER_NETDEV_LINK_1000)) 143 #define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \ 144 BIT(TRIGGER_NETDEV_LINK_100)) 145 146 struct led { 147 unsigned long rules; 148 unsigned long state; 149 }; 150 151 #define clk_hw_to_en8811h_priv(_hw) \ 152 container_of(_hw, struct en8811h_priv, hw) 153 154 struct en8811h_priv { 155 u32 firmware_version; 156 bool mcu_needs_restart; 157 struct led led[EN8811H_LED_COUNT]; 158 struct clk_hw hw; 159 struct phy_device *phydev; 160 }; 161 162 enum { 163 AIR_PHY_LED_STATE_FORCE_ON, 164 AIR_PHY_LED_STATE_FORCE_BLINK, 165 }; 166 167 enum { 168 AIR_PHY_LED_DUR_BLINK_32MS, 169 AIR_PHY_LED_DUR_BLINK_64MS, 170 AIR_PHY_LED_DUR_BLINK_128MS, 171 AIR_PHY_LED_DUR_BLINK_256MS, 172 AIR_PHY_LED_DUR_BLINK_512MS, 173 AIR_PHY_LED_DUR_BLINK_1024MS, 174 }; 175 176 enum { 177 AIR_LED_DISABLE, 178 AIR_LED_ENABLE, 179 }; 180 181 enum { 182 AIR_ACTIVE_LOW, 183 AIR_ACTIVE_HIGH, 184 }; 185 186 enum { 187 AIR_LED_MODE_DISABLE, 188 AIR_LED_MODE_USER_DEFINE, 189 }; 190 191 #define AIR_PHY_LED_DUR_UNIT 1024 192 #define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) 193 194 static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 195 BIT(TRIGGER_NETDEV_LINK) | 196 BIT(TRIGGER_NETDEV_LINK_10) | 197 BIT(TRIGGER_NETDEV_LINK_100) | 198 BIT(TRIGGER_NETDEV_LINK_1000) | 199 BIT(TRIGGER_NETDEV_LINK_2500) | 200 BIT(TRIGGER_NETDEV_RX) | 201 BIT(TRIGGER_NETDEV_TX); 202 203 static int air_phy_read_page(struct phy_device *phydev) 204 { 205 return __phy_read(phydev, AIR_EXT_PAGE_ACCESS); 206 } 207 208 static int air_phy_write_page(struct phy_device *phydev, int page) 209 { 210 return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page); 211 } 212 213 static int __air_buckpbus_reg_write(struct phy_device *phydev, 214 u32 pbus_address, u32 pbus_data) 215 { 216 int ret; 217 218 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); 219 if (ret < 0) 220 return ret; 221 222 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 223 upper_16_bits(pbus_address)); 224 if (ret < 0) 225 return ret; 226 227 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 228 lower_16_bits(pbus_address)); 229 if (ret < 0) 230 return ret; 231 232 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, 233 upper_16_bits(pbus_data)); 234 if (ret < 0) 235 return ret; 236 237 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, 238 lower_16_bits(pbus_data)); 239 if (ret < 0) 240 return ret; 241 242 return 0; 243 } 244 245 static int air_buckpbus_reg_write(struct phy_device *phydev, 246 u32 pbus_address, u32 pbus_data) 247 { 248 int saved_page; 249 int ret = 0; 250 251 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 252 253 if (saved_page >= 0) { 254 ret = __air_buckpbus_reg_write(phydev, pbus_address, 255 pbus_data); 256 if (ret < 0) 257 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 258 pbus_address, ret); 259 } 260 261 return phy_restore_page(phydev, saved_page, ret); 262 } 263 264 static int __air_buckpbus_reg_read(struct phy_device *phydev, 265 u32 pbus_address, u32 *pbus_data) 266 { 267 int pbus_data_low, pbus_data_high; 268 int ret; 269 270 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); 271 if (ret < 0) 272 return ret; 273 274 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, 275 upper_16_bits(pbus_address)); 276 if (ret < 0) 277 return ret; 278 279 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, 280 lower_16_bits(pbus_address)); 281 if (ret < 0) 282 return ret; 283 284 pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); 285 if (pbus_data_high < 0) 286 return pbus_data_high; 287 288 pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); 289 if (pbus_data_low < 0) 290 return pbus_data_low; 291 292 *pbus_data = pbus_data_low | (pbus_data_high << 16); 293 return 0; 294 } 295 296 static int air_buckpbus_reg_read(struct phy_device *phydev, 297 u32 pbus_address, u32 *pbus_data) 298 { 299 int saved_page; 300 int ret = 0; 301 302 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 303 304 if (saved_page >= 0) { 305 ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); 306 if (ret < 0) 307 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 308 pbus_address, ret); 309 } 310 311 return phy_restore_page(phydev, saved_page, ret); 312 } 313 314 static int __air_buckpbus_reg_modify(struct phy_device *phydev, 315 u32 pbus_address, u32 mask, u32 set) 316 { 317 int pbus_data_low, pbus_data_high; 318 u32 pbus_data_old, pbus_data_new; 319 int ret; 320 321 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); 322 if (ret < 0) 323 return ret; 324 325 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, 326 upper_16_bits(pbus_address)); 327 if (ret < 0) 328 return ret; 329 330 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, 331 lower_16_bits(pbus_address)); 332 if (ret < 0) 333 return ret; 334 335 pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); 336 if (pbus_data_high < 0) 337 return pbus_data_high; 338 339 pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); 340 if (pbus_data_low < 0) 341 return pbus_data_low; 342 343 pbus_data_old = pbus_data_low | (pbus_data_high << 16); 344 pbus_data_new = (pbus_data_old & ~mask) | set; 345 if (pbus_data_new == pbus_data_old) 346 return 0; 347 348 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 349 upper_16_bits(pbus_address)); 350 if (ret < 0) 351 return ret; 352 353 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 354 lower_16_bits(pbus_address)); 355 if (ret < 0) 356 return ret; 357 358 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, 359 upper_16_bits(pbus_data_new)); 360 if (ret < 0) 361 return ret; 362 363 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, 364 lower_16_bits(pbus_data_new)); 365 if (ret < 0) 366 return ret; 367 368 return 0; 369 } 370 371 static int air_buckpbus_reg_modify(struct phy_device *phydev, 372 u32 pbus_address, u32 mask, u32 set) 373 { 374 int saved_page; 375 int ret = 0; 376 377 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 378 379 if (saved_page >= 0) { 380 ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask, 381 set); 382 if (ret < 0) 383 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 384 pbus_address, ret); 385 } 386 387 return phy_restore_page(phydev, saved_page, ret); 388 } 389 390 static int __air_write_buf(struct phy_device *phydev, u32 address, 391 const struct firmware *fw) 392 { 393 unsigned int offset; 394 int ret; 395 u16 val; 396 397 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); 398 if (ret < 0) 399 return ret; 400 401 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 402 upper_16_bits(address)); 403 if (ret < 0) 404 return ret; 405 406 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 407 lower_16_bits(address)); 408 if (ret < 0) 409 return ret; 410 411 for (offset = 0; offset < fw->size; offset += 4) { 412 val = get_unaligned_le16(&fw->data[offset + 2]); 413 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); 414 if (ret < 0) 415 return ret; 416 417 val = get_unaligned_le16(&fw->data[offset]); 418 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); 419 if (ret < 0) 420 return ret; 421 } 422 423 return 0; 424 } 425 426 static int air_write_buf(struct phy_device *phydev, u32 address, 427 const struct firmware *fw) 428 { 429 int saved_page; 430 int ret = 0; 431 432 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 433 434 if (saved_page >= 0) { 435 ret = __air_write_buf(phydev, address, fw); 436 if (ret < 0) 437 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 438 address, ret); 439 } 440 441 return phy_restore_page(phydev, saved_page, ret); 442 } 443 444 static int en8811h_wait_mcu_ready(struct phy_device *phydev) 445 { 446 int ret, reg_value; 447 448 /* Because of mdio-lock, may have to wait for multiple loads */ 449 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 450 EN8811H_PHY_FW_STATUS, reg_value, 451 reg_value == EN8811H_PHY_READY, 452 20000, 7500000, true); 453 if (ret) { 454 phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); 455 return -ENODEV; 456 } 457 458 return 0; 459 } 460 461 static int en8811h_load_firmware(struct phy_device *phydev) 462 { 463 struct en8811h_priv *priv = phydev->priv; 464 struct device *dev = &phydev->mdio.dev; 465 const struct firmware *fw1, *fw2; 466 int ret; 467 468 ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); 469 if (ret < 0) 470 return ret; 471 472 ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev); 473 if (ret < 0) 474 goto en8811h_load_firmware_rel1; 475 476 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 477 EN8811H_FW_CTRL_1_START); 478 if (ret < 0) 479 goto en8811h_load_firmware_out; 480 481 ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, 482 EN8811H_FW_CTRL_2_LOADING, 483 EN8811H_FW_CTRL_2_LOADING); 484 if (ret < 0) 485 goto en8811h_load_firmware_out; 486 487 ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1); 488 if (ret < 0) 489 goto en8811h_load_firmware_out; 490 491 ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2); 492 if (ret < 0) 493 goto en8811h_load_firmware_out; 494 495 ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, 496 EN8811H_FW_CTRL_2_LOADING, 0); 497 if (ret < 0) 498 goto en8811h_load_firmware_out; 499 500 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 501 EN8811H_FW_CTRL_1_FINISH); 502 if (ret < 0) 503 goto en8811h_load_firmware_out; 504 505 ret = en8811h_wait_mcu_ready(phydev); 506 507 air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, 508 &priv->firmware_version); 509 phydev_info(phydev, "MD32 firmware version: %08x\n", 510 priv->firmware_version); 511 512 en8811h_load_firmware_out: 513 release_firmware(fw2); 514 515 en8811h_load_firmware_rel1: 516 release_firmware(fw1); 517 518 if (ret < 0) 519 phydev_err(phydev, "Load firmware failed: %d\n", ret); 520 521 return ret; 522 } 523 524 static int en8811h_restart_mcu(struct phy_device *phydev) 525 { 526 int ret; 527 528 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 529 EN8811H_FW_CTRL_1_START); 530 if (ret < 0) 531 return ret; 532 533 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 534 EN8811H_FW_CTRL_1_FINISH); 535 if (ret < 0) 536 return ret; 537 538 return en8811h_wait_mcu_ready(phydev); 539 } 540 541 static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on) 542 { 543 struct en8811h_priv *priv = phydev->priv; 544 bool changed; 545 546 if (index >= EN8811H_LED_COUNT) 547 return -EINVAL; 548 549 if (on) 550 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON, 551 &priv->led[index].state); 552 else 553 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON, 554 &priv->led[index].state); 555 556 changed |= (priv->led[index].rules != 0); 557 558 /* clear netdev trigger rules in case LED_OFF has been set */ 559 if (!on) 560 priv->led[index].rules = 0; 561 562 if (changed) 563 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 564 AIR_PHY_LED_ON(index), 565 AIR_PHY_LED_ON_MASK, 566 on ? AIR_PHY_LED_ON_FORCE_ON : 0); 567 568 return 0; 569 } 570 571 static int air_hw_led_blink_set(struct phy_device *phydev, u8 index, 572 bool blinking) 573 { 574 struct en8811h_priv *priv = phydev->priv; 575 bool changed; 576 577 if (index >= EN8811H_LED_COUNT) 578 return -EINVAL; 579 580 if (blinking) 581 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 582 &priv->led[index].state); 583 else 584 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 585 &priv->led[index].state); 586 587 changed |= (priv->led[index].rules != 0); 588 589 if (changed) 590 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 591 AIR_PHY_LED_BLINK(index), 592 blinking ? 593 AIR_PHY_LED_BLINK_FORCE_BLINK : 0); 594 else 595 return 0; 596 } 597 598 static int air_led_blink_set(struct phy_device *phydev, u8 index, 599 unsigned long *delay_on, 600 unsigned long *delay_off) 601 { 602 struct en8811h_priv *priv = phydev->priv; 603 bool blinking = false; 604 int err; 605 606 if (index >= EN8811H_LED_COUNT) 607 return -EINVAL; 608 609 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 610 blinking = true; 611 *delay_on = 50; 612 *delay_off = 50; 613 } 614 615 err = air_hw_led_blink_set(phydev, index, blinking); 616 if (err) 617 return err; 618 619 /* led-blink set, so switch led-on off */ 620 err = air_hw_led_on_set(phydev, index, false); 621 if (err) 622 return err; 623 624 /* hw-control is off*/ 625 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state)) 626 priv->led[index].rules = 0; 627 628 return 0; 629 } 630 631 static int air_led_brightness_set(struct phy_device *phydev, u8 index, 632 enum led_brightness value) 633 { 634 struct en8811h_priv *priv = phydev->priv; 635 int err; 636 637 if (index >= EN8811H_LED_COUNT) 638 return -EINVAL; 639 640 /* led-on set, so switch led-blink off */ 641 err = air_hw_led_blink_set(phydev, index, false); 642 if (err) 643 return err; 644 645 err = air_hw_led_on_set(phydev, index, (value != LED_OFF)); 646 if (err) 647 return err; 648 649 /* hw-control is off */ 650 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state)) 651 priv->led[index].rules = 0; 652 653 return 0; 654 } 655 656 static int air_led_hw_control_get(struct phy_device *phydev, u8 index, 657 unsigned long *rules) 658 { 659 struct en8811h_priv *priv = phydev->priv; 660 661 if (index >= EN8811H_LED_COUNT) 662 return -EINVAL; 663 664 *rules = priv->led[index].rules; 665 666 return 0; 667 }; 668 669 static int air_led_hw_control_set(struct phy_device *phydev, u8 index, 670 unsigned long rules) 671 { 672 struct en8811h_priv *priv = phydev->priv; 673 u16 on = 0, blink = 0; 674 int ret; 675 676 if (index >= EN8811H_LED_COUNT) 677 return -EINVAL; 678 679 priv->led[index].rules = rules; 680 681 if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 682 on |= AIR_PHY_LED_ON_FDX; 683 684 if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 685 on |= AIR_PHY_LED_ON_LINK10; 686 687 if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 688 on |= AIR_PHY_LED_ON_LINK100; 689 690 if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 691 on |= AIR_PHY_LED_ON_LINK1000; 692 693 if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) 694 on |= AIR_PHY_LED_ON_LINK2500; 695 696 if (rules & BIT(TRIGGER_NETDEV_RX)) { 697 blink |= AIR_PHY_LED_BLINK_10RX | 698 AIR_PHY_LED_BLINK_100RX | 699 AIR_PHY_LED_BLINK_1000RX | 700 AIR_PHY_LED_BLINK_2500RX; 701 } 702 703 if (rules & BIT(TRIGGER_NETDEV_TX)) { 704 blink |= AIR_PHY_LED_BLINK_10TX | 705 AIR_PHY_LED_BLINK_100TX | 706 AIR_PHY_LED_BLINK_1000TX | 707 AIR_PHY_LED_BLINK_2500TX; 708 } 709 710 if (blink || on) { 711 /* switch hw-control on, so led-on and led-blink are off */ 712 clear_bit(AIR_PHY_LED_STATE_FORCE_ON, 713 &priv->led[index].state); 714 clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 715 &priv->led[index].state); 716 } else { 717 priv->led[index].rules = 0; 718 } 719 720 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), 721 AIR_PHY_LED_ON_MASK, on); 722 723 if (ret < 0) 724 return ret; 725 726 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), 727 blink); 728 }; 729 730 static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) 731 { 732 int val = 0; 733 int err; 734 735 if (index >= EN8811H_LED_COUNT) 736 return -EINVAL; 737 738 if (state == AIR_LED_ENABLE) 739 val |= AIR_PHY_LED_ON_ENABLE; 740 else 741 val &= ~AIR_PHY_LED_ON_ENABLE; 742 743 if (pol == AIR_ACTIVE_HIGH) 744 val |= AIR_PHY_LED_ON_POLARITY; 745 else 746 val &= ~AIR_PHY_LED_ON_POLARITY; 747 748 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), 749 AIR_PHY_LED_ON_ENABLE | 750 AIR_PHY_LED_ON_POLARITY, val); 751 752 if (err < 0) 753 return err; 754 755 return 0; 756 } 757 758 static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode) 759 { 760 struct en8811h_priv *priv = phydev->priv; 761 int ret, i; 762 763 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, 764 dur); 765 if (ret < 0) 766 return ret; 767 768 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, 769 dur >> 1); 770 if (ret < 0) 771 return ret; 772 773 switch (mode) { 774 case AIR_LED_MODE_DISABLE: 775 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, 776 AIR_PHY_LED_BCR_EXT_CTRL | 777 AIR_PHY_LED_BCR_MODE_MASK, 0); 778 if (ret < 0) 779 return ret; 780 break; 781 case AIR_LED_MODE_USER_DEFINE: 782 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, 783 AIR_PHY_LED_BCR_EXT_CTRL | 784 AIR_PHY_LED_BCR_CLK_EN, 785 AIR_PHY_LED_BCR_EXT_CTRL | 786 AIR_PHY_LED_BCR_CLK_EN); 787 if (ret < 0) 788 return ret; 789 break; 790 default: 791 phydev_err(phydev, "LED mode %d is not supported\n", mode); 792 return -EINVAL; 793 } 794 795 for (i = 0; i < num; ++i) { 796 ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH); 797 if (ret < 0) { 798 phydev_err(phydev, "LED%d init failed: %d\n", i, ret); 799 return ret; 800 } 801 air_led_hw_control_set(phydev, i, priv->led[i].rules); 802 } 803 804 return 0; 805 } 806 807 static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index, 808 unsigned long rules) 809 { 810 if (index >= EN8811H_LED_COUNT) 811 return -EINVAL; 812 813 /* All combinations of the supported triggers are allowed */ 814 if (rules & ~en8811h_led_trig) 815 return -EOPNOTSUPP; 816 817 return 0; 818 }; 819 820 static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw, 821 unsigned long parent) 822 { 823 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 824 struct phy_device *phydev = priv->phydev; 825 u32 pbus_value; 826 int ret; 827 828 ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value); 829 if (ret < 0) 830 return ret; 831 832 return (pbus_value & EN8811H_HWTRAP1_CKO) ? 50000000 : 25000000; 833 } 834 835 static int en8811h_clk_enable(struct clk_hw *hw) 836 { 837 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 838 struct phy_device *phydev = priv->phydev; 839 840 return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM, 841 EN8811H_CLK_CGM_CKO, 842 EN8811H_CLK_CGM_CKO); 843 } 844 845 static void en8811h_clk_disable(struct clk_hw *hw) 846 { 847 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 848 struct phy_device *phydev = priv->phydev; 849 850 air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM, 851 EN8811H_CLK_CGM_CKO, 0); 852 } 853 854 static int en8811h_clk_is_enabled(struct clk_hw *hw) 855 { 856 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 857 struct phy_device *phydev = priv->phydev; 858 u32 pbus_value; 859 int ret; 860 861 ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value); 862 if (ret < 0) 863 return ret; 864 865 return (pbus_value & EN8811H_CLK_CGM_CKO); 866 } 867 868 static const struct clk_ops en8811h_clk_ops = { 869 .recalc_rate = en8811h_clk_recalc_rate, 870 .enable = en8811h_clk_enable, 871 .disable = en8811h_clk_disable, 872 .is_enabled = en8811h_clk_is_enabled, 873 }; 874 875 static int en8811h_clk_provider_setup(struct device *dev, struct clk_hw *hw) 876 { 877 struct clk_init_data init; 878 int ret; 879 880 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 881 return 0; 882 883 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko", 884 fwnode_get_name(dev_fwnode(dev))); 885 if (!init.name) 886 return -ENOMEM; 887 888 init.ops = &en8811h_clk_ops; 889 init.flags = 0; 890 init.num_parents = 0; 891 hw->init = &init; 892 893 ret = devm_clk_hw_register(dev, hw); 894 if (ret) 895 return ret; 896 897 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 898 } 899 900 static int en8811h_probe(struct phy_device *phydev) 901 { 902 struct en8811h_priv *priv; 903 int ret; 904 905 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), 906 GFP_KERNEL); 907 if (!priv) 908 return -ENOMEM; 909 phydev->priv = priv; 910 911 ret = en8811h_load_firmware(phydev); 912 if (ret < 0) 913 return ret; 914 915 /* mcu has just restarted after firmware load */ 916 priv->mcu_needs_restart = false; 917 918 priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; 919 priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; 920 priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; 921 922 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ 923 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 924 925 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 926 AIR_LED_MODE_DISABLE); 927 if (ret < 0) { 928 phydev_err(phydev, "Failed to disable leds: %d\n", ret); 929 return ret; 930 } 931 932 priv->phydev = phydev; 933 /* Co-Clock Output */ 934 ret = en8811h_clk_provider_setup(&phydev->mdio.dev, &priv->hw); 935 if (ret) 936 return ret; 937 938 /* Configure led gpio pins as output */ 939 ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT, 940 EN8811H_GPIO_OUTPUT_345, 941 EN8811H_GPIO_OUTPUT_345); 942 if (ret < 0) 943 return ret; 944 945 return 0; 946 } 947 948 static int en8811h_config_init(struct phy_device *phydev) 949 { 950 struct en8811h_priv *priv = phydev->priv; 951 struct device *dev = &phydev->mdio.dev; 952 u32 pbus_value; 953 int ret; 954 955 /* If restart happened in .probe(), no need to restart now */ 956 if (priv->mcu_needs_restart) { 957 ret = en8811h_restart_mcu(phydev); 958 if (ret < 0) 959 return ret; 960 } else { 961 /* Next calls to .config_init() mcu needs to restart */ 962 priv->mcu_needs_restart = true; 963 } 964 965 /* Select mode 1, the only mode supported. 966 * Configures the SerDes for 2500Base-X with rate adaptation 967 */ 968 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, 969 AIR_PHY_MCU_CMD_1_MODE1); 970 if (ret < 0) 971 return ret; 972 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, 973 AIR_PHY_MCU_CMD_2_MODE1); 974 if (ret < 0) 975 return ret; 976 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, 977 AIR_PHY_MCU_CMD_3_MODE1); 978 if (ret < 0) 979 return ret; 980 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, 981 AIR_PHY_MCU_CMD_4_MODE1); 982 if (ret < 0) 983 return ret; 984 985 /* Serdes polarity */ 986 pbus_value = 0; 987 if (device_property_read_bool(dev, "airoha,pnswap-rx")) 988 pbus_value |= EN8811H_POLARITY_RX_REVERSE; 989 else 990 pbus_value &= ~EN8811H_POLARITY_RX_REVERSE; 991 if (device_property_read_bool(dev, "airoha,pnswap-tx")) 992 pbus_value &= ~EN8811H_POLARITY_TX_NORMAL; 993 else 994 pbus_value |= EN8811H_POLARITY_TX_NORMAL; 995 ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, 996 EN8811H_POLARITY_RX_REVERSE | 997 EN8811H_POLARITY_TX_NORMAL, pbus_value); 998 if (ret < 0) 999 return ret; 1000 1001 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1002 AIR_LED_MODE_USER_DEFINE); 1003 if (ret < 0) { 1004 phydev_err(phydev, "Failed to initialize leds: %d\n", ret); 1005 return ret; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int en8811h_get_features(struct phy_device *phydev) 1012 { 1013 linkmode_set_bit_array(phy_basic_ports_array, 1014 ARRAY_SIZE(phy_basic_ports_array), 1015 phydev->supported); 1016 1017 return genphy_c45_pma_read_abilities(phydev); 1018 } 1019 1020 static int en8811h_get_rate_matching(struct phy_device *phydev, 1021 phy_interface_t iface) 1022 { 1023 return RATE_MATCH_PAUSE; 1024 } 1025 1026 static int en8811h_config_aneg(struct phy_device *phydev) 1027 { 1028 bool changed = false; 1029 int ret; 1030 u32 adv; 1031 1032 if (phydev->autoneg == AUTONEG_DISABLE) { 1033 phydev_warn(phydev, "Disabling autoneg is not supported\n"); 1034 return -EINVAL; 1035 } 1036 1037 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1038 1039 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1040 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 1041 if (ret < 0) 1042 return ret; 1043 if (ret > 0) 1044 changed = true; 1045 1046 return __genphy_config_aneg(phydev, changed); 1047 } 1048 1049 static int en8811h_read_status(struct phy_device *phydev) 1050 { 1051 struct en8811h_priv *priv = phydev->priv; 1052 u32 pbus_value; 1053 int ret, val; 1054 1055 ret = genphy_update_link(phydev); 1056 if (ret) 1057 return ret; 1058 1059 phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED; 1060 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1061 phydev->speed = SPEED_UNKNOWN; 1062 phydev->duplex = DUPLEX_UNKNOWN; 1063 phydev->pause = 0; 1064 phydev->asym_pause = 0; 1065 phydev->rate_matching = RATE_MATCH_PAUSE; 1066 1067 ret = genphy_read_master_slave(phydev); 1068 if (ret < 0) 1069 return ret; 1070 1071 ret = genphy_read_lpa(phydev); 1072 if (ret < 0) 1073 return ret; 1074 1075 /* Get link partner 2.5GBASE-T ability from vendor register */ 1076 ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value); 1077 if (ret < 0) 1078 return ret; 1079 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1080 phydev->lp_advertising, 1081 pbus_value & EN8811H_2P5G_LPA_2P5G); 1082 1083 if (phydev->autoneg_complete) 1084 phy_resolve_aneg_pause(phydev); 1085 1086 if (!phydev->link) 1087 return 0; 1088 1089 /* Get real speed from vendor register */ 1090 val = phy_read(phydev, AIR_AUX_CTRL_STATUS); 1091 if (val < 0) 1092 return val; 1093 switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) { 1094 case AIR_AUX_CTRL_STATUS_SPEED_2500: 1095 phydev->speed = SPEED_2500; 1096 break; 1097 case AIR_AUX_CTRL_STATUS_SPEED_1000: 1098 phydev->speed = SPEED_1000; 1099 break; 1100 case AIR_AUX_CTRL_STATUS_SPEED_100: 1101 phydev->speed = SPEED_100; 1102 break; 1103 } 1104 1105 /* Firmware before version 24011202 has no vendor register 2P5G_LPA. 1106 * Assume link partner advertised it if connected at 2500Mbps. 1107 */ 1108 if (priv->firmware_version < 0x24011202) { 1109 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1110 phydev->lp_advertising, 1111 phydev->speed == SPEED_2500); 1112 } 1113 1114 /* Only supports full duplex */ 1115 phydev->duplex = DUPLEX_FULL; 1116 1117 return 0; 1118 } 1119 1120 static int en8811h_clear_intr(struct phy_device *phydev) 1121 { 1122 int ret; 1123 1124 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, 1125 AIR_PHY_MCU_CMD_3_DOCMD); 1126 if (ret < 0) 1127 return ret; 1128 1129 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, 1130 AIR_PHY_MCU_CMD_4_INTCLR); 1131 if (ret < 0) 1132 return ret; 1133 1134 return 0; 1135 } 1136 1137 static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev) 1138 { 1139 int ret; 1140 1141 ret = en8811h_clear_intr(phydev); 1142 if (ret < 0) { 1143 phy_error(phydev); 1144 return IRQ_NONE; 1145 } 1146 1147 phy_trigger_machine(phydev); 1148 1149 return IRQ_HANDLED; 1150 } 1151 1152 static struct phy_driver en8811h_driver[] = { 1153 { 1154 PHY_ID_MATCH_MODEL(EN8811H_PHY_ID), 1155 .name = "Airoha EN8811H", 1156 .probe = en8811h_probe, 1157 .get_features = en8811h_get_features, 1158 .config_init = en8811h_config_init, 1159 .get_rate_matching = en8811h_get_rate_matching, 1160 .config_aneg = en8811h_config_aneg, 1161 .read_status = en8811h_read_status, 1162 .config_intr = en8811h_clear_intr, 1163 .handle_interrupt = en8811h_handle_interrupt, 1164 .led_hw_is_supported = en8811h_led_hw_is_supported, 1165 .read_page = air_phy_read_page, 1166 .write_page = air_phy_write_page, 1167 .led_blink_set = air_led_blink_set, 1168 .led_brightness_set = air_led_brightness_set, 1169 .led_hw_control_set = air_led_hw_control_set, 1170 .led_hw_control_get = air_led_hw_control_get, 1171 } }; 1172 1173 module_phy_driver(en8811h_driver); 1174 1175 static const struct mdio_device_id __maybe_unused en8811h_tbl[] = { 1176 { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, 1177 { } 1178 }; 1179 1180 MODULE_DEVICE_TABLE(mdio, en8811h_tbl); 1181 MODULE_FIRMWARE(EN8811H_MD32_DM); 1182 MODULE_FIRMWARE(EN8811H_MD32_DSP); 1183 1184 MODULE_DESCRIPTION("Airoha EN8811H PHY drivers"); 1185 MODULE_AUTHOR("Airoha"); 1186 MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>"); 1187 MODULE_LICENSE("GPL"); 1188