1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHYs. 4 * 5 * Limitations: 6 * - Only full duplex supported 7 * - Forced speed (AN off) is not supported by hardware (100Mbps) 8 * 9 * Source originated from airoha's en8811h.c and en8811h.h v1.2.1 10 * with AN8811HB bits from air_an8811hb.c v0.0.4 11 * 12 * Copyright (C) 2023, 2026 Airoha Technology Corp. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/phy.h> 18 #include <linux/phy/phy-common-props.h> 19 #include <linux/firmware.h> 20 #include <linux/property.h> 21 #include <linux/wordpart.h> 22 #include <linux/unaligned.h> 23 24 #define EN8811H_PHY_ID 0x03a2a411 25 #define AN8811HB_PHY_ID 0xc0ff04a0 26 27 #define EN8811H_MD32_DM "airoha/EthMD32.dm.bin" 28 #define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin" 29 #define AN8811HB_MD32_DM "airoha/an8811hb/EthMD32_CRC.DM.bin" 30 #define AN8811HB_MD32_DSP "airoha/an8811hb/EthMD32_CRC.DSP.bin" 31 32 #define AIR_FW_ADDR_DM 0x00000000 33 #define AIR_FW_ADDR_DSP 0x00100000 34 35 /* MII Registers */ 36 #define AIR_AUX_CTRL_STATUS 0x1d 37 #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) 38 #define AIR_AUX_CTRL_STATUS_SPEED_10 0x0 39 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 40 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 41 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc 42 43 #define AIR_EXT_PAGE_ACCESS 0x1f 44 #define AIR_PHY_PAGE_STANDARD 0x0000 45 #define AIR_PHY_PAGE_EXTENDED_4 0x0004 46 47 /* MII Registers Page 4*/ 48 #define AIR_BPBUS_MODE 0x10 49 #define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 50 #define AIR_BPBUS_MODE_ADDR_INCR BIT(15) 51 #define AIR_BPBUS_WR_ADDR_HIGH 0x11 52 #define AIR_BPBUS_WR_ADDR_LOW 0x12 53 #define AIR_BPBUS_WR_DATA_HIGH 0x13 54 #define AIR_BPBUS_WR_DATA_LOW 0x14 55 #define AIR_BPBUS_RD_ADDR_HIGH 0x15 56 #define AIR_BPBUS_RD_ADDR_LOW 0x16 57 #define AIR_BPBUS_RD_DATA_HIGH 0x17 58 #define AIR_BPBUS_RD_DATA_LOW 0x18 59 60 /* Registers on MDIO_MMD_VEND1 */ 61 #define EN8811H_PHY_FW_STATUS 0x8009 62 #define EN8811H_PHY_READY 0x02 63 64 #define AIR_PHY_MCU_CMD_0 0x800b 65 #define AIR_PHY_MCU_CMD_1 0x800c 66 #define AIR_PHY_MCU_CMD_1_MODE1 0x0 67 #define AIR_PHY_MCU_CMD_2 0x800d 68 #define AIR_PHY_MCU_CMD_2_MODE1 0x0 69 #define AIR_PHY_MCU_CMD_3 0x800e 70 #define AIR_PHY_MCU_CMD_3_MODE1 0x1101 71 #define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 72 #define AIR_PHY_MCU_CMD_4 0x800f 73 #define AIR_PHY_MCU_CMD_4_MODE1 0x0002 74 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_A 0x00d7 75 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_B 0x00d8 76 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_C 0x00d9 77 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_D 0x00da 78 #define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 79 80 /* Registers on MDIO_MMD_VEND2 */ 81 #define AIR_PHY_LED_BCR 0x021 82 #define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0) 83 #define AIR_PHY_LED_BCR_TIME_TEST BIT(2) 84 #define AIR_PHY_LED_BCR_CLK_EN BIT(3) 85 #define AIR_PHY_LED_BCR_EXT_CTRL BIT(15) 86 87 #define AIR_PHY_LED_DUR_ON 0x022 88 89 #define AIR_PHY_LED_DUR_BLINK 0x023 90 91 #define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) 92 #define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8)) 93 #define AIR_PHY_LED_ON_LINK1000 BIT(0) 94 #define AIR_PHY_LED_ON_LINK100 BIT(1) 95 #define AIR_PHY_LED_ON_LINK10 BIT(2) 96 #define AIR_PHY_LED_ON_LINKDOWN BIT(3) 97 #define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 98 #define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 99 #define AIR_PHY_LED_ON_FORCE_ON BIT(6) 100 #define AIR_PHY_LED_ON_LINK2500 BIT(8) 101 #define AIR_PHY_LED_ON_POLARITY BIT(14) 102 #define AIR_PHY_LED_ON_ENABLE BIT(15) 103 104 #define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) 105 #define AIR_PHY_LED_BLINK_1000TX BIT(0) 106 #define AIR_PHY_LED_BLINK_1000RX BIT(1) 107 #define AIR_PHY_LED_BLINK_100TX BIT(2) 108 #define AIR_PHY_LED_BLINK_100RX BIT(3) 109 #define AIR_PHY_LED_BLINK_10TX BIT(4) 110 #define AIR_PHY_LED_BLINK_10RX BIT(5) 111 #define AIR_PHY_LED_BLINK_COLLISION BIT(6) 112 #define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 113 #define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 114 #define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9) 115 #define AIR_PHY_LED_BLINK_2500TX BIT(10) 116 #define AIR_PHY_LED_BLINK_2500RX BIT(11) 117 118 /* Registers on BUCKPBUS */ 119 #define AIR_PHY_CONTROL 0x3a9c 120 #define AIR_PHY_CONTROL_INTERNAL BIT(11) 121 122 #define EN8811H_2P5G_LPA 0x3b30 123 #define EN8811H_2P5G_LPA_2P5G BIT(0) 124 125 #define EN8811H_FW_VERSION 0x3b3c 126 127 #define EN8811H_POLARITY 0xca0f8 128 #define EN8811H_POLARITY_TX_NORMAL BIT(0) 129 #define EN8811H_POLARITY_RX_REVERSE BIT(1) 130 131 #define EN8811H_GPIO_OUTPUT 0xcf8b8 132 #define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) 133 134 #define EN8811H_HWTRAP1 0xcf914 135 #define EN8811H_HWTRAP1_CKO BIT(12) 136 #define EN8811H_CLK_CGM 0xcf958 137 #define EN8811H_CLK_CGM_CKO BIT(26) 138 139 #define EN8811H_FW_CTRL_1 0x0f0018 140 #define EN8811H_FW_CTRL_1_START 0x0 141 #define EN8811H_FW_CTRL_1_FINISH 0x1 142 #define EN8811H_FW_CTRL_2 0x800000 143 #define EN8811H_FW_CTRL_2_LOADING BIT(11) 144 145 #define AN8811HB_CRC_PM_SET1 0xf020c 146 #define AN8811HB_CRC_PM_MON2 0xf0218 147 #define AN8811HB_CRC_PM_MON3 0xf021c 148 #define AN8811HB_CRC_DM_SET1 0xf0224 149 #define AN8811HB_CRC_DM_MON2 0xf0230 150 #define AN8811HB_CRC_DM_MON3 0xf0234 151 #define AN8811HB_CRC_RD_EN BIT(0) 152 #define AN8811HB_CRC_ST (BIT(0) | BIT(1)) 153 #define AN8811HB_CRC_CHECK_PASS BIT(0) 154 155 #define AN8811HB_TX_POLARITY 0x5ce004 156 #define AN8811HB_TX_POLARITY_NORMAL BIT(7) 157 #define AN8811HB_RX_POLARITY 0x5ce61c 158 #define AN8811HB_RX_POLARITY_NORMAL BIT(7) 159 160 #define AN8811HB_GPIO_OUTPUT 0x5cf8b8 161 #define AN8811HB_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) 162 163 #define AN8811HB_HWTRAP1 0x5cf910 164 #define AN8811HB_HWTRAP2 0x5cf914 165 #define AN8811HB_HWTRAP2_CKO BIT(28) 166 167 #define AN8811HB_CLK_DRV 0x5cf9e4 168 #define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12) 169 #define AN8811HB_CLK_DRV_CKOPWD BIT(12) 170 #define AN8811HB_CLK_DRV_CKO_LDPWD BIT(13) 171 #define AN8811HB_CLK_DRV_CKO_LPPWD BIT(14) 172 173 /* Led definitions */ 174 #define EN8811H_LED_COUNT 3 175 176 /* Default LED setup: 177 * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx 178 * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps 179 * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps 180 */ 181 #define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \ 182 BIT(TRIGGER_NETDEV_RX) | \ 183 BIT(TRIGGER_NETDEV_TX)) 184 #define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \ 185 BIT(TRIGGER_NETDEV_LINK_1000)) 186 #define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \ 187 BIT(TRIGGER_NETDEV_LINK_100)) 188 189 struct led { 190 unsigned long rules; 191 unsigned long state; 192 }; 193 194 #define clk_hw_to_en8811h_priv(_hw) \ 195 container_of(_hw, struct en8811h_priv, hw) 196 197 struct en8811h_priv { 198 u32 firmware_version; 199 bool mcu_needs_restart; 200 struct led led[EN8811H_LED_COUNT]; 201 struct clk_hw hw; 202 struct phy_device *phydev; 203 unsigned int cko_is_enabled; 204 }; 205 206 enum { 207 AIR_PHY_LED_STATE_FORCE_ON, 208 AIR_PHY_LED_STATE_FORCE_BLINK, 209 }; 210 211 enum { 212 AIR_PHY_LED_DUR_BLINK_32MS, 213 AIR_PHY_LED_DUR_BLINK_64MS, 214 AIR_PHY_LED_DUR_BLINK_128MS, 215 AIR_PHY_LED_DUR_BLINK_256MS, 216 AIR_PHY_LED_DUR_BLINK_512MS, 217 AIR_PHY_LED_DUR_BLINK_1024MS, 218 }; 219 220 enum { 221 AIR_LED_DISABLE, 222 AIR_LED_ENABLE, 223 }; 224 225 enum { 226 AIR_ACTIVE_LOW, 227 AIR_ACTIVE_HIGH, 228 }; 229 230 enum { 231 AIR_LED_MODE_DISABLE, 232 AIR_LED_MODE_USER_DEFINE, 233 }; 234 235 #define AIR_PHY_LED_DUR_UNIT 1024 236 #define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) 237 238 static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 239 BIT(TRIGGER_NETDEV_LINK) | 240 BIT(TRIGGER_NETDEV_LINK_10) | 241 BIT(TRIGGER_NETDEV_LINK_100) | 242 BIT(TRIGGER_NETDEV_LINK_1000) | 243 BIT(TRIGGER_NETDEV_LINK_2500) | 244 BIT(TRIGGER_NETDEV_RX) | 245 BIT(TRIGGER_NETDEV_TX); 246 247 static int air_phy_read_page(struct phy_device *phydev) 248 { 249 return __phy_read(phydev, AIR_EXT_PAGE_ACCESS); 250 } 251 252 static int air_phy_write_page(struct phy_device *phydev, int page) 253 { 254 return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page); 255 } 256 257 static int __air_buckpbus_reg_write(struct phy_device *phydev, 258 u32 pbus_address, u32 pbus_data) 259 { 260 int ret; 261 262 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); 263 if (ret < 0) 264 return ret; 265 266 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 267 upper_16_bits(pbus_address)); 268 if (ret < 0) 269 return ret; 270 271 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 272 lower_16_bits(pbus_address)); 273 if (ret < 0) 274 return ret; 275 276 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, 277 upper_16_bits(pbus_data)); 278 if (ret < 0) 279 return ret; 280 281 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, 282 lower_16_bits(pbus_data)); 283 if (ret < 0) 284 return ret; 285 286 return 0; 287 } 288 289 static int air_buckpbus_reg_write(struct phy_device *phydev, 290 u32 pbus_address, u32 pbus_data) 291 { 292 int saved_page; 293 int ret = 0; 294 295 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 296 297 if (saved_page >= 0) { 298 ret = __air_buckpbus_reg_write(phydev, pbus_address, 299 pbus_data); 300 if (ret < 0) 301 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 302 pbus_address, ret); 303 } 304 305 return phy_restore_page(phydev, saved_page, ret); 306 } 307 308 static int __air_buckpbus_reg_read(struct phy_device *phydev, 309 u32 pbus_address, u32 *pbus_data) 310 { 311 int pbus_data_low, pbus_data_high; 312 int ret; 313 314 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); 315 if (ret < 0) 316 return ret; 317 318 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, 319 upper_16_bits(pbus_address)); 320 if (ret < 0) 321 return ret; 322 323 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, 324 lower_16_bits(pbus_address)); 325 if (ret < 0) 326 return ret; 327 328 pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); 329 if (pbus_data_high < 0) 330 return pbus_data_high; 331 332 pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); 333 if (pbus_data_low < 0) 334 return pbus_data_low; 335 336 *pbus_data = pbus_data_low | (pbus_data_high << 16); 337 return 0; 338 } 339 340 static int air_buckpbus_reg_read(struct phy_device *phydev, 341 u32 pbus_address, u32 *pbus_data) 342 { 343 int saved_page; 344 int ret = 0; 345 346 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 347 348 if (saved_page >= 0) { 349 ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); 350 if (ret < 0) 351 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 352 pbus_address, ret); 353 } 354 355 return phy_restore_page(phydev, saved_page, ret); 356 } 357 358 static int __air_buckpbus_reg_modify(struct phy_device *phydev, 359 u32 pbus_address, u32 mask, u32 set) 360 { 361 int pbus_data_low, pbus_data_high; 362 u32 pbus_data_old, pbus_data_new; 363 int ret; 364 365 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); 366 if (ret < 0) 367 return ret; 368 369 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, 370 upper_16_bits(pbus_address)); 371 if (ret < 0) 372 return ret; 373 374 ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, 375 lower_16_bits(pbus_address)); 376 if (ret < 0) 377 return ret; 378 379 pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); 380 if (pbus_data_high < 0) 381 return pbus_data_high; 382 383 pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); 384 if (pbus_data_low < 0) 385 return pbus_data_low; 386 387 pbus_data_old = pbus_data_low | (pbus_data_high << 16); 388 pbus_data_new = (pbus_data_old & ~mask) | set; 389 if (pbus_data_new == pbus_data_old) 390 return 0; 391 392 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 393 upper_16_bits(pbus_address)); 394 if (ret < 0) 395 return ret; 396 397 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 398 lower_16_bits(pbus_address)); 399 if (ret < 0) 400 return ret; 401 402 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, 403 upper_16_bits(pbus_data_new)); 404 if (ret < 0) 405 return ret; 406 407 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, 408 lower_16_bits(pbus_data_new)); 409 if (ret < 0) 410 return ret; 411 412 return 0; 413 } 414 415 static int air_buckpbus_reg_modify(struct phy_device *phydev, 416 u32 pbus_address, u32 mask, u32 set) 417 { 418 int saved_page; 419 int ret = 0; 420 421 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 422 423 if (saved_page >= 0) { 424 ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask, 425 set); 426 if (ret < 0) 427 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 428 pbus_address, ret); 429 } 430 431 return phy_restore_page(phydev, saved_page, ret); 432 } 433 434 static int __air_write_buf(struct phy_device *phydev, u32 address, 435 const struct firmware *fw) 436 { 437 unsigned int offset; 438 int ret; 439 u16 val; 440 441 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); 442 if (ret < 0) 443 return ret; 444 445 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 446 upper_16_bits(address)); 447 if (ret < 0) 448 return ret; 449 450 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 451 lower_16_bits(address)); 452 if (ret < 0) 453 return ret; 454 455 for (offset = 0; offset < fw->size; offset += 4) { 456 val = get_unaligned_le16(&fw->data[offset + 2]); 457 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); 458 if (ret < 0) 459 return ret; 460 461 val = get_unaligned_le16(&fw->data[offset]); 462 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); 463 if (ret < 0) 464 return ret; 465 } 466 467 return 0; 468 } 469 470 static int air_write_buf(struct phy_device *phydev, u32 address, 471 const struct firmware *fw) 472 { 473 int saved_page; 474 int ret = 0; 475 476 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 477 478 if (saved_page >= 0) { 479 ret = __air_write_buf(phydev, address, fw); 480 if (ret < 0) 481 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 482 address, ret); 483 } 484 485 return phy_restore_page(phydev, saved_page, ret); 486 } 487 488 static int en8811h_wait_mcu_ready(struct phy_device *phydev) 489 { 490 int ret, reg_value; 491 492 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 493 EN8811H_FW_CTRL_1_FINISH); 494 if (ret) 495 return ret; 496 497 /* Because of mdio-lock, may have to wait for multiple loads */ 498 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 499 EN8811H_PHY_FW_STATUS, reg_value, 500 reg_value == EN8811H_PHY_READY, 501 20000, 7500000, true); 502 if (ret) { 503 phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); 504 return -ENODEV; 505 } 506 507 return 0; 508 } 509 510 static int an8811hb_check_crc(struct phy_device *phydev, u32 set1, 511 u32 mon2, u32 mon3) 512 { 513 u32 pbus_value; 514 int retry = 25; 515 int ret; 516 517 /* Configure CRC */ 518 ret = air_buckpbus_reg_modify(phydev, set1, 519 AN8811HB_CRC_RD_EN, 520 AN8811HB_CRC_RD_EN); 521 if (ret < 0) 522 return ret; 523 air_buckpbus_reg_read(phydev, set1, &pbus_value); 524 525 do { 526 msleep(300); 527 air_buckpbus_reg_read(phydev, mon2, &pbus_value); 528 529 /* We do not know what errors this check is supposed 530 * catch or what to do about a failure. So print the 531 * result and continue like the vendor driver does. 532 */ 533 if (pbus_value & AN8811HB_CRC_ST) { 534 air_buckpbus_reg_read(phydev, mon3, &pbus_value); 535 phydev_dbg(phydev, "CRC Check %s!\n", 536 pbus_value & AN8811HB_CRC_CHECK_PASS ? 537 "PASS" : "FAIL"); 538 return air_buckpbus_reg_modify(phydev, set1, 539 AN8811HB_CRC_RD_EN, 0); 540 } 541 } while (--retry); 542 543 phydev_err(phydev, "CRC Check is not ready (%u)\n", pbus_value); 544 return -ENODEV; 545 } 546 547 static void en8811h_print_fw_version(struct phy_device *phydev) 548 { 549 struct en8811h_priv *priv = phydev->priv; 550 551 air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, 552 &priv->firmware_version); 553 phydev_info(phydev, "MD32 firmware version: %08x\n", 554 priv->firmware_version); 555 } 556 557 static int an8811hb_load_file(struct phy_device *phydev, const char *name, 558 u32 address) 559 { 560 struct device *dev = &phydev->mdio.dev; 561 const struct firmware *fw; 562 int ret; 563 564 ret = request_firmware_direct(&fw, name, dev); 565 if (ret < 0) 566 return ret; 567 568 ret = air_write_buf(phydev, address, fw); 569 release_firmware(fw); 570 return ret; 571 } 572 573 static int an8811hb_load_firmware(struct phy_device *phydev) 574 { 575 int ret; 576 577 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 578 EN8811H_FW_CTRL_1_START); 579 if (ret < 0) 580 return ret; 581 582 ret = an8811hb_load_file(phydev, AN8811HB_MD32_DM, AIR_FW_ADDR_DM); 583 if (ret < 0) 584 return ret; 585 586 ret = an8811hb_check_crc(phydev, AN8811HB_CRC_DM_SET1, 587 AN8811HB_CRC_DM_MON2, 588 AN8811HB_CRC_DM_MON3); 589 if (ret < 0) 590 return ret; 591 592 ret = an8811hb_load_file(phydev, AN8811HB_MD32_DSP, AIR_FW_ADDR_DSP); 593 if (ret < 0) 594 return ret; 595 596 ret = an8811hb_check_crc(phydev, AN8811HB_CRC_PM_SET1, 597 AN8811HB_CRC_PM_MON2, 598 AN8811HB_CRC_PM_MON3); 599 if (ret < 0) 600 return ret; 601 602 return en8811h_wait_mcu_ready(phydev); 603 } 604 605 static int en8811h_load_firmware(struct phy_device *phydev) 606 { 607 struct device *dev = &phydev->mdio.dev; 608 const struct firmware *fw1, *fw2; 609 int ret; 610 611 ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); 612 if (ret < 0) 613 return ret; 614 615 ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev); 616 if (ret < 0) 617 goto en8811h_load_firmware_rel1; 618 619 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 620 EN8811H_FW_CTRL_1_START); 621 if (ret < 0) 622 goto en8811h_load_firmware_out; 623 624 ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, 625 EN8811H_FW_CTRL_2_LOADING, 626 EN8811H_FW_CTRL_2_LOADING); 627 if (ret < 0) 628 goto en8811h_load_firmware_out; 629 630 ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1); 631 if (ret < 0) 632 goto en8811h_load_firmware_out; 633 634 ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2); 635 if (ret < 0) 636 goto en8811h_load_firmware_out; 637 638 ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, 639 EN8811H_FW_CTRL_2_LOADING, 0); 640 if (ret < 0) 641 goto en8811h_load_firmware_out; 642 643 ret = en8811h_wait_mcu_ready(phydev); 644 if (ret < 0) 645 goto en8811h_load_firmware_out; 646 647 en8811h_print_fw_version(phydev); 648 649 en8811h_load_firmware_out: 650 release_firmware(fw2); 651 652 en8811h_load_firmware_rel1: 653 release_firmware(fw1); 654 655 if (ret < 0) 656 phydev_err(phydev, "Load firmware failed: %d\n", ret); 657 658 return ret; 659 } 660 661 static int en8811h_restart_mcu(struct phy_device *phydev) 662 { 663 int ret; 664 665 ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 666 EN8811H_FW_CTRL_1_START); 667 if (ret < 0) 668 return ret; 669 670 return en8811h_wait_mcu_ready(phydev); 671 } 672 673 static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on) 674 { 675 struct en8811h_priv *priv = phydev->priv; 676 bool changed; 677 678 if (index >= EN8811H_LED_COUNT) 679 return -EINVAL; 680 681 if (on) 682 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON, 683 &priv->led[index].state); 684 else 685 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON, 686 &priv->led[index].state); 687 688 changed |= (priv->led[index].rules != 0); 689 690 /* clear netdev trigger rules in case LED_OFF has been set */ 691 if (!on) 692 priv->led[index].rules = 0; 693 694 if (changed) 695 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 696 AIR_PHY_LED_ON(index), 697 AIR_PHY_LED_ON_MASK, 698 on ? AIR_PHY_LED_ON_FORCE_ON : 0); 699 700 return 0; 701 } 702 703 static int air_hw_led_blink_set(struct phy_device *phydev, u8 index, 704 bool blinking) 705 { 706 struct en8811h_priv *priv = phydev->priv; 707 bool changed; 708 709 if (index >= EN8811H_LED_COUNT) 710 return -EINVAL; 711 712 if (blinking) 713 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 714 &priv->led[index].state); 715 else 716 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 717 &priv->led[index].state); 718 719 changed |= (priv->led[index].rules != 0); 720 721 if (changed) 722 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 723 AIR_PHY_LED_BLINK(index), 724 blinking ? 725 AIR_PHY_LED_BLINK_FORCE_BLINK : 0); 726 else 727 return 0; 728 } 729 730 static int air_led_blink_set(struct phy_device *phydev, u8 index, 731 unsigned long *delay_on, 732 unsigned long *delay_off) 733 { 734 struct en8811h_priv *priv = phydev->priv; 735 bool blinking = false; 736 int err; 737 738 if (index >= EN8811H_LED_COUNT) 739 return -EINVAL; 740 741 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 742 blinking = true; 743 *delay_on = 50; 744 *delay_off = 50; 745 } 746 747 err = air_hw_led_blink_set(phydev, index, blinking); 748 if (err) 749 return err; 750 751 /* led-blink set, so switch led-on off */ 752 err = air_hw_led_on_set(phydev, index, false); 753 if (err) 754 return err; 755 756 /* hw-control is off*/ 757 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state)) 758 priv->led[index].rules = 0; 759 760 return 0; 761 } 762 763 static int air_led_brightness_set(struct phy_device *phydev, u8 index, 764 enum led_brightness value) 765 { 766 struct en8811h_priv *priv = phydev->priv; 767 int err; 768 769 if (index >= EN8811H_LED_COUNT) 770 return -EINVAL; 771 772 /* led-on set, so switch led-blink off */ 773 err = air_hw_led_blink_set(phydev, index, false); 774 if (err) 775 return err; 776 777 err = air_hw_led_on_set(phydev, index, (value != LED_OFF)); 778 if (err) 779 return err; 780 781 /* hw-control is off */ 782 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state)) 783 priv->led[index].rules = 0; 784 785 return 0; 786 } 787 788 static int air_led_hw_control_get(struct phy_device *phydev, u8 index, 789 unsigned long *rules) 790 { 791 struct en8811h_priv *priv = phydev->priv; 792 793 if (index >= EN8811H_LED_COUNT) 794 return -EINVAL; 795 796 *rules = priv->led[index].rules; 797 798 return 0; 799 }; 800 801 static int air_led_hw_control_set(struct phy_device *phydev, u8 index, 802 unsigned long rules) 803 { 804 struct en8811h_priv *priv = phydev->priv; 805 u16 on = 0, blink = 0; 806 int ret; 807 808 if (index >= EN8811H_LED_COUNT) 809 return -EINVAL; 810 811 priv->led[index].rules = rules; 812 813 if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 814 on |= AIR_PHY_LED_ON_FDX; 815 816 if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 817 on |= AIR_PHY_LED_ON_LINK10; 818 819 if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 820 on |= AIR_PHY_LED_ON_LINK100; 821 822 if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 823 on |= AIR_PHY_LED_ON_LINK1000; 824 825 if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) 826 on |= AIR_PHY_LED_ON_LINK2500; 827 828 if (rules & BIT(TRIGGER_NETDEV_RX)) { 829 blink |= AIR_PHY_LED_BLINK_10RX | 830 AIR_PHY_LED_BLINK_100RX | 831 AIR_PHY_LED_BLINK_1000RX | 832 AIR_PHY_LED_BLINK_2500RX; 833 } 834 835 if (rules & BIT(TRIGGER_NETDEV_TX)) { 836 blink |= AIR_PHY_LED_BLINK_10TX | 837 AIR_PHY_LED_BLINK_100TX | 838 AIR_PHY_LED_BLINK_1000TX | 839 AIR_PHY_LED_BLINK_2500TX; 840 } 841 842 if (blink || on) { 843 /* switch hw-control on, so led-on and led-blink are off */ 844 clear_bit(AIR_PHY_LED_STATE_FORCE_ON, 845 &priv->led[index].state); 846 clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 847 &priv->led[index].state); 848 } else { 849 priv->led[index].rules = 0; 850 } 851 852 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), 853 AIR_PHY_LED_ON_MASK, on); 854 855 if (ret < 0) 856 return ret; 857 858 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), 859 blink); 860 }; 861 862 static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) 863 { 864 int val = 0; 865 int err; 866 867 if (index >= EN8811H_LED_COUNT) 868 return -EINVAL; 869 870 if (state == AIR_LED_ENABLE) 871 val |= AIR_PHY_LED_ON_ENABLE; 872 else 873 val &= ~AIR_PHY_LED_ON_ENABLE; 874 875 if (pol == AIR_ACTIVE_HIGH) 876 val |= AIR_PHY_LED_ON_POLARITY; 877 else 878 val &= ~AIR_PHY_LED_ON_POLARITY; 879 880 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), 881 AIR_PHY_LED_ON_ENABLE | 882 AIR_PHY_LED_ON_POLARITY, val); 883 884 if (err < 0) 885 return err; 886 887 return 0; 888 } 889 890 static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode) 891 { 892 struct en8811h_priv *priv = phydev->priv; 893 int ret, i; 894 895 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, 896 dur); 897 if (ret < 0) 898 return ret; 899 900 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, 901 dur >> 1); 902 if (ret < 0) 903 return ret; 904 905 switch (mode) { 906 case AIR_LED_MODE_DISABLE: 907 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, 908 AIR_PHY_LED_BCR_EXT_CTRL | 909 AIR_PHY_LED_BCR_MODE_MASK, 0); 910 if (ret < 0) 911 return ret; 912 break; 913 case AIR_LED_MODE_USER_DEFINE: 914 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, 915 AIR_PHY_LED_BCR_EXT_CTRL | 916 AIR_PHY_LED_BCR_CLK_EN, 917 AIR_PHY_LED_BCR_EXT_CTRL | 918 AIR_PHY_LED_BCR_CLK_EN); 919 if (ret < 0) 920 return ret; 921 break; 922 default: 923 phydev_err(phydev, "LED mode %d is not supported\n", mode); 924 return -EINVAL; 925 } 926 927 for (i = 0; i < num; ++i) { 928 ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH); 929 if (ret < 0) { 930 phydev_err(phydev, "LED%d init failed: %d\n", i, ret); 931 return ret; 932 } 933 air_led_hw_control_set(phydev, i, priv->led[i].rules); 934 } 935 936 return 0; 937 } 938 939 static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index, 940 unsigned long rules) 941 { 942 if (index >= EN8811H_LED_COUNT) 943 return -EINVAL; 944 945 /* All combinations of the supported triggers are allowed */ 946 if (rules & ~en8811h_led_trig) 947 return -EOPNOTSUPP; 948 949 return 0; 950 }; 951 952 static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw, 953 unsigned long parent) 954 { 955 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 956 struct phy_device *phydev = priv->phydev; 957 u32 pbus_value; 958 int ret; 959 960 ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); 961 if (ret < 0) 962 return ret; 963 964 return (pbus_value & AN8811HB_HWTRAP2_CKO) ? 50000000 : 25000000; 965 } 966 967 static int an8811hb_clk_enable(struct clk_hw *hw) 968 { 969 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 970 struct phy_device *phydev = priv->phydev; 971 972 return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, 973 AN8811HB_CLK_DRV_CKO_MASK, 974 AN8811HB_CLK_DRV_CKO_MASK); 975 } 976 977 static void an8811hb_clk_disable(struct clk_hw *hw) 978 { 979 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 980 struct phy_device *phydev = priv->phydev; 981 982 air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, 983 AN8811HB_CLK_DRV_CKO_MASK, 0); 984 } 985 986 static int an8811hb_clk_is_enabled(struct clk_hw *hw) 987 { 988 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 989 struct phy_device *phydev = priv->phydev; 990 u32 pbus_value; 991 int ret; 992 993 ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value); 994 if (ret < 0) 995 return ret; 996 997 return (pbus_value & AN8811HB_CLK_DRV_CKO_MASK); 998 } 999 1000 static int an8811hb_clk_save_context(struct clk_hw *hw) 1001 { 1002 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1003 1004 priv->cko_is_enabled = an8811hb_clk_is_enabled(hw); 1005 1006 return 0; 1007 } 1008 1009 static void an8811hb_clk_restore_context(struct clk_hw *hw) 1010 { 1011 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1012 1013 if (!priv->cko_is_enabled) 1014 an8811hb_clk_disable(hw); 1015 } 1016 1017 static const struct clk_ops an8811hb_clk_ops = { 1018 .recalc_rate = an8811hb_clk_recalc_rate, 1019 .enable = an8811hb_clk_enable, 1020 .disable = an8811hb_clk_disable, 1021 .is_enabled = an8811hb_clk_is_enabled, 1022 .save_context = an8811hb_clk_save_context, 1023 .restore_context = an8811hb_clk_restore_context, 1024 }; 1025 1026 static int an8811hb_clk_provider_setup(struct device *dev, struct clk_hw *hw) 1027 { 1028 struct clk_init_data init; 1029 int ret; 1030 1031 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1032 return 0; 1033 1034 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko", 1035 fwnode_get_name(dev_fwnode(dev))); 1036 if (!init.name) 1037 return -ENOMEM; 1038 1039 init.ops = &an8811hb_clk_ops; 1040 init.flags = 0; 1041 init.num_parents = 0; 1042 hw->init = &init; 1043 1044 ret = devm_clk_hw_register(dev, hw); 1045 if (ret) 1046 return ret; 1047 1048 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 1049 } 1050 1051 static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw, 1052 unsigned long parent) 1053 { 1054 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1055 struct phy_device *phydev = priv->phydev; 1056 u32 pbus_value; 1057 int ret; 1058 1059 ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value); 1060 if (ret < 0) 1061 return ret; 1062 1063 return (pbus_value & EN8811H_HWTRAP1_CKO) ? 50000000 : 25000000; 1064 } 1065 1066 static int en8811h_clk_enable(struct clk_hw *hw) 1067 { 1068 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1069 struct phy_device *phydev = priv->phydev; 1070 1071 return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM, 1072 EN8811H_CLK_CGM_CKO, 1073 EN8811H_CLK_CGM_CKO); 1074 } 1075 1076 static void en8811h_clk_disable(struct clk_hw *hw) 1077 { 1078 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1079 struct phy_device *phydev = priv->phydev; 1080 1081 air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM, 1082 EN8811H_CLK_CGM_CKO, 0); 1083 } 1084 1085 static int en8811h_clk_is_enabled(struct clk_hw *hw) 1086 { 1087 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1088 struct phy_device *phydev = priv->phydev; 1089 u32 pbus_value; 1090 int ret; 1091 1092 ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value); 1093 if (ret < 0) 1094 return ret; 1095 1096 return (pbus_value & EN8811H_CLK_CGM_CKO); 1097 } 1098 1099 static int en8811h_clk_save_context(struct clk_hw *hw) 1100 { 1101 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1102 1103 priv->cko_is_enabled = en8811h_clk_is_enabled(hw); 1104 1105 return 0; 1106 } 1107 1108 static void en8811h_clk_restore_context(struct clk_hw *hw) 1109 { 1110 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1111 1112 if (!priv->cko_is_enabled) 1113 en8811h_clk_disable(hw); 1114 } 1115 1116 static const struct clk_ops en8811h_clk_ops = { 1117 .recalc_rate = en8811h_clk_recalc_rate, 1118 .enable = en8811h_clk_enable, 1119 .disable = en8811h_clk_disable, 1120 .is_enabled = en8811h_clk_is_enabled, 1121 .save_context = en8811h_clk_save_context, 1122 .restore_context = en8811h_clk_restore_context, 1123 }; 1124 1125 static int en8811h_clk_provider_setup(struct device *dev, struct clk_hw *hw) 1126 { 1127 struct clk_init_data init; 1128 int ret; 1129 1130 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1131 return 0; 1132 1133 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko", 1134 fwnode_get_name(dev_fwnode(dev))); 1135 if (!init.name) 1136 return -ENOMEM; 1137 1138 init.ops = &en8811h_clk_ops; 1139 init.flags = 0; 1140 init.num_parents = 0; 1141 hw->init = &init; 1142 1143 ret = devm_clk_hw_register(dev, hw); 1144 if (ret) 1145 return ret; 1146 1147 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 1148 } 1149 1150 static int en8811h_leds_setup(struct phy_device *phydev) 1151 { 1152 struct en8811h_priv *priv = phydev->priv; 1153 int ret; 1154 1155 priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; 1156 priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; 1157 priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; 1158 1159 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1160 AIR_LED_MODE_DISABLE); 1161 if (ret < 0) 1162 phydev_err(phydev, "Failed to disable leds: %d\n", ret); 1163 1164 return ret; 1165 } 1166 1167 static int an8811hb_probe(struct phy_device *phydev) 1168 { 1169 struct en8811h_priv *priv; 1170 int ret; 1171 1172 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), 1173 GFP_KERNEL); 1174 if (!priv) 1175 return -ENOMEM; 1176 phydev->priv = priv; 1177 1178 ret = an8811hb_load_firmware(phydev); 1179 if (ret < 0) { 1180 phydev_err(phydev, "Load firmware failed: %d\n", ret); 1181 return ret; 1182 } 1183 1184 en8811h_print_fw_version(phydev); 1185 1186 /* mcu has just restarted after firmware load */ 1187 priv->mcu_needs_restart = false; 1188 1189 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ 1190 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 1191 1192 ret = en8811h_leds_setup(phydev); 1193 if (ret < 0) 1194 return ret; 1195 1196 priv->phydev = phydev; 1197 /* Co-Clock Output */ 1198 ret = an8811hb_clk_provider_setup(&phydev->mdio.dev, &priv->hw); 1199 if (ret) 1200 return ret; 1201 1202 /* Configure led gpio pins as output */ 1203 ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, 1204 AN8811HB_GPIO_OUTPUT_345, 1205 AN8811HB_GPIO_OUTPUT_345); 1206 if (ret < 0) 1207 return ret; 1208 1209 return 0; 1210 } 1211 1212 static int en8811h_probe(struct phy_device *phydev) 1213 { 1214 struct en8811h_priv *priv; 1215 int ret; 1216 1217 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), 1218 GFP_KERNEL); 1219 if (!priv) 1220 return -ENOMEM; 1221 phydev->priv = priv; 1222 1223 ret = en8811h_load_firmware(phydev); 1224 if (ret < 0) 1225 return ret; 1226 1227 /* mcu has just restarted after firmware load */ 1228 priv->mcu_needs_restart = false; 1229 1230 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ 1231 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 1232 1233 ret = en8811h_leds_setup(phydev); 1234 if (ret < 0) 1235 return ret; 1236 1237 priv->phydev = phydev; 1238 /* Co-Clock Output */ 1239 ret = en8811h_clk_provider_setup(&phydev->mdio.dev, &priv->hw); 1240 if (ret) 1241 return ret; 1242 1243 /* Configure led gpio pins as output */ 1244 ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT, 1245 EN8811H_GPIO_OUTPUT_345, 1246 EN8811H_GPIO_OUTPUT_345); 1247 if (ret < 0) 1248 return ret; 1249 1250 return 0; 1251 } 1252 1253 static int an8811hb_config_serdes_polarity(struct phy_device *phydev) 1254 { 1255 struct device *dev = &phydev->mdio.dev; 1256 u32 pbus_value = 0; 1257 unsigned int pol; 1258 int ret; 1259 1260 ret = phy_get_manual_rx_polarity(dev_fwnode(dev), 1261 phy_modes(phydev->interface), &pol); 1262 if (ret) 1263 return ret; 1264 if (pol == PHY_POL_NORMAL) 1265 pbus_value |= AN8811HB_RX_POLARITY_NORMAL; 1266 ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, 1267 AN8811HB_RX_POLARITY_NORMAL, 1268 pbus_value); 1269 if (ret < 0) 1270 return ret; 1271 1272 ret = phy_get_manual_tx_polarity(dev_fwnode(dev), 1273 phy_modes(phydev->interface), &pol); 1274 if (ret) 1275 return ret; 1276 pbus_value = 0; 1277 if (pol == PHY_POL_NORMAL) 1278 pbus_value |= AN8811HB_TX_POLARITY_NORMAL; 1279 return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, 1280 AN8811HB_TX_POLARITY_NORMAL, 1281 pbus_value); 1282 } 1283 1284 static int en8811h_config_serdes_polarity(struct phy_device *phydev) 1285 { 1286 struct device *dev = &phydev->mdio.dev; 1287 unsigned int pol, default_pol; 1288 u32 pbus_value = 0; 1289 int ret; 1290 1291 default_pol = PHY_POL_NORMAL; 1292 if (device_property_read_bool(dev, "airoha,pnswap-rx")) 1293 default_pol = PHY_POL_INVERT; 1294 1295 ret = phy_get_rx_polarity(dev_fwnode(dev), phy_modes(phydev->interface), 1296 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), 1297 default_pol, &pol); 1298 if (ret) 1299 return ret; 1300 if (pol == PHY_POL_INVERT) 1301 pbus_value |= EN8811H_POLARITY_RX_REVERSE; 1302 1303 default_pol = PHY_POL_NORMAL; 1304 if (device_property_read_bool(dev, "airoha,pnswap-tx")) 1305 default_pol = PHY_POL_INVERT; 1306 1307 ret = phy_get_tx_polarity(dev_fwnode(dev), phy_modes(phydev->interface), 1308 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), 1309 default_pol, &pol); 1310 if (ret) 1311 return ret; 1312 if (pol == PHY_POL_NORMAL) 1313 pbus_value |= EN8811H_POLARITY_TX_NORMAL; 1314 1315 return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, 1316 EN8811H_POLARITY_RX_REVERSE | 1317 EN8811H_POLARITY_TX_NORMAL, pbus_value); 1318 } 1319 1320 static int an8811hb_config_init(struct phy_device *phydev) 1321 { 1322 struct en8811h_priv *priv = phydev->priv; 1323 int ret; 1324 1325 /* If restart happened in .probe(), no need to restart now */ 1326 if (priv->mcu_needs_restart) { 1327 ret = en8811h_restart_mcu(phydev); 1328 if (ret < 0) 1329 return ret; 1330 } else { 1331 /* Next calls to .config_init() mcu needs to restart */ 1332 priv->mcu_needs_restart = true; 1333 } 1334 1335 ret = an8811hb_config_serdes_polarity(phydev); 1336 if (ret < 0) 1337 return ret; 1338 1339 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1340 AIR_LED_MODE_USER_DEFINE); 1341 if (ret < 0) 1342 phydev_err(phydev, "Failed to initialize leds: %d\n", ret); 1343 1344 return ret; 1345 } 1346 1347 static int en8811h_config_init(struct phy_device *phydev) 1348 { 1349 struct en8811h_priv *priv = phydev->priv; 1350 int ret; 1351 1352 /* If restart happened in .probe(), no need to restart now */ 1353 if (priv->mcu_needs_restart) { 1354 ret = en8811h_restart_mcu(phydev); 1355 if (ret < 0) 1356 return ret; 1357 } else { 1358 /* Next calls to .config_init() mcu needs to restart */ 1359 priv->mcu_needs_restart = true; 1360 } 1361 1362 /* Select mode 1, the only mode supported. 1363 * Configures the SerDes for 2500Base-X with rate adaptation 1364 */ 1365 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, 1366 AIR_PHY_MCU_CMD_1_MODE1); 1367 if (ret < 0) 1368 return ret; 1369 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, 1370 AIR_PHY_MCU_CMD_2_MODE1); 1371 if (ret < 0) 1372 return ret; 1373 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, 1374 AIR_PHY_MCU_CMD_3_MODE1); 1375 if (ret < 0) 1376 return ret; 1377 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, 1378 AIR_PHY_MCU_CMD_4_MODE1); 1379 if (ret < 0) 1380 return ret; 1381 1382 ret = en8811h_config_serdes_polarity(phydev); 1383 if (ret < 0) 1384 return ret; 1385 1386 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1387 AIR_LED_MODE_USER_DEFINE); 1388 if (ret < 0) { 1389 phydev_err(phydev, "Failed to initialize leds: %d\n", ret); 1390 return ret; 1391 } 1392 1393 return 0; 1394 } 1395 1396 static int en8811h_get_features(struct phy_device *phydev) 1397 { 1398 linkmode_set_bit_array(phy_basic_ports_array, 1399 ARRAY_SIZE(phy_basic_ports_array), 1400 phydev->supported); 1401 1402 return genphy_c45_pma_read_abilities(phydev); 1403 } 1404 1405 static int en8811h_get_rate_matching(struct phy_device *phydev, 1406 phy_interface_t iface) 1407 { 1408 return RATE_MATCH_PAUSE; 1409 } 1410 1411 static int en8811h_config_aneg(struct phy_device *phydev) 1412 { 1413 bool changed = false; 1414 int ret; 1415 u32 adv; 1416 1417 if (phydev->autoneg == AUTONEG_DISABLE) { 1418 phydev_warn(phydev, "Disabling autoneg is not supported\n"); 1419 return -EINVAL; 1420 } 1421 1422 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1423 1424 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1425 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 1426 if (ret < 0) 1427 return ret; 1428 if (ret > 0) 1429 changed = true; 1430 1431 return __genphy_config_aneg(phydev, changed); 1432 } 1433 1434 static int en8811h_read_status(struct phy_device *phydev) 1435 { 1436 struct en8811h_priv *priv = phydev->priv; 1437 u32 pbus_value; 1438 int ret, val; 1439 1440 ret = genphy_update_link(phydev); 1441 if (ret) 1442 return ret; 1443 1444 phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED; 1445 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1446 phydev->speed = SPEED_UNKNOWN; 1447 phydev->duplex = DUPLEX_UNKNOWN; 1448 phydev->pause = 0; 1449 phydev->asym_pause = 0; 1450 phydev->rate_matching = RATE_MATCH_PAUSE; 1451 1452 ret = genphy_read_master_slave(phydev); 1453 if (ret < 0) 1454 return ret; 1455 1456 ret = genphy_read_lpa(phydev); 1457 if (ret < 0) 1458 return ret; 1459 1460 if (phy_id_compare_model(phydev->phy_id, AN8811HB_PHY_ID)) { 1461 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1462 if (val < 0) 1463 return val; 1464 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1465 phydev->lp_advertising, 1466 val & MDIO_AN_10GBT_STAT_LP2_5G); 1467 } else { 1468 /* Get link partner 2.5GBASE-T ability from vendor register */ 1469 ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, 1470 &pbus_value); 1471 if (ret < 0) 1472 return ret; 1473 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1474 phydev->lp_advertising, 1475 pbus_value & EN8811H_2P5G_LPA_2P5G); 1476 } 1477 1478 if (phydev->autoneg_complete) 1479 phy_resolve_aneg_pause(phydev); 1480 1481 if (!phydev->link) 1482 return 0; 1483 1484 /* Get real speed from vendor register */ 1485 val = phy_read(phydev, AIR_AUX_CTRL_STATUS); 1486 if (val < 0) 1487 return val; 1488 switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) { 1489 case AIR_AUX_CTRL_STATUS_SPEED_2500: 1490 phydev->speed = SPEED_2500; 1491 break; 1492 case AIR_AUX_CTRL_STATUS_SPEED_1000: 1493 phydev->speed = SPEED_1000; 1494 break; 1495 case AIR_AUX_CTRL_STATUS_SPEED_100: 1496 phydev->speed = SPEED_100; 1497 break; 1498 case AIR_AUX_CTRL_STATUS_SPEED_10: 1499 phydev->speed = SPEED_10; 1500 break; 1501 } 1502 1503 /* Firmware before version 24011202 has no vendor register 2P5G_LPA. 1504 * Assume link partner advertised it if connected at 2500Mbps. 1505 */ 1506 if (priv->firmware_version < 0x24011202) { 1507 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1508 phydev->lp_advertising, 1509 phydev->speed == SPEED_2500); 1510 } 1511 1512 /* Only supports full duplex */ 1513 phydev->duplex = DUPLEX_FULL; 1514 1515 return 0; 1516 } 1517 1518 static int en8811h_clear_intr(struct phy_device *phydev) 1519 { 1520 int ret; 1521 1522 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, 1523 AIR_PHY_MCU_CMD_3_DOCMD); 1524 if (ret < 0) 1525 return ret; 1526 1527 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, 1528 AIR_PHY_MCU_CMD_4_INTCLR); 1529 if (ret < 0) 1530 return ret; 1531 1532 return 0; 1533 } 1534 1535 static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev) 1536 { 1537 int ret; 1538 1539 ret = en8811h_clear_intr(phydev); 1540 if (ret < 0) { 1541 phy_error(phydev); 1542 return IRQ_NONE; 1543 } 1544 1545 phy_trigger_machine(phydev); 1546 1547 return IRQ_HANDLED; 1548 } 1549 1550 static int en8811h_resume(struct phy_device *phydev) 1551 { 1552 clk_restore_context(); 1553 1554 return genphy_resume(phydev); 1555 } 1556 1557 static int en8811h_suspend(struct phy_device *phydev) 1558 { 1559 clk_save_context(); 1560 1561 return genphy_suspend(phydev); 1562 } 1563 1564 static struct phy_driver en8811h_driver[] = { 1565 { 1566 PHY_ID_MATCH_MODEL(EN8811H_PHY_ID), 1567 .name = "Airoha EN8811H", 1568 .probe = en8811h_probe, 1569 .get_features = en8811h_get_features, 1570 .config_init = en8811h_config_init, 1571 .get_rate_matching = en8811h_get_rate_matching, 1572 .config_aneg = en8811h_config_aneg, 1573 .read_status = en8811h_read_status, 1574 .resume = en8811h_resume, 1575 .suspend = en8811h_suspend, 1576 .config_intr = en8811h_clear_intr, 1577 .handle_interrupt = en8811h_handle_interrupt, 1578 .led_hw_is_supported = en8811h_led_hw_is_supported, 1579 .read_page = air_phy_read_page, 1580 .write_page = air_phy_write_page, 1581 .led_blink_set = air_led_blink_set, 1582 .led_brightness_set = air_led_brightness_set, 1583 .led_hw_control_set = air_led_hw_control_set, 1584 .led_hw_control_get = air_led_hw_control_get, 1585 }, 1586 { 1587 PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID), 1588 .name = "Airoha AN8811HB", 1589 .probe = an8811hb_probe, 1590 .get_features = en8811h_get_features, 1591 .config_init = an8811hb_config_init, 1592 .get_rate_matching = en8811h_get_rate_matching, 1593 .config_aneg = en8811h_config_aneg, 1594 .read_status = en8811h_read_status, 1595 .resume = en8811h_resume, 1596 .suspend = en8811h_suspend, 1597 .config_intr = en8811h_clear_intr, 1598 .handle_interrupt = en8811h_handle_interrupt, 1599 .led_hw_is_supported = en8811h_led_hw_is_supported, 1600 .read_page = air_phy_read_page, 1601 .write_page = air_phy_write_page, 1602 .led_blink_set = air_led_blink_set, 1603 .led_brightness_set = air_led_brightness_set, 1604 .led_hw_control_set = air_led_hw_control_set, 1605 .led_hw_control_get = air_led_hw_control_get, 1606 } }; 1607 1608 module_phy_driver(en8811h_driver); 1609 1610 static const struct mdio_device_id __maybe_unused en8811h_tbl[] = { 1611 { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, 1612 { PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID) }, 1613 { } 1614 }; 1615 1616 MODULE_DEVICE_TABLE(mdio, en8811h_tbl); 1617 MODULE_FIRMWARE(EN8811H_MD32_DM); 1618 MODULE_FIRMWARE(EN8811H_MD32_DSP); 1619 MODULE_FIRMWARE(AN8811HB_MD32_DM); 1620 MODULE_FIRMWARE(AN8811HB_MD32_DSP); 1621 1622 MODULE_DESCRIPTION("Airoha EN8811H and AN8811HB PHY drivers"); 1623 MODULE_AUTHOR("Airoha"); 1624 MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>"); 1625 MODULE_LICENSE("GPL"); 1626