1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHYs. 4 * 5 * Limitations: 6 * - Only full duplex supported 7 * - Forced speed (AN off) is not supported by hardware (100Mbps) 8 * 9 * Source originated from airoha's en8811h.c and en8811h.h v1.2.1 10 * with AN8811HB bits from air_an8811hb.c v0.0.4 11 * 12 * Copyright (C) 2023, 2026 Airoha Technology Corp. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/phy.h> 18 #include <linux/phy/phy-common-props.h> 19 #include <linux/firmware.h> 20 #include <linux/bitfield.h> 21 #include <linux/property.h> 22 #include <linux/wordpart.h> 23 #include <linux/unaligned.h> 24 25 #include "air_phy_lib.h" 26 27 #define EN8811H_PHY_ID 0x03a2a411 28 #define AN8811HB_PHY_ID 0xc0ff04a0 29 30 #define EN8811H_MD32_DM "airoha/EthMD32.dm.bin" 31 #define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin" 32 #define AN8811HB_MD32_DM "airoha/an8811hb/EthMD32_CRC.DM.bin" 33 #define AN8811HB_MD32_DSP "airoha/an8811hb/EthMD32_CRC.DSP.bin" 34 35 #define AIR_FW_ADDR_DM 0x00000000 36 #define AIR_FW_ADDR_DSP 0x00100000 37 38 /* MII Registers */ 39 #define AIR_AUX_CTRL_STATUS 0x1d 40 #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) 41 #define AIR_AUX_CTRL_STATUS_SPEED_10 0x0 42 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 43 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 44 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc 45 46 /* Registers on MDIO_MMD_VEND1 */ 47 #define EN8811H_PHY_FW_STATUS 0x8009 48 #define EN8811H_PHY_READY 0x02 49 50 #define AIR_PHY_MCU_CMD_0 0x800b 51 #define AIR_PHY_MCU_CMD_1 0x800c 52 #define AIR_PHY_MCU_CMD_1_MODE1 0x0 53 #define AIR_PHY_MCU_CMD_2 0x800d 54 #define AIR_PHY_MCU_CMD_2_MODE1 0x0 55 #define AIR_PHY_MCU_CMD_3 0x800e 56 #define AIR_PHY_MCU_CMD_3_MODE1 0x1101 57 #define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 58 #define AIR_PHY_MCU_CMD_4 0x800f 59 #define AIR_PHY_MCU_CMD_4_MODE1 0x0002 60 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_A 0x00d7 61 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_B 0x00d8 62 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_C 0x00d9 63 #define AIR_PHY_MCU_CMD_4_CABLE_PAIR_D 0x00da 64 #define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 65 66 /* Registers on MDIO_MMD_VEND2 */ 67 #define AIR_PHY_LED_BCR 0x021 68 #define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0) 69 #define AIR_PHY_LED_BCR_TIME_TEST BIT(2) 70 #define AIR_PHY_LED_BCR_CLK_EN BIT(3) 71 #define AIR_PHY_LED_BCR_EXT_CTRL BIT(15) 72 73 #define AIR_PHY_LED_DUR_ON 0x022 74 75 #define AIR_PHY_LED_DUR_BLINK 0x023 76 77 #define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) 78 #define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8)) 79 #define AIR_PHY_LED_ON_LINK1000 BIT(0) 80 #define AIR_PHY_LED_ON_LINK100 BIT(1) 81 #define AIR_PHY_LED_ON_LINK10 BIT(2) 82 #define AIR_PHY_LED_ON_LINKDOWN BIT(3) 83 #define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 84 #define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 85 #define AIR_PHY_LED_ON_FORCE_ON BIT(6) 86 #define AIR_PHY_LED_ON_LINK2500 BIT(8) 87 #define AIR_PHY_LED_ON_POLARITY BIT(14) 88 #define AIR_PHY_LED_ON_ENABLE BIT(15) 89 90 #define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) 91 #define AIR_PHY_LED_BLINK_1000TX BIT(0) 92 #define AIR_PHY_LED_BLINK_1000RX BIT(1) 93 #define AIR_PHY_LED_BLINK_100TX BIT(2) 94 #define AIR_PHY_LED_BLINK_100RX BIT(3) 95 #define AIR_PHY_LED_BLINK_10TX BIT(4) 96 #define AIR_PHY_LED_BLINK_10RX BIT(5) 97 #define AIR_PHY_LED_BLINK_COLLISION BIT(6) 98 #define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 99 #define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 100 #define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9) 101 #define AIR_PHY_LED_BLINK_2500TX BIT(10) 102 #define AIR_PHY_LED_BLINK_2500RX BIT(11) 103 104 /* Registers on BUCKPBUS */ 105 #define AIR_PHY_CONTROL 0x3a9c 106 #define AIR_PHY_CONTROL_INTERNAL BIT(11) 107 108 #define EN8811H_2P5G_LPA 0x3b30 109 #define EN8811H_2P5G_LPA_2P5G BIT(0) 110 111 #define EN8811H_FW_VERSION 0x3b3c 112 113 #define EN8811H_POLARITY 0xca0f8 114 #define EN8811H_POLARITY_TX_NORMAL BIT(0) 115 #define EN8811H_POLARITY_RX_REVERSE BIT(1) 116 117 #define EN8811H_GPIO_OUTPUT 0xcf8b8 118 #define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) 119 120 #define EN8811H_HWTRAP1 0xcf914 121 #define EN8811H_HWTRAP1_CKO BIT(12) 122 #define EN8811H_CLK_CGM 0xcf958 123 #define EN8811H_CLK_CGM_CKO BIT(26) 124 125 #define EN8811H_FW_CTRL_1 0x0f0018 126 #define EN8811H_FW_CTRL_1_START 0x0 127 #define EN8811H_FW_CTRL_1_FINISH 0x1 128 #define EN8811H_FW_CTRL_2 0x800000 129 #define EN8811H_FW_CTRL_2_LOADING BIT(11) 130 131 #define AN8811HB_CRC_PM_SET1 0xf020c 132 #define AN8811HB_CRC_PM_MON2 0xf0218 133 #define AN8811HB_CRC_PM_MON3 0xf021c 134 #define AN8811HB_CRC_DM_SET1 0xf0224 135 #define AN8811HB_CRC_DM_MON2 0xf0230 136 #define AN8811HB_CRC_DM_MON3 0xf0234 137 #define AN8811HB_CRC_RD_EN BIT(0) 138 #define AN8811HB_CRC_ST (BIT(0) | BIT(1)) 139 #define AN8811HB_CRC_CHECK_PASS BIT(0) 140 141 #define AN8811HB_TX_POLARITY 0x5ce004 142 #define AN8811HB_TX_POLARITY_NORMAL BIT(7) 143 #define AN8811HB_RX_POLARITY 0x5ce61c 144 #define AN8811HB_RX_POLARITY_NORMAL BIT(7) 145 146 #define AN8811HB_GPIO_OUTPUT 0x5cf8b8 147 #define AN8811HB_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) 148 149 #define AN8811HB_HWTRAP1 0x5cf910 150 #define AN8811HB_HWTRAP2 0x5cf914 151 #define AN8811HB_HWTRAP2_CKO BIT(28) 152 153 #define AN8811HB_CLK_DRV 0x5cf9e4 154 #define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12) 155 #define AN8811HB_CLK_DRV_CKOPWD BIT(12) 156 #define AN8811HB_CLK_DRV_CKO_LDPWD BIT(13) 157 #define AN8811HB_CLK_DRV_CKO_LPPWD BIT(14) 158 159 #define AN8811HB_MCU_SW_RST 0x5cf9f8 160 #define AN8811HB_MCU_SW_RST_HOLD BIT(16) 161 #define AN8811HB_MCU_SW_RST_RUN (BIT(16) | BIT(0)) 162 #define AN8811HB_MCU_SW_START 0x5cf9fc 163 #define AN8811HB_MCU_SW_START_EN BIT(16) 164 165 /* MII register constants for PBUS access (PHY addr + 8) */ 166 #define AIR_PBUS_ADDR_HIGH 0x1c 167 #define AIR_PBUS_DATA_HIGH 0x10 168 #define AIR_PBUS_REG_ADDR_HIGH_MASK GENMASK(15, 6) 169 #define AIR_PBUS_REG_ADDR_LOW_MASK GENMASK(5, 2) 170 171 /* Led definitions */ 172 #define EN8811H_LED_COUNT 3 173 174 #define EN8811H_PBUS_ADDR_OFFS 8 175 176 /* Default LED setup: 177 * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx 178 * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps 179 * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps 180 */ 181 #define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \ 182 BIT(TRIGGER_NETDEV_RX) | \ 183 BIT(TRIGGER_NETDEV_TX)) 184 #define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \ 185 BIT(TRIGGER_NETDEV_LINK_1000)) 186 #define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \ 187 BIT(TRIGGER_NETDEV_LINK_100)) 188 189 struct led { 190 unsigned long rules; 191 unsigned long state; 192 }; 193 194 #define clk_hw_to_en8811h_priv(_hw) \ 195 container_of(_hw, struct en8811h_priv, hw) 196 197 struct en8811h_priv { 198 u32 firmware_version; 199 bool mcu_needs_restart; 200 struct led led[EN8811H_LED_COUNT]; 201 struct clk_hw hw; 202 struct phy_device *phydev; 203 unsigned int cko_is_enabled; 204 struct mdio_device *pbusdev; 205 }; 206 207 enum { 208 AIR_PHY_LED_STATE_FORCE_ON, 209 AIR_PHY_LED_STATE_FORCE_BLINK, 210 }; 211 212 enum { 213 AIR_PHY_LED_DUR_BLINK_32MS, 214 AIR_PHY_LED_DUR_BLINK_64MS, 215 AIR_PHY_LED_DUR_BLINK_128MS, 216 AIR_PHY_LED_DUR_BLINK_256MS, 217 AIR_PHY_LED_DUR_BLINK_512MS, 218 AIR_PHY_LED_DUR_BLINK_1024MS, 219 }; 220 221 enum { 222 AIR_LED_DISABLE, 223 AIR_LED_ENABLE, 224 }; 225 226 enum { 227 AIR_ACTIVE_LOW, 228 AIR_ACTIVE_HIGH, 229 }; 230 231 enum { 232 AIR_LED_MODE_DISABLE, 233 AIR_LED_MODE_USER_DEFINE, 234 }; 235 236 #define AIR_PHY_LED_DUR_UNIT 1024 237 #define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) 238 239 static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 240 BIT(TRIGGER_NETDEV_LINK) | 241 BIT(TRIGGER_NETDEV_LINK_10) | 242 BIT(TRIGGER_NETDEV_LINK_100) | 243 BIT(TRIGGER_NETDEV_LINK_1000) | 244 BIT(TRIGGER_NETDEV_LINK_2500) | 245 BIT(TRIGGER_NETDEV_RX) | 246 BIT(TRIGGER_NETDEV_TX); 247 248 static int __air_pbus_reg_write(struct mdio_device *mdiodev, 249 u32 pbus_reg, u32 pbus_data) 250 { 251 int ret; 252 253 ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_EXT_PAGE_ACCESS, 254 upper_16_bits(pbus_reg)); 255 if (ret < 0) 256 return ret; 257 258 ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_PBUS_ADDR_HIGH, 259 FIELD_GET(AIR_PBUS_REG_ADDR_HIGH_MASK, pbus_reg)); 260 if (ret < 0) 261 return ret; 262 263 ret = __mdiobus_write(mdiodev->bus, mdiodev->addr, 264 FIELD_GET(AIR_PBUS_REG_ADDR_LOW_MASK, pbus_reg), 265 lower_16_bits(pbus_data)); 266 if (ret < 0) 267 return ret; 268 269 return __mdiobus_write(mdiodev->bus, mdiodev->addr, AIR_PBUS_DATA_HIGH, 270 upper_16_bits(pbus_data)); 271 } 272 273 static int __air_write_buf(struct phy_device *phydev, u32 address, 274 const struct firmware *fw) 275 { 276 unsigned int offset; 277 int ret; 278 u16 val; 279 280 ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); 281 if (ret < 0) 282 return ret; 283 284 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, 285 upper_16_bits(address)); 286 if (ret < 0) 287 return ret; 288 289 ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, 290 lower_16_bits(address)); 291 if (ret < 0) 292 return ret; 293 294 for (offset = 0; offset < fw->size; offset += 4) { 295 val = get_unaligned_le16(&fw->data[offset + 2]); 296 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); 297 if (ret < 0) 298 return ret; 299 300 val = get_unaligned_le16(&fw->data[offset]); 301 ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); 302 if (ret < 0) 303 return ret; 304 } 305 306 return 0; 307 } 308 309 static int air_write_buf(struct phy_device *phydev, u32 address, 310 const struct firmware *fw) 311 { 312 int saved_page; 313 int ret = 0; 314 315 saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); 316 317 if (saved_page >= 0) { 318 ret = __air_write_buf(phydev, address, fw); 319 if (ret < 0) 320 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, 321 address, ret); 322 } 323 324 return phy_restore_page(phydev, saved_page, ret); 325 } 326 327 static int en8811h_wait_mcu_ready(struct phy_device *phydev) 328 { 329 int ret, reg_value; 330 331 ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 332 EN8811H_FW_CTRL_1_FINISH); 333 if (ret) 334 return ret; 335 336 /* Because of mdio-lock, may have to wait for multiple loads */ 337 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 338 EN8811H_PHY_FW_STATUS, reg_value, 339 reg_value == EN8811H_PHY_READY, 340 20000, 7500000, true); 341 if (ret) { 342 phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); 343 return -ENODEV; 344 } 345 346 return 0; 347 } 348 349 static int an8811hb_check_crc(struct phy_device *phydev, u32 set1, 350 u32 mon2, u32 mon3) 351 { 352 u32 pbus_value; 353 int retry = 25; 354 int ret; 355 356 /* Configure CRC */ 357 ret = air_phy_buckpbus_reg_modify(phydev, set1, 358 AN8811HB_CRC_RD_EN, 359 AN8811HB_CRC_RD_EN); 360 if (ret < 0) 361 return ret; 362 air_phy_buckpbus_reg_read(phydev, set1, &pbus_value); 363 364 do { 365 msleep(300); 366 air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value); 367 368 /* We do not know what errors this check is supposed 369 * catch or what to do about a failure. So print the 370 * result and continue like the vendor driver does. 371 */ 372 if (pbus_value & AN8811HB_CRC_ST) { 373 air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value); 374 phydev_dbg(phydev, "CRC Check %s!\n", 375 pbus_value & AN8811HB_CRC_CHECK_PASS ? 376 "PASS" : "FAIL"); 377 return air_phy_buckpbus_reg_modify(phydev, set1, 378 AN8811HB_CRC_RD_EN, 379 0); 380 } 381 } while (--retry); 382 383 phydev_err(phydev, "CRC Check is not ready (%u)\n", pbus_value); 384 return -ENODEV; 385 } 386 387 static void en8811h_print_fw_version(struct phy_device *phydev) 388 { 389 struct en8811h_priv *priv = phydev->priv; 390 391 air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, 392 &priv->firmware_version); 393 phydev_info(phydev, "MD32 firmware version: %08x\n", 394 priv->firmware_version); 395 } 396 397 static int an8811hb_load_file(struct phy_device *phydev, const char *name, 398 u32 address) 399 { 400 struct device *dev = &phydev->mdio.dev; 401 const struct firmware *fw; 402 int ret; 403 404 ret = request_firmware_direct(&fw, name, dev); 405 if (ret < 0) 406 return ret; 407 408 ret = air_write_buf(phydev, address, fw); 409 release_firmware(fw); 410 return ret; 411 } 412 413 static int an8811hb_mcu_assert(struct phy_device *phydev) 414 { 415 struct en8811h_priv *priv = phydev->priv; 416 int ret; 417 418 phy_lock_mdio_bus(phydev); 419 420 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_RST, 421 AN8811HB_MCU_SW_RST_HOLD); 422 if (ret < 0) 423 goto unlock; 424 425 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_START, 0); 426 if (ret < 0) 427 goto unlock; 428 429 msleep(50); 430 phydev_dbg(phydev, "MCU asserted\n"); 431 432 unlock: 433 phy_unlock_mdio_bus(phydev); 434 return ret; 435 } 436 437 static int an8811hb_mcu_deassert(struct phy_device *phydev) 438 { 439 struct en8811h_priv *priv = phydev->priv; 440 int ret; 441 442 phy_lock_mdio_bus(phydev); 443 444 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_START, 445 AN8811HB_MCU_SW_START_EN); 446 if (ret < 0) 447 goto unlock; 448 449 ret = __air_pbus_reg_write(priv->pbusdev, AN8811HB_MCU_SW_RST, 450 AN8811HB_MCU_SW_RST_RUN); 451 if (ret < 0) 452 goto unlock; 453 454 msleep(50); 455 phydev_dbg(phydev, "MCU deasserted\n"); 456 457 unlock: 458 phy_unlock_mdio_bus(phydev); 459 return ret; 460 } 461 462 static int an8811hb_load_firmware(struct phy_device *phydev) 463 { 464 int ret; 465 466 ret = an8811hb_mcu_assert(phydev); 467 if (ret < 0) 468 return ret; 469 470 ret = an8811hb_mcu_deassert(phydev); 471 if (ret < 0) 472 return ret; 473 474 ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 475 EN8811H_FW_CTRL_1_START); 476 if (ret < 0) 477 return ret; 478 479 ret = an8811hb_load_file(phydev, AN8811HB_MD32_DM, AIR_FW_ADDR_DM); 480 if (ret < 0) 481 return ret; 482 483 ret = an8811hb_check_crc(phydev, AN8811HB_CRC_DM_SET1, 484 AN8811HB_CRC_DM_MON2, 485 AN8811HB_CRC_DM_MON3); 486 if (ret < 0) 487 return ret; 488 489 ret = an8811hb_load_file(phydev, AN8811HB_MD32_DSP, AIR_FW_ADDR_DSP); 490 if (ret < 0) 491 return ret; 492 493 ret = an8811hb_check_crc(phydev, AN8811HB_CRC_PM_SET1, 494 AN8811HB_CRC_PM_MON2, 495 AN8811HB_CRC_PM_MON3); 496 if (ret < 0) 497 return ret; 498 499 return en8811h_wait_mcu_ready(phydev); 500 } 501 502 static int en8811h_load_firmware(struct phy_device *phydev) 503 { 504 struct device *dev = &phydev->mdio.dev; 505 const struct firmware *fw1, *fw2; 506 int ret; 507 508 ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); 509 if (ret < 0) 510 return ret; 511 512 ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev); 513 if (ret < 0) 514 goto en8811h_load_firmware_rel1; 515 516 ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 517 EN8811H_FW_CTRL_1_START); 518 if (ret < 0) 519 goto en8811h_load_firmware_out; 520 521 ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, 522 EN8811H_FW_CTRL_2_LOADING, 523 EN8811H_FW_CTRL_2_LOADING); 524 if (ret < 0) 525 goto en8811h_load_firmware_out; 526 527 ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1); 528 if (ret < 0) 529 goto en8811h_load_firmware_out; 530 531 ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2); 532 if (ret < 0) 533 goto en8811h_load_firmware_out; 534 535 ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, 536 EN8811H_FW_CTRL_2_LOADING, 0); 537 if (ret < 0) 538 goto en8811h_load_firmware_out; 539 540 ret = en8811h_wait_mcu_ready(phydev); 541 if (ret < 0) 542 goto en8811h_load_firmware_out; 543 544 en8811h_print_fw_version(phydev); 545 546 en8811h_load_firmware_out: 547 release_firmware(fw2); 548 549 en8811h_load_firmware_rel1: 550 release_firmware(fw1); 551 552 if (ret < 0) 553 phydev_err(phydev, "Load firmware failed: %d\n", ret); 554 555 return ret; 556 } 557 558 static int en8811h_restart_mcu(struct phy_device *phydev) 559 { 560 int ret; 561 562 if (phy_id_compare_model(phydev->phy_id, AN8811HB_PHY_ID)) { 563 ret = an8811hb_mcu_assert(phydev); 564 if (ret < 0) 565 return ret; 566 567 ret = an8811hb_mcu_deassert(phydev); 568 if (ret < 0) 569 return ret; 570 } 571 572 ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, 573 EN8811H_FW_CTRL_1_START); 574 if (ret < 0) 575 return ret; 576 577 return en8811h_wait_mcu_ready(phydev); 578 } 579 580 static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on) 581 { 582 struct en8811h_priv *priv = phydev->priv; 583 bool changed; 584 585 if (index >= EN8811H_LED_COUNT) 586 return -EINVAL; 587 588 if (on) 589 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON, 590 &priv->led[index].state); 591 else 592 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON, 593 &priv->led[index].state); 594 595 changed |= (priv->led[index].rules != 0); 596 597 /* clear netdev trigger rules in case LED_OFF has been set */ 598 if (!on) 599 priv->led[index].rules = 0; 600 601 if (changed) 602 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 603 AIR_PHY_LED_ON(index), 604 AIR_PHY_LED_ON_MASK, 605 on ? AIR_PHY_LED_ON_FORCE_ON : 0); 606 607 return 0; 608 } 609 610 static int air_hw_led_blink_set(struct phy_device *phydev, u8 index, 611 bool blinking) 612 { 613 struct en8811h_priv *priv = phydev->priv; 614 bool changed; 615 616 if (index >= EN8811H_LED_COUNT) 617 return -EINVAL; 618 619 if (blinking) 620 changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 621 &priv->led[index].state); 622 else 623 changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 624 &priv->led[index].state); 625 626 changed |= (priv->led[index].rules != 0); 627 628 if (changed) 629 return phy_write_mmd(phydev, MDIO_MMD_VEND2, 630 AIR_PHY_LED_BLINK(index), 631 blinking ? 632 AIR_PHY_LED_BLINK_FORCE_BLINK : 0); 633 else 634 return 0; 635 } 636 637 static int air_led_blink_set(struct phy_device *phydev, u8 index, 638 unsigned long *delay_on, 639 unsigned long *delay_off) 640 { 641 struct en8811h_priv *priv = phydev->priv; 642 bool blinking = false; 643 int err; 644 645 if (index >= EN8811H_LED_COUNT) 646 return -EINVAL; 647 648 if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { 649 blinking = true; 650 *delay_on = 50; 651 *delay_off = 50; 652 } 653 654 err = air_hw_led_blink_set(phydev, index, blinking); 655 if (err) 656 return err; 657 658 /* led-blink set, so switch led-on off */ 659 err = air_hw_led_on_set(phydev, index, false); 660 if (err) 661 return err; 662 663 /* hw-control is off*/ 664 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state)) 665 priv->led[index].rules = 0; 666 667 return 0; 668 } 669 670 static int air_led_brightness_set(struct phy_device *phydev, u8 index, 671 enum led_brightness value) 672 { 673 struct en8811h_priv *priv = phydev->priv; 674 int err; 675 676 if (index >= EN8811H_LED_COUNT) 677 return -EINVAL; 678 679 /* led-on set, so switch led-blink off */ 680 err = air_hw_led_blink_set(phydev, index, false); 681 if (err) 682 return err; 683 684 err = air_hw_led_on_set(phydev, index, (value != LED_OFF)); 685 if (err) 686 return err; 687 688 /* hw-control is off */ 689 if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state)) 690 priv->led[index].rules = 0; 691 692 return 0; 693 } 694 695 static int air_led_hw_control_get(struct phy_device *phydev, u8 index, 696 unsigned long *rules) 697 { 698 struct en8811h_priv *priv = phydev->priv; 699 700 if (index >= EN8811H_LED_COUNT) 701 return -EINVAL; 702 703 *rules = priv->led[index].rules; 704 705 return 0; 706 }; 707 708 static int air_led_hw_control_set(struct phy_device *phydev, u8 index, 709 unsigned long rules) 710 { 711 struct en8811h_priv *priv = phydev->priv; 712 u16 on = 0, blink = 0; 713 int ret; 714 715 if (index >= EN8811H_LED_COUNT) 716 return -EINVAL; 717 718 priv->led[index].rules = rules; 719 720 if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) 721 on |= AIR_PHY_LED_ON_FDX; 722 723 if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) 724 on |= AIR_PHY_LED_ON_LINK10; 725 726 if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) 727 on |= AIR_PHY_LED_ON_LINK100; 728 729 if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) 730 on |= AIR_PHY_LED_ON_LINK1000; 731 732 if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) 733 on |= AIR_PHY_LED_ON_LINK2500; 734 735 if (rules & BIT(TRIGGER_NETDEV_RX)) { 736 blink |= AIR_PHY_LED_BLINK_10RX | 737 AIR_PHY_LED_BLINK_100RX | 738 AIR_PHY_LED_BLINK_1000RX | 739 AIR_PHY_LED_BLINK_2500RX; 740 } 741 742 if (rules & BIT(TRIGGER_NETDEV_TX)) { 743 blink |= AIR_PHY_LED_BLINK_10TX | 744 AIR_PHY_LED_BLINK_100TX | 745 AIR_PHY_LED_BLINK_1000TX | 746 AIR_PHY_LED_BLINK_2500TX; 747 } 748 749 if (blink || on) { 750 /* switch hw-control on, so led-on and led-blink are off */ 751 clear_bit(AIR_PHY_LED_STATE_FORCE_ON, 752 &priv->led[index].state); 753 clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, 754 &priv->led[index].state); 755 } else { 756 priv->led[index].rules = 0; 757 } 758 759 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), 760 AIR_PHY_LED_ON_MASK, on); 761 762 if (ret < 0) 763 return ret; 764 765 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), 766 blink); 767 }; 768 769 static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) 770 { 771 int val = 0; 772 int err; 773 774 if (index >= EN8811H_LED_COUNT) 775 return -EINVAL; 776 777 if (state == AIR_LED_ENABLE) 778 val |= AIR_PHY_LED_ON_ENABLE; 779 else 780 val &= ~AIR_PHY_LED_ON_ENABLE; 781 782 if (pol == AIR_ACTIVE_HIGH) 783 val |= AIR_PHY_LED_ON_POLARITY; 784 else 785 val &= ~AIR_PHY_LED_ON_POLARITY; 786 787 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), 788 AIR_PHY_LED_ON_ENABLE | 789 AIR_PHY_LED_ON_POLARITY, val); 790 791 if (err < 0) 792 return err; 793 794 return 0; 795 } 796 797 static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode) 798 { 799 struct en8811h_priv *priv = phydev->priv; 800 int ret, i; 801 802 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, 803 dur); 804 if (ret < 0) 805 return ret; 806 807 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, 808 dur >> 1); 809 if (ret < 0) 810 return ret; 811 812 switch (mode) { 813 case AIR_LED_MODE_DISABLE: 814 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, 815 AIR_PHY_LED_BCR_EXT_CTRL | 816 AIR_PHY_LED_BCR_MODE_MASK, 0); 817 if (ret < 0) 818 return ret; 819 break; 820 case AIR_LED_MODE_USER_DEFINE: 821 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, 822 AIR_PHY_LED_BCR_EXT_CTRL | 823 AIR_PHY_LED_BCR_CLK_EN, 824 AIR_PHY_LED_BCR_EXT_CTRL | 825 AIR_PHY_LED_BCR_CLK_EN); 826 if (ret < 0) 827 return ret; 828 break; 829 default: 830 phydev_err(phydev, "LED mode %d is not supported\n", mode); 831 return -EINVAL; 832 } 833 834 for (i = 0; i < num; ++i) { 835 ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH); 836 if (ret < 0) { 837 phydev_err(phydev, "LED%d init failed: %d\n", i, ret); 838 return ret; 839 } 840 air_led_hw_control_set(phydev, i, priv->led[i].rules); 841 } 842 843 return 0; 844 } 845 846 static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index, 847 unsigned long rules) 848 { 849 if (index >= EN8811H_LED_COUNT) 850 return -EINVAL; 851 852 /* All combinations of the supported triggers are allowed */ 853 if (rules & ~en8811h_led_trig) 854 return -EOPNOTSUPP; 855 856 return 0; 857 }; 858 859 static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw, 860 unsigned long parent) 861 { 862 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 863 struct phy_device *phydev = priv->phydev; 864 u32 pbus_value; 865 int ret; 866 867 ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); 868 if (ret < 0) 869 return ret; 870 871 return (pbus_value & AN8811HB_HWTRAP2_CKO) ? 50000000 : 25000000; 872 } 873 874 static int an8811hb_clk_enable(struct clk_hw *hw) 875 { 876 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 877 struct phy_device *phydev = priv->phydev; 878 879 return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, 880 AN8811HB_CLK_DRV_CKO_MASK, 881 AN8811HB_CLK_DRV_CKO_MASK); 882 } 883 884 static void an8811hb_clk_disable(struct clk_hw *hw) 885 { 886 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 887 struct phy_device *phydev = priv->phydev; 888 889 air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, 890 AN8811HB_CLK_DRV_CKO_MASK, 0); 891 } 892 893 static int an8811hb_clk_is_enabled(struct clk_hw *hw) 894 { 895 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 896 struct phy_device *phydev = priv->phydev; 897 u32 pbus_value; 898 int ret; 899 900 ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value); 901 if (ret < 0) 902 return ret; 903 904 return (pbus_value & AN8811HB_CLK_DRV_CKO_MASK); 905 } 906 907 static int an8811hb_clk_save_context(struct clk_hw *hw) 908 { 909 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 910 911 priv->cko_is_enabled = an8811hb_clk_is_enabled(hw); 912 913 return 0; 914 } 915 916 static void an8811hb_clk_restore_context(struct clk_hw *hw) 917 { 918 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 919 920 if (!priv->cko_is_enabled) 921 an8811hb_clk_disable(hw); 922 } 923 924 static const struct clk_ops an8811hb_clk_ops = { 925 .recalc_rate = an8811hb_clk_recalc_rate, 926 .enable = an8811hb_clk_enable, 927 .disable = an8811hb_clk_disable, 928 .is_enabled = an8811hb_clk_is_enabled, 929 .save_context = an8811hb_clk_save_context, 930 .restore_context = an8811hb_clk_restore_context, 931 }; 932 933 static int an8811hb_clk_provider_setup(struct device *dev, struct clk_hw *hw) 934 { 935 struct clk_init_data init; 936 int ret; 937 938 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 939 return 0; 940 941 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko", 942 fwnode_get_name(dev_fwnode(dev))); 943 if (!init.name) 944 return -ENOMEM; 945 946 init.ops = &an8811hb_clk_ops; 947 init.flags = 0; 948 init.num_parents = 0; 949 hw->init = &init; 950 951 ret = devm_clk_hw_register(dev, hw); 952 if (ret) 953 return ret; 954 955 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 956 } 957 958 static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw, 959 unsigned long parent) 960 { 961 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 962 struct phy_device *phydev = priv->phydev; 963 u32 pbus_value; 964 int ret; 965 966 ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value); 967 if (ret < 0) 968 return ret; 969 970 return (pbus_value & EN8811H_HWTRAP1_CKO) ? 50000000 : 25000000; 971 } 972 973 static int en8811h_clk_enable(struct clk_hw *hw) 974 { 975 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 976 struct phy_device *phydev = priv->phydev; 977 978 return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM, 979 EN8811H_CLK_CGM_CKO, 980 EN8811H_CLK_CGM_CKO); 981 } 982 983 static void en8811h_clk_disable(struct clk_hw *hw) 984 { 985 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 986 struct phy_device *phydev = priv->phydev; 987 988 air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM, 989 EN8811H_CLK_CGM_CKO, 0); 990 } 991 992 static int en8811h_clk_is_enabled(struct clk_hw *hw) 993 { 994 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 995 struct phy_device *phydev = priv->phydev; 996 u32 pbus_value; 997 int ret; 998 999 ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value); 1000 if (ret < 0) 1001 return ret; 1002 1003 return (pbus_value & EN8811H_CLK_CGM_CKO); 1004 } 1005 1006 static int en8811h_clk_save_context(struct clk_hw *hw) 1007 { 1008 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1009 1010 priv->cko_is_enabled = en8811h_clk_is_enabled(hw); 1011 1012 return 0; 1013 } 1014 1015 static void en8811h_clk_restore_context(struct clk_hw *hw) 1016 { 1017 struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw); 1018 1019 if (!priv->cko_is_enabled) 1020 en8811h_clk_disable(hw); 1021 } 1022 1023 static const struct clk_ops en8811h_clk_ops = { 1024 .recalc_rate = en8811h_clk_recalc_rate, 1025 .enable = en8811h_clk_enable, 1026 .disable = en8811h_clk_disable, 1027 .is_enabled = en8811h_clk_is_enabled, 1028 .save_context = en8811h_clk_save_context, 1029 .restore_context = en8811h_clk_restore_context, 1030 }; 1031 1032 static int en8811h_clk_provider_setup(struct device *dev, struct clk_hw *hw) 1033 { 1034 struct clk_init_data init; 1035 int ret; 1036 1037 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1038 return 0; 1039 1040 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-cko", 1041 fwnode_get_name(dev_fwnode(dev))); 1042 if (!init.name) 1043 return -ENOMEM; 1044 1045 init.ops = &en8811h_clk_ops; 1046 init.flags = 0; 1047 init.num_parents = 0; 1048 hw->init = &init; 1049 1050 ret = devm_clk_hw_register(dev, hw); 1051 if (ret) 1052 return ret; 1053 1054 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 1055 } 1056 1057 static int en8811h_leds_setup(struct phy_device *phydev) 1058 { 1059 struct en8811h_priv *priv = phydev->priv; 1060 int ret; 1061 1062 priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; 1063 priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; 1064 priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; 1065 1066 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1067 AIR_LED_MODE_DISABLE); 1068 if (ret < 0) 1069 phydev_err(phydev, "Failed to disable leds: %d\n", ret); 1070 1071 return ret; 1072 } 1073 1074 static int an8811hb_probe(struct phy_device *phydev) 1075 { 1076 struct mdio_device *mdiodev; 1077 struct en8811h_priv *priv; 1078 int ret; 1079 1080 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), 1081 GFP_KERNEL); 1082 if (!priv) 1083 return -ENOMEM; 1084 phydev->priv = priv; 1085 1086 /* 1087 * The AN8811HB PHY address is restricted to 8-15 (decimal), 1088 * depending on the board hardware strapping. 1089 * This means the PBUS address is only in the range 16-21 (decimal), 1090 * so we do not need to handle the case 1091 * where the PBUS address exceeds 31 (decimal). 1092 */ 1093 mdiodev = mdio_device_create(phydev->mdio.bus, 1094 phydev->mdio.addr + EN8811H_PBUS_ADDR_OFFS); 1095 if (IS_ERR(mdiodev)) 1096 return PTR_ERR(mdiodev); 1097 1098 ret = mdio_device_register(mdiodev); 1099 if (ret) 1100 goto err_dev_free; 1101 1102 priv->pbusdev = mdiodev; 1103 1104 ret = an8811hb_load_firmware(phydev); 1105 if (ret < 0) { 1106 phydev_err(phydev, "Load firmware failed: %d\n", ret); 1107 goto err_dev_create; 1108 } 1109 1110 en8811h_print_fw_version(phydev); 1111 1112 /* mcu has just restarted after firmware load */ 1113 priv->mcu_needs_restart = false; 1114 1115 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ 1116 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 1117 1118 ret = en8811h_leds_setup(phydev); 1119 if (ret < 0) 1120 goto err_dev_create; 1121 1122 priv->phydev = phydev; 1123 /* Co-Clock Output */ 1124 ret = an8811hb_clk_provider_setup(&phydev->mdio.dev, &priv->hw); 1125 if (ret) 1126 goto err_dev_create; 1127 1128 /* Configure led gpio pins as output */ 1129 ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, 1130 AN8811HB_GPIO_OUTPUT_345, 1131 AN8811HB_GPIO_OUTPUT_345); 1132 if (ret < 0) 1133 goto err_dev_create; 1134 1135 return 0; 1136 1137 err_dev_create: 1138 mdio_device_remove(mdiodev); 1139 1140 err_dev_free: 1141 mdio_device_free(mdiodev); 1142 return ret; 1143 } 1144 1145 static int en8811h_probe(struct phy_device *phydev) 1146 { 1147 struct en8811h_priv *priv; 1148 int ret; 1149 1150 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), 1151 GFP_KERNEL); 1152 if (!priv) 1153 return -ENOMEM; 1154 phydev->priv = priv; 1155 1156 ret = en8811h_load_firmware(phydev); 1157 if (ret < 0) 1158 return ret; 1159 1160 /* mcu has just restarted after firmware load */ 1161 priv->mcu_needs_restart = false; 1162 1163 /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ 1164 phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 1165 1166 ret = en8811h_leds_setup(phydev); 1167 if (ret < 0) 1168 return ret; 1169 1170 priv->phydev = phydev; 1171 /* Co-Clock Output */ 1172 ret = en8811h_clk_provider_setup(&phydev->mdio.dev, &priv->hw); 1173 if (ret) 1174 return ret; 1175 1176 return 0; 1177 } 1178 1179 static int an8811hb_config_serdes_polarity(struct phy_device *phydev) 1180 { 1181 struct device *dev = &phydev->mdio.dev; 1182 u32 pbus_value = 0; 1183 unsigned int pol; 1184 int ret; 1185 1186 ret = phy_get_manual_rx_polarity(dev_fwnode(dev), 1187 phy_modes(phydev->interface), &pol); 1188 if (ret) 1189 return ret; 1190 if (pol == PHY_POL_NORMAL) 1191 pbus_value |= AN8811HB_RX_POLARITY_NORMAL; 1192 ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, 1193 AN8811HB_RX_POLARITY_NORMAL, 1194 pbus_value); 1195 if (ret < 0) 1196 return ret; 1197 1198 ret = phy_get_manual_tx_polarity(dev_fwnode(dev), 1199 phy_modes(phydev->interface), &pol); 1200 if (ret) 1201 return ret; 1202 pbus_value = 0; 1203 if (pol == PHY_POL_NORMAL) 1204 pbus_value |= AN8811HB_TX_POLARITY_NORMAL; 1205 return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, 1206 AN8811HB_TX_POLARITY_NORMAL, 1207 pbus_value); 1208 } 1209 1210 static int en8811h_config_serdes_polarity(struct phy_device *phydev) 1211 { 1212 struct device *dev = &phydev->mdio.dev; 1213 unsigned int pol, default_pol; 1214 u32 pbus_value = 0; 1215 int ret; 1216 1217 default_pol = PHY_POL_NORMAL; 1218 if (device_property_read_bool(dev, "airoha,pnswap-rx")) 1219 default_pol = PHY_POL_INVERT; 1220 1221 ret = phy_get_rx_polarity(dev_fwnode(dev), phy_modes(phydev->interface), 1222 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), 1223 default_pol, &pol); 1224 if (ret) 1225 return ret; 1226 if (pol == PHY_POL_INVERT) 1227 pbus_value |= EN8811H_POLARITY_RX_REVERSE; 1228 1229 default_pol = PHY_POL_NORMAL; 1230 if (device_property_read_bool(dev, "airoha,pnswap-tx")) 1231 default_pol = PHY_POL_INVERT; 1232 1233 ret = phy_get_tx_polarity(dev_fwnode(dev), phy_modes(phydev->interface), 1234 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), 1235 default_pol, &pol); 1236 if (ret) 1237 return ret; 1238 if (pol == PHY_POL_NORMAL) 1239 pbus_value |= EN8811H_POLARITY_TX_NORMAL; 1240 1241 return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY, 1242 EN8811H_POLARITY_RX_REVERSE | 1243 EN8811H_POLARITY_TX_NORMAL, 1244 pbus_value); 1245 } 1246 1247 static int an8811hb_config_init(struct phy_device *phydev) 1248 { 1249 struct en8811h_priv *priv = phydev->priv; 1250 int ret; 1251 1252 /* If restart happened in .probe(), no need to restart now */ 1253 if (priv->mcu_needs_restart) { 1254 ret = en8811h_restart_mcu(phydev); 1255 if (ret < 0) 1256 return ret; 1257 } else { 1258 /* Next calls to .config_init() mcu needs to restart */ 1259 priv->mcu_needs_restart = true; 1260 } 1261 1262 ret = an8811hb_config_serdes_polarity(phydev); 1263 if (ret < 0) 1264 return ret; 1265 1266 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1267 AIR_LED_MODE_USER_DEFINE); 1268 if (ret < 0) 1269 phydev_err(phydev, "Failed to initialize leds: %d\n", ret); 1270 1271 return ret; 1272 } 1273 1274 static int en8811h_config_init(struct phy_device *phydev) 1275 { 1276 struct en8811h_priv *priv = phydev->priv; 1277 int ret; 1278 1279 /* If restart happened in .probe(), no need to restart now */ 1280 if (priv->mcu_needs_restart) { 1281 ret = en8811h_restart_mcu(phydev); 1282 if (ret < 0) 1283 return ret; 1284 } else { 1285 /* Next calls to .config_init() mcu needs to restart */ 1286 priv->mcu_needs_restart = true; 1287 } 1288 1289 /* Select mode 1, the only mode supported. 1290 * Configures the SerDes for 2500Base-X with rate adaptation 1291 */ 1292 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, 1293 AIR_PHY_MCU_CMD_1_MODE1); 1294 if (ret < 0) 1295 return ret; 1296 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, 1297 AIR_PHY_MCU_CMD_2_MODE1); 1298 if (ret < 0) 1299 return ret; 1300 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, 1301 AIR_PHY_MCU_CMD_3_MODE1); 1302 if (ret < 0) 1303 return ret; 1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, 1305 AIR_PHY_MCU_CMD_4_MODE1); 1306 if (ret < 0) 1307 return ret; 1308 1309 ret = en8811h_config_serdes_polarity(phydev); 1310 if (ret < 0) 1311 return ret; 1312 1313 ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, 1314 AIR_LED_MODE_USER_DEFINE); 1315 if (ret < 0) { 1316 phydev_err(phydev, "Failed to initialize leds: %d\n", ret); 1317 return ret; 1318 } 1319 1320 /* Configure led gpio pins as output. Must be redone on every 1321 * .config_init(), not just once in .probe(): en8811h_restart_mcu() 1322 * resets buckpbus-mapped MCU state (incl. this register) on every 1323 * call after the first, e.g. on link renegotiation or ifup/ifdown. 1324 */ 1325 ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT, 1326 EN8811H_GPIO_OUTPUT_345, 1327 EN8811H_GPIO_OUTPUT_345); 1328 if (ret < 0) 1329 return ret; 1330 1331 return 0; 1332 } 1333 1334 static int en8811h_get_features(struct phy_device *phydev) 1335 { 1336 linkmode_set_bit_array(phy_basic_ports_array, 1337 ARRAY_SIZE(phy_basic_ports_array), 1338 phydev->supported); 1339 1340 return genphy_c45_pma_read_abilities(phydev); 1341 } 1342 1343 static int en8811h_get_rate_matching(struct phy_device *phydev, 1344 phy_interface_t iface) 1345 { 1346 return RATE_MATCH_PAUSE; 1347 } 1348 1349 static int en8811h_config_aneg(struct phy_device *phydev) 1350 { 1351 bool changed = false; 1352 int ret; 1353 u32 adv; 1354 1355 if (phydev->autoneg == AUTONEG_DISABLE) { 1356 phydev_warn(phydev, "Disabling autoneg is not supported\n"); 1357 return -EINVAL; 1358 } 1359 1360 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 1361 1362 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1363 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 1364 if (ret < 0) 1365 return ret; 1366 if (ret > 0) 1367 changed = true; 1368 1369 return __genphy_config_aneg(phydev, changed); 1370 } 1371 1372 static int en8811h_read_status(struct phy_device *phydev) 1373 { 1374 struct en8811h_priv *priv = phydev->priv; 1375 u32 pbus_value; 1376 int ret, val; 1377 1378 ret = genphy_update_link(phydev); 1379 if (ret) 1380 return ret; 1381 1382 phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED; 1383 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; 1384 phydev->speed = SPEED_UNKNOWN; 1385 phydev->duplex = DUPLEX_UNKNOWN; 1386 phydev->pause = 0; 1387 phydev->asym_pause = 0; 1388 phydev->rate_matching = RATE_MATCH_PAUSE; 1389 1390 ret = genphy_read_master_slave(phydev); 1391 if (ret < 0) 1392 return ret; 1393 1394 ret = genphy_read_lpa(phydev); 1395 if (ret < 0) 1396 return ret; 1397 1398 if (phy_id_compare_model(phydev->phy_id, AN8811HB_PHY_ID)) { 1399 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1400 if (val < 0) 1401 return val; 1402 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1403 phydev->lp_advertising, 1404 val & MDIO_AN_10GBT_STAT_LP2_5G); 1405 } else { 1406 /* Get link partner 2.5GBASE-T ability from vendor register */ 1407 ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, 1408 &pbus_value); 1409 if (ret < 0) 1410 return ret; 1411 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1412 phydev->lp_advertising, 1413 pbus_value & EN8811H_2P5G_LPA_2P5G); 1414 } 1415 1416 if (phydev->autoneg_complete) 1417 phy_resolve_aneg_pause(phydev); 1418 1419 if (!phydev->link) 1420 return 0; 1421 1422 /* Get real speed from vendor register */ 1423 val = phy_read(phydev, AIR_AUX_CTRL_STATUS); 1424 if (val < 0) 1425 return val; 1426 switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) { 1427 case AIR_AUX_CTRL_STATUS_SPEED_2500: 1428 phydev->speed = SPEED_2500; 1429 break; 1430 case AIR_AUX_CTRL_STATUS_SPEED_1000: 1431 phydev->speed = SPEED_1000; 1432 break; 1433 case AIR_AUX_CTRL_STATUS_SPEED_100: 1434 phydev->speed = SPEED_100; 1435 break; 1436 case AIR_AUX_CTRL_STATUS_SPEED_10: 1437 phydev->speed = SPEED_10; 1438 break; 1439 } 1440 1441 /* Firmware before version 24011202 has no vendor register 2P5G_LPA. 1442 * Assume link partner advertised it if connected at 2500Mbps. 1443 */ 1444 if (priv->firmware_version < 0x24011202) { 1445 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 1446 phydev->lp_advertising, 1447 phydev->speed == SPEED_2500); 1448 } 1449 1450 /* Only supports full duplex */ 1451 phydev->duplex = DUPLEX_FULL; 1452 1453 return 0; 1454 } 1455 1456 static int en8811h_clear_intr(struct phy_device *phydev) 1457 { 1458 int ret; 1459 1460 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, 1461 AIR_PHY_MCU_CMD_3_DOCMD); 1462 if (ret < 0) 1463 return ret; 1464 1465 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, 1466 AIR_PHY_MCU_CMD_4_INTCLR); 1467 if (ret < 0) 1468 return ret; 1469 1470 return 0; 1471 } 1472 1473 static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev) 1474 { 1475 int ret; 1476 1477 ret = en8811h_clear_intr(phydev); 1478 if (ret < 0) { 1479 phy_error(phydev); 1480 return IRQ_NONE; 1481 } 1482 1483 phy_trigger_machine(phydev); 1484 1485 return IRQ_HANDLED; 1486 } 1487 1488 static int en8811h_resume(struct phy_device *phydev) 1489 { 1490 clk_restore_context(); 1491 1492 return genphy_resume(phydev); 1493 } 1494 1495 static int en8811h_suspend(struct phy_device *phydev) 1496 { 1497 clk_save_context(); 1498 1499 return genphy_suspend(phydev); 1500 } 1501 1502 static void an8811hb_remove(struct phy_device *phydev) 1503 { 1504 struct en8811h_priv *priv = phydev->priv; 1505 1506 if (priv->pbusdev) { 1507 mdio_device_remove(priv->pbusdev); 1508 mdio_device_free(priv->pbusdev); 1509 } 1510 } 1511 1512 static struct phy_driver en8811h_driver[] = { 1513 { 1514 PHY_ID_MATCH_MODEL(EN8811H_PHY_ID), 1515 .name = "Airoha EN8811H", 1516 .probe = en8811h_probe, 1517 .get_features = en8811h_get_features, 1518 .config_init = en8811h_config_init, 1519 .get_rate_matching = en8811h_get_rate_matching, 1520 .config_aneg = en8811h_config_aneg, 1521 .read_status = en8811h_read_status, 1522 .resume = en8811h_resume, 1523 .suspend = en8811h_suspend, 1524 .config_intr = en8811h_clear_intr, 1525 .handle_interrupt = en8811h_handle_interrupt, 1526 .led_hw_is_supported = en8811h_led_hw_is_supported, 1527 .read_page = air_phy_read_page, 1528 .write_page = air_phy_write_page, 1529 .led_blink_set = air_led_blink_set, 1530 .led_brightness_set = air_led_brightness_set, 1531 .led_hw_control_set = air_led_hw_control_set, 1532 .led_hw_control_get = air_led_hw_control_get, 1533 }, 1534 { 1535 PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID), 1536 .name = "Airoha AN8811HB", 1537 .probe = an8811hb_probe, 1538 .remove = an8811hb_remove, 1539 .get_features = en8811h_get_features, 1540 .config_init = an8811hb_config_init, 1541 .get_rate_matching = en8811h_get_rate_matching, 1542 .config_aneg = en8811h_config_aneg, 1543 .read_status = en8811h_read_status, 1544 .resume = en8811h_resume, 1545 .suspend = en8811h_suspend, 1546 .config_intr = en8811h_clear_intr, 1547 .handle_interrupt = en8811h_handle_interrupt, 1548 .led_hw_is_supported = en8811h_led_hw_is_supported, 1549 .read_page = air_phy_read_page, 1550 .write_page = air_phy_write_page, 1551 .led_blink_set = air_led_blink_set, 1552 .led_brightness_set = air_led_brightness_set, 1553 .led_hw_control_set = air_led_hw_control_set, 1554 .led_hw_control_get = air_led_hw_control_get, 1555 } }; 1556 1557 module_phy_driver(en8811h_driver); 1558 1559 static const struct mdio_device_id __maybe_unused en8811h_tbl[] = { 1560 { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, 1561 { PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID) }, 1562 { } 1563 }; 1564 1565 MODULE_DEVICE_TABLE(mdio, en8811h_tbl); 1566 MODULE_FIRMWARE(EN8811H_MD32_DM); 1567 MODULE_FIRMWARE(EN8811H_MD32_DSP); 1568 MODULE_FIRMWARE(AN8811HB_MD32_DM); 1569 MODULE_FIRMWARE(AN8811HB_MD32_DSP); 1570 1571 MODULE_DESCRIPTION("Airoha EN8811H and AN8811HB PHY drivers"); 1572 MODULE_AUTHOR("Airoha"); 1573 MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>"); 1574 MODULE_LICENSE("GPL"); 1575