1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #define SYNOPSYS_XPCS_ID 0x7996ced0 10 #define SYNOPSYS_XPCS_MASK 0xffffffff 11 12 /* Vendor regs access */ 13 #define DW_VENDOR BIT(15) 14 15 /* VR_XS_PCS */ 16 #define DW_USXGMII_RST BIT(10) 17 #define DW_USXGMII_EN BIT(9) 18 #define DW_VR_XS_PCS_DIG_CTRL1 0x0000 19 #define DW_VR_RST BIT(15) 20 #define DW_EN_VSMMD1 BIT(13) 21 #define DW_CL37_BP BIT(12) 22 #define DW_VR_XS_PCS_DIG_STS 0x0010 23 #define DW_RXFIFO_ERR GENMASK(6, 5) 24 #define DW_PSEQ_ST GENMASK(4, 2) 25 #define DW_PSEQ_ST_GOOD FIELD_PREP(GENMASK(4, 2), 0x4) 26 27 /* SR_MII */ 28 #define DW_USXGMII_FULL BIT(8) 29 #define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5)) 30 #define DW_USXGMII_10000 (BIT(13) | BIT(6)) 31 #define DW_USXGMII_5000 (BIT(13) | BIT(5)) 32 #define DW_USXGMII_2500 (BIT(5)) 33 #define DW_USXGMII_1000 (BIT(6)) 34 #define DW_USXGMII_100 (BIT(13)) 35 #define DW_USXGMII_10 (0) 36 37 /* SR_AN */ 38 #define DW_SR_AN_ADV1 0x10 39 #define DW_SR_AN_ADV2 0x11 40 #define DW_SR_AN_ADV3 0x12 41 42 /* Clause 73 Defines */ 43 /* AN_LP_ABL1 */ 44 #define DW_C73_PAUSE BIT(10) 45 #define DW_C73_ASYM_PAUSE BIT(11) 46 #define DW_C73_AN_ADV_SF 0x1 47 /* AN_LP_ABL2 */ 48 #define DW_C73_1000KX BIT(5) 49 #define DW_C73_10000KX4 BIT(6) 50 #define DW_C73_10000KR BIT(7) 51 /* AN_LP_ABL3 */ 52 #define DW_C73_2500KX BIT(0) 53 #define DW_C73_5000KR BIT(1) 54 55 /* Clause 37 Defines */ 56 /* VR MII MMD registers offsets */ 57 #define DW_VR_MII_MMD_CTRL 0x0000 58 #define DW_VR_MII_MMD_STS 0x0001 59 #define DW_VR_MII_MMD_STS_LINK_STS BIT(2) 60 #define DW_VR_MII_DIG_CTRL1 0x8000 61 #define DW_VR_MII_AN_CTRL 0x8001 62 #define DW_VR_MII_AN_INTR_STS 0x8002 63 /* Enable 2.5G Mode */ 64 #define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2) 65 /* EEE Mode Control Register */ 66 #define DW_VR_MII_EEE_MCTRL0 0x8006 67 #define DW_VR_MII_EEE_MCTRL1 0x800b 68 #define DW_VR_MII_DIG_CTRL2 0x80e1 69 70 /* VR_MII_DIG_CTRL1 */ 71 #define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9) 72 #define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0) 73 74 /* VR_MII_DIG_CTRL2 */ 75 #define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4) 76 #define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0) 77 78 /* VR_MII_AN_CTRL */ 79 #define DW_VR_MII_AN_CTRL_8BIT BIT(8) 80 #define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3 81 #define DW_VR_MII_TX_CONFIG_MASK BIT(3) 82 #define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1 83 #define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII 0x0 84 #define DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT 1 85 #define DW_VR_MII_PCS_MODE_MASK GENMASK(2, 1) 86 #define DW_VR_MII_PCS_MODE_C37_1000BASEX 0x0 87 #define DW_VR_MII_PCS_MODE_C37_SGMII 0x2 88 #define DW_VR_MII_AN_INTR_EN BIT(0) 89 90 /* VR_MII_AN_INTR_STS */ 91 #define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0) 92 #define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1) 93 #define DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT 2 94 #define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2) 95 #define DW_VR_MII_C37_ANSGM_SP_10 0x0 96 #define DW_VR_MII_C37_ANSGM_SP_100 0x1 97 #define DW_VR_MII_C37_ANSGM_SP_1000 0x2 98 #define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4) 99 100 /* SR MII MMD Control defines */ 101 #define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */ 102 #define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */ 103 #define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */ 104 105 /* SR MII MMD AN Advertisement defines */ 106 #define DW_HALF_DUPLEX BIT(6) 107 #define DW_FULL_DUPLEX BIT(5) 108 109 /* VR MII EEE Control 0 defines */ 110 #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */ 111 #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */ 112 #define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */ 113 #define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */ 114 #define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */ 115 #define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */ 116 117 #define DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT 8 118 #define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8) 119 120 /* VR MII EEE Control 1 defines */ 121 #define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */ 122 123 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg); 124 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val); 125 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg); 126 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val); 127 int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs); 128 int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs); 129 int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs); 130 int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface); 131