1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/pcs/pcs-xpcs.h> 12 #include <linux/mdio.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 #include <linux/property.h> 16 17 #include "pcs-xpcs.h" 18 19 #define phylink_pcs_to_xpcs(pl_pcs) \ 20 container_of((pl_pcs), struct dw_xpcs, pcs) 21 22 static const int xpcs_usxgmii_features[] = { 23 ETHTOOL_LINK_MODE_Pause_BIT, 24 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 25 ETHTOOL_LINK_MODE_Autoneg_BIT, 26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 30 __ETHTOOL_LINK_MODE_MASK_NBITS, 31 }; 32 33 static const int xpcs_10gkr_features[] = { 34 ETHTOOL_LINK_MODE_Pause_BIT, 35 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 37 __ETHTOOL_LINK_MODE_MASK_NBITS, 38 }; 39 40 static const int xpcs_xlgmii_features[] = { 41 ETHTOOL_LINK_MODE_Pause_BIT, 42 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 43 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 44 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 45 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 46 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 47 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 48 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 49 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 50 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 51 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 52 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 53 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 54 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 55 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 56 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 57 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 58 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 59 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 60 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 61 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 62 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 63 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 64 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 65 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 66 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 67 __ETHTOOL_LINK_MODE_MASK_NBITS, 68 }; 69 70 static const int xpcs_10gbaser_features[] = { 71 ETHTOOL_LINK_MODE_Pause_BIT, 72 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 73 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 74 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 75 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 76 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 77 __ETHTOOL_LINK_MODE_MASK_NBITS, 78 }; 79 80 static const int xpcs_sgmii_features[] = { 81 ETHTOOL_LINK_MODE_Pause_BIT, 82 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 83 ETHTOOL_LINK_MODE_Autoneg_BIT, 84 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 85 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 86 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 87 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 88 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 89 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 90 __ETHTOOL_LINK_MODE_MASK_NBITS, 91 }; 92 93 static const int xpcs_1000basex_features[] = { 94 ETHTOOL_LINK_MODE_Pause_BIT, 95 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 96 ETHTOOL_LINK_MODE_Autoneg_BIT, 97 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 98 __ETHTOOL_LINK_MODE_MASK_NBITS, 99 }; 100 101 static const int xpcs_2500basex_features[] = { 102 ETHTOOL_LINK_MODE_Pause_BIT, 103 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 104 ETHTOOL_LINK_MODE_Autoneg_BIT, 105 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 106 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 107 __ETHTOOL_LINK_MODE_MASK_NBITS, 108 }; 109 110 struct dw_xpcs_compat { 111 phy_interface_t interface; 112 const int *supported; 113 int an_mode; 114 int (*pma_config)(struct dw_xpcs *xpcs); 115 }; 116 117 struct dw_xpcs_desc { 118 u32 id; 119 u32 mask; 120 const struct dw_xpcs_compat *compat; 121 }; 122 123 static const struct dw_xpcs_compat * 124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) 125 { 126 const struct dw_xpcs_compat *compat; 127 128 for (compat = xpcs->desc->compat; compat->supported; compat++) 129 if (compat->interface == interface) 130 return compat; 131 132 return NULL; 133 } 134 135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) 136 { 137 return &xpcs->pcs; 138 } 139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); 140 141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 142 { 143 const struct dw_xpcs_compat *compat; 144 145 compat = xpcs_find_compat(xpcs, interface); 146 if (!compat) 147 return -ENODEV; 148 149 return compat->an_mode; 150 } 151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 152 153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, 154 enum ethtool_link_mode_bit_indices linkmode) 155 { 156 int i; 157 158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 159 if (compat->supported[i] == linkmode) 160 return true; 161 162 return false; 163 } 164 165 #define xpcs_linkmode_supported(compat, mode) \ 166 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 167 168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 169 { 170 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 171 } 172 173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 174 { 175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 176 } 177 178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 179 { 180 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 181 } 182 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 184 u16 mask, u16 set) 185 { 186 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 187 } 188 189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 190 { 191 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 192 } 193 194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 195 u16 val) 196 { 197 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 198 } 199 200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 201 u16 set) 202 { 203 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 204 } 205 206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 207 { 208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 209 } 210 211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 212 { 213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 214 } 215 216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 217 { 218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 219 } 220 221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 222 { 223 int ret, val; 224 225 ret = read_poll_timeout(xpcs_read, val, 226 val < 0 || !(val & BMCR_RESET), 227 50000, 600000, true, xpcs, dev, MII_BMCR); 228 if (val < 0) 229 ret = val; 230 231 return ret; 232 } 233 234 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 235 const struct dw_xpcs_compat *compat) 236 { 237 int ret, dev; 238 239 switch (compat->an_mode) { 240 case DW_AN_C73: 241 case DW_10GBASER: 242 dev = MDIO_MMD_PCS; 243 break; 244 case DW_AN_C37_SGMII: 245 case DW_2500BASEX: 246 case DW_AN_C37_1000BASEX: 247 dev = MDIO_MMD_VEND2; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET); 254 if (ret < 0) 255 return ret; 256 257 return xpcs_poll_reset(xpcs, dev); 258 } 259 260 #define xpcs_warn(__xpcs, __state, __args...) \ 261 ({ \ 262 if ((__state)->link) \ 263 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 264 }) 265 266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 267 struct phylink_link_state *state, 268 u16 pcs_stat1) 269 { 270 int ret; 271 272 if (pcs_stat1 & MDIO_STAT1_FAULT) { 273 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 274 return -EFAULT; 275 } 276 277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 278 if (ret < 0) 279 return ret; 280 281 if (ret & MDIO_STAT2_RXFAULT) 282 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 283 if (ret & MDIO_STAT2_TXFAULT) 284 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 285 286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 287 if (ret < 0) 288 return ret; 289 290 if (ret & DW_RXFIFO_ERR) { 291 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 292 return -EFAULT; 293 } 294 295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 296 if (ret < 0) 297 return ret; 298 299 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 300 xpcs_warn(xpcs, state, "Link is not locked!\n"); 301 302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 303 if (ret < 0) 304 return ret; 305 306 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 307 xpcs_warn(xpcs, state, "Link has errors!\n"); 308 return -EFAULT; 309 } 310 311 return 0; 312 } 313 314 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) 315 { 316 int ret, speed_sel; 317 318 switch (speed) { 319 case SPEED_10: 320 speed_sel = DW_USXGMII_10; 321 break; 322 case SPEED_100: 323 speed_sel = DW_USXGMII_100; 324 break; 325 case SPEED_1000: 326 speed_sel = DW_USXGMII_1000; 327 break; 328 case SPEED_2500: 329 speed_sel = DW_USXGMII_2500; 330 break; 331 case SPEED_5000: 332 speed_sel = DW_USXGMII_5000; 333 break; 334 case SPEED_10000: 335 speed_sel = DW_USXGMII_10000; 336 break; 337 default: 338 /* Nothing to do here */ 339 return; 340 } 341 342 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 343 if (ret < 0) 344 goto out; 345 346 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, 347 speed_sel | DW_USXGMII_FULL); 348 if (ret < 0) 349 goto out; 350 351 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 352 DW_USXGMII_RST); 353 if (ret < 0) 354 goto out; 355 356 return; 357 358 out: 359 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", 360 __func__, ERR_PTR(ret)); 361 } 362 363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 364 const struct dw_xpcs_compat *compat) 365 { 366 int ret, adv; 367 368 /* By default, in USXGMII mode XPCS operates at 10G baud and 369 * replicates data to achieve lower speeds. Hereby, in this 370 * default configuration we need to advertise all supported 371 * modes and not only the ones we want to use. 372 */ 373 374 /* SR_AN_ADV3 */ 375 adv = 0; 376 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 377 adv |= DW_C73_2500KX; 378 379 /* TODO: 5000baseKR */ 380 381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 382 if (ret < 0) 383 return ret; 384 385 /* SR_AN_ADV2 */ 386 adv = 0; 387 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 388 adv |= DW_C73_1000KX; 389 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 390 adv |= DW_C73_10000KX4; 391 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 392 adv |= DW_C73_10000KR; 393 394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 395 if (ret < 0) 396 return ret; 397 398 /* SR_AN_ADV1 */ 399 adv = DW_C73_AN_ADV_SF; 400 if (xpcs_linkmode_supported(compat, Pause)) 401 adv |= DW_C73_PAUSE; 402 if (xpcs_linkmode_supported(compat, Asym_Pause)) 403 adv |= DW_C73_ASYM_PAUSE; 404 405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 406 } 407 408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 409 const struct dw_xpcs_compat *compat) 410 { 411 int ret; 412 413 ret = _xpcs_config_aneg_c73(xpcs, compat); 414 if (ret < 0) 415 return ret; 416 417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 418 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 419 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 420 } 421 422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 423 struct phylink_link_state *state, 424 const struct dw_xpcs_compat *compat, u16 an_stat1) 425 { 426 int ret; 427 428 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 430 if (ret < 0) 431 return ret; 432 433 /* Check if Aneg outcome is valid */ 434 if (!(ret & DW_C73_AN_ADV_SF)) { 435 xpcs_config_aneg_c73(xpcs, compat); 436 return 0; 437 } 438 439 return 1; 440 } 441 442 return 0; 443 } 444 445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 446 struct phylink_link_state *state, u16 an_stat1) 447 { 448 u16 lpa[3]; 449 int i, ret; 450 451 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 452 phylink_clear(state->lp_advertising, Autoneg); 453 return 0; 454 } 455 456 phylink_set(state->lp_advertising, Autoneg); 457 458 /* Read Clause 73 link partner advertisement */ 459 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 461 if (ret < 0) 462 return ret; 463 464 lpa[i] = ret; 465 } 466 467 mii_c73_mod_linkmode(state->lp_advertising, lpa); 468 469 return 0; 470 } 471 472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 473 struct phylink_link_state *state) 474 { 475 unsigned long *adv = state->advertising; 476 int speed = SPEED_UNKNOWN; 477 int bit; 478 479 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 480 int new_speed = SPEED_UNKNOWN; 481 482 switch (bit) { 483 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 484 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 485 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 486 new_speed = SPEED_25000; 487 break; 488 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 489 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 490 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 491 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 492 new_speed = SPEED_40000; 493 break; 494 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 495 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 496 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 497 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 498 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 499 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 500 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 501 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 502 new_speed = SPEED_50000; 503 break; 504 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 505 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 506 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 507 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 508 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 509 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 510 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 511 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 512 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 513 new_speed = SPEED_100000; 514 break; 515 default: 516 continue; 517 } 518 519 if (new_speed > speed) 520 speed = new_speed; 521 } 522 523 return speed; 524 } 525 526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs, 527 struct phylink_link_state *state) 528 { 529 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 530 state->duplex = DUPLEX_FULL; 531 532 switch (state->interface) { 533 case PHY_INTERFACE_MODE_10GKR: 534 state->speed = SPEED_10000; 535 break; 536 case PHY_INTERFACE_MODE_XLGMII: 537 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 538 break; 539 default: 540 state->speed = SPEED_UNKNOWN; 541 break; 542 } 543 } 544 545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 546 const struct phylink_link_state *state) 547 { 548 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 549 const struct dw_xpcs_compat *compat; 550 struct dw_xpcs *xpcs; 551 int i; 552 553 xpcs = phylink_pcs_to_xpcs(pcs); 554 compat = xpcs_find_compat(xpcs, state->interface); 555 if (!compat) 556 return -EINVAL; 557 558 /* Populate the supported link modes for this PHY interface type. 559 * FIXME: what about the port modes and autoneg bit? This masks 560 * all those away. 561 */ 562 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 563 set_bit(compat->supported[i], xpcs_supported); 564 565 linkmode_and(supported, supported, xpcs_supported); 566 567 return 0; 568 } 569 570 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, 571 phy_interface_t interface) 572 { 573 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 574 const struct dw_xpcs_compat *compat; 575 576 compat = xpcs_find_compat(xpcs, interface); 577 if (!compat) 578 return 0; 579 580 switch (compat->an_mode) { 581 case DW_AN_C73: 582 return LINK_INBAND_ENABLE; 583 584 case DW_AN_C37_SGMII: 585 case DW_AN_C37_1000BASEX: 586 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 587 588 case DW_10GBASER: 589 case DW_2500BASEX: 590 return LINK_INBAND_DISABLE; 591 592 default: 593 return 0; 594 } 595 } 596 597 static void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 598 { 599 const struct dw_xpcs_compat *compat; 600 601 for (compat = xpcs->desc->compat; compat->supported; compat++) 602 __set_bit(compat->interface, interfaces); 603 } 604 605 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) 606 { 607 u16 mask, val; 608 int ret; 609 610 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 611 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 612 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 613 DW_VR_MII_EEE_MULT_FACT_100NS; 614 615 if (enable) 616 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 617 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 618 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 619 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 620 mult_fact_100ns); 621 else 622 val = 0; 623 624 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 625 val); 626 if (ret < 0) 627 return ret; 628 629 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 630 DW_VR_MII_EEE_TRN_LPI, 631 enable ? DW_VR_MII_EEE_TRN_LPI : 0); 632 } 633 EXPORT_SYMBOL_GPL(xpcs_config_eee); 634 635 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) 636 { 637 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 638 const struct dw_xpcs_compat *compat; 639 int ret; 640 641 if (!xpcs->need_reset) 642 return; 643 644 compat = xpcs_find_compat(xpcs, interface); 645 if (!compat) { 646 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", 647 phy_modes(interface)); 648 return; 649 } 650 651 ret = xpcs_soft_reset(xpcs, compat); 652 if (ret) 653 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", 654 ERR_PTR(ret)); 655 656 xpcs->need_reset = false; 657 } 658 659 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, 660 unsigned int neg_mode) 661 { 662 int ret, mdio_ctrl, tx_conf; 663 u16 mask, val; 664 665 /* For AN for C37 SGMII mode, the settings are :- 666 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 667 it is already enabled) 668 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 669 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 670 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 671 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 672 * speed/duplex mode change by HW after SGMII AN complete) 673 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 674 * 675 * Note that VR_MII_MMD_CTRL is MII_BMCR. 676 * 677 * Note: Since it is MAC side SGMII, there is no need to set 678 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 679 * PHY about the link state change after C28 AN is completed 680 * between PHY and Link Partner. There is also no need to 681 * trigger AN restart for MAC-side SGMII. 682 */ 683 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 684 if (mdio_ctrl < 0) 685 return mdio_ctrl; 686 687 if (mdio_ctrl & BMCR_ANENABLE) { 688 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 689 mdio_ctrl & ~BMCR_ANENABLE); 690 if (ret < 0) 691 return ret; 692 } 693 694 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 695 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 696 DW_VR_MII_PCS_MODE_C37_SGMII); 697 698 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 699 mask |= DW_VR_MII_AN_CTRL_8BIT; 700 val |= DW_VR_MII_AN_CTRL_8BIT; 701 /* Hardware requires it to be PHY side SGMII */ 702 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 703 } else { 704 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 705 } 706 707 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 708 709 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 710 if (ret < 0) 711 return ret; 712 713 mask = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 714 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 715 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 716 717 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 718 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 719 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 720 } 721 722 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 723 if (ret < 0) 724 return ret; 725 726 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 727 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 728 mdio_ctrl | BMCR_ANENABLE); 729 730 return ret; 731 } 732 733 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, 734 unsigned int neg_mode, 735 const unsigned long *advertising) 736 { 737 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 738 int ret, mdio_ctrl, adv; 739 bool changed = 0; 740 u16 mask, val; 741 742 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 743 * be disabled first:- 744 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 745 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 746 * 747 * Note that VR_MII_MMD_CTRL is MII_BMCR. 748 */ 749 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 750 if (mdio_ctrl < 0) 751 return mdio_ctrl; 752 753 if (mdio_ctrl & BMCR_ANENABLE) { 754 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 755 mdio_ctrl & ~BMCR_ANENABLE); 756 if (ret < 0) 757 return ret; 758 } 759 760 mask = DW_VR_MII_PCS_MODE_MASK; 761 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 762 DW_VR_MII_PCS_MODE_C37_1000BASEX); 763 764 if (!xpcs->pcs.poll) { 765 mask |= DW_VR_MII_AN_INTR_EN; 766 val |= DW_VR_MII_AN_INTR_EN; 767 } 768 769 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 770 if (ret < 0) 771 return ret; 772 773 /* Check for advertising changes and update the C45 MII ADV 774 * register accordingly. 775 */ 776 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 777 advertising); 778 if (adv >= 0) { 779 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 780 MII_ADVERTISE, 0xffff, adv); 781 if (ret < 0) 782 return ret; 783 784 changed = ret; 785 } 786 787 /* Clear CL37 AN complete status */ 788 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 789 if (ret < 0) 790 return ret; 791 792 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 793 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 794 mdio_ctrl | BMCR_ANENABLE); 795 if (ret < 0) 796 return ret; 797 } 798 799 return changed; 800 } 801 802 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 803 { 804 int ret; 805 806 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 807 DW_VR_MII_DIG_CTRL1_2G5_EN | 808 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 809 DW_VR_MII_DIG_CTRL1_2G5_EN); 810 if (ret < 0) 811 return ret; 812 813 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, 814 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100, 815 BMCR_SPEED1000); 816 } 817 818 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 819 const unsigned long *advertising, 820 unsigned int neg_mode) 821 { 822 const struct dw_xpcs_compat *compat; 823 int ret; 824 825 compat = xpcs_find_compat(xpcs, interface); 826 if (!compat) 827 return -ENODEV; 828 829 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 830 ret = txgbe_xpcs_switch_mode(xpcs, interface); 831 if (ret) 832 return ret; 833 834 /* Wangxun devices need backplane CL37 AN enabled for 835 * SGMII and 1000base-X 836 */ 837 if (interface == PHY_INTERFACE_MODE_SGMII || 838 interface == PHY_INTERFACE_MODE_1000BASEX) 839 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, 840 DW_CL37_BP | DW_EN_VSMMD1); 841 } 842 843 switch (compat->an_mode) { 844 case DW_10GBASER: 845 break; 846 case DW_AN_C73: 847 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 848 ret = xpcs_config_aneg_c73(xpcs, compat); 849 if (ret) 850 return ret; 851 } 852 break; 853 case DW_AN_C37_SGMII: 854 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode); 855 if (ret) 856 return ret; 857 break; 858 case DW_AN_C37_1000BASEX: 859 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode, 860 advertising); 861 if (ret) 862 return ret; 863 break; 864 case DW_2500BASEX: 865 ret = xpcs_config_2500basex(xpcs); 866 if (ret) 867 return ret; 868 break; 869 default: 870 return -EINVAL; 871 } 872 873 if (compat->pma_config) { 874 ret = compat->pma_config(xpcs); 875 if (ret) 876 return ret; 877 } 878 879 return 0; 880 } 881 882 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 883 phy_interface_t interface, 884 const unsigned long *advertising, 885 bool permit_pause_to_mac) 886 { 887 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 888 889 return xpcs_do_config(xpcs, interface, advertising, neg_mode); 890 } 891 892 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 893 struct phylink_link_state *state, 894 const struct dw_xpcs_compat *compat) 895 { 896 bool an_enabled; 897 int pcs_stat1; 898 int an_stat1; 899 int ret; 900 901 /* The link status bit is latching-low, so it is important to 902 * avoid unnecessary re-reads of this register to avoid missing 903 * a link-down event. 904 */ 905 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 906 if (pcs_stat1 < 0) { 907 state->link = false; 908 return pcs_stat1; 909 } 910 911 /* Link needs to be read first ... */ 912 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 913 914 /* ... and then we check the faults. */ 915 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 916 if (ret) { 917 ret = xpcs_soft_reset(xpcs, compat); 918 if (ret) 919 return ret; 920 921 state->link = 0; 922 923 return xpcs_do_config(xpcs, state->interface, NULL, 924 PHYLINK_PCS_NEG_INBAND_ENABLED); 925 } 926 927 /* There is no point doing anything else if the link is down. */ 928 if (!state->link) 929 return 0; 930 931 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 932 state->advertising); 933 if (an_enabled) { 934 /* The link status bit is latching-low, so it is important to 935 * avoid unnecessary re-reads of this register to avoid missing 936 * a link-down event. 937 */ 938 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 939 if (an_stat1 < 0) { 940 state->link = false; 941 return an_stat1; 942 } 943 944 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 945 an_stat1); 946 if (!state->an_complete) { 947 state->link = false; 948 return 0; 949 } 950 951 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 952 if (ret < 0) { 953 state->link = false; 954 return ret; 955 } 956 957 phylink_resolve_c73(state); 958 } else { 959 xpcs_resolve_pma(xpcs, state); 960 } 961 962 return 0; 963 } 964 965 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 966 struct phylink_link_state *state) 967 { 968 int ret; 969 970 /* Reset link_state */ 971 state->link = false; 972 state->speed = SPEED_UNKNOWN; 973 state->duplex = DUPLEX_UNKNOWN; 974 state->pause = 0; 975 976 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 977 * status, speed and duplex. 978 */ 979 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 980 if (ret < 0) 981 return ret; 982 983 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 984 int speed_value; 985 986 state->link = true; 987 988 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 989 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 990 state->speed = SPEED_1000; 991 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 992 state->speed = SPEED_100; 993 else 994 state->speed = SPEED_10; 995 996 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 997 state->duplex = DUPLEX_FULL; 998 else 999 state->duplex = DUPLEX_HALF; 1000 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1001 int speed, duplex; 1002 1003 state->link = true; 1004 1005 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 1006 if (speed < 0) 1007 return speed; 1008 1009 speed &= BMCR_SPEED100 | BMCR_SPEED1000; 1010 if (speed == BMCR_SPEED1000) 1011 state->speed = SPEED_1000; 1012 else if (speed == BMCR_SPEED100) 1013 state->speed = SPEED_100; 1014 else if (speed == 0) 1015 state->speed = SPEED_10; 1016 1017 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE); 1018 if (duplex < 0) 1019 return duplex; 1020 1021 if (duplex & ADVERTISE_1000XFULL) 1022 state->duplex = DUPLEX_FULL; 1023 else if (duplex & ADVERTISE_1000XHALF) 1024 state->duplex = DUPLEX_HALF; 1025 1026 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 1033 struct phylink_link_state *state) 1034 { 1035 int lpa, bmsr; 1036 1037 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1038 state->advertising)) { 1039 /* Reset link state */ 1040 state->link = false; 1041 1042 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 1043 if (lpa < 0 || lpa & LPA_RFAULT) 1044 return lpa; 1045 1046 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1047 if (bmsr < 0) 1048 return bmsr; 1049 1050 /* Clear AN complete interrupt */ 1051 if (!xpcs->pcs.poll) { 1052 int an_intr; 1053 1054 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1055 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1056 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1057 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr); 1058 } 1059 } 1060 1061 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa); 1062 } 1063 1064 return 0; 1065 } 1066 1067 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, 1068 struct phylink_link_state *state) 1069 { 1070 int ret; 1071 1072 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1073 if (ret < 0) { 1074 state->link = 0; 1075 return ret; 1076 } 1077 1078 state->link = !!(ret & BMSR_LSTATUS); 1079 if (!state->link) 1080 return 0; 1081 1082 state->speed = SPEED_2500; 1083 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 1084 state->duplex = DUPLEX_FULL; 1085 1086 return 0; 1087 } 1088 1089 static void xpcs_get_state(struct phylink_pcs *pcs, 1090 struct phylink_link_state *state) 1091 { 1092 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1093 const struct dw_xpcs_compat *compat; 1094 int ret; 1095 1096 compat = xpcs_find_compat(xpcs, state->interface); 1097 if (!compat) 1098 return; 1099 1100 switch (compat->an_mode) { 1101 case DW_10GBASER: 1102 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1103 break; 1104 case DW_AN_C73: 1105 ret = xpcs_get_state_c73(xpcs, state, compat); 1106 if (ret) 1107 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1108 "xpcs_get_state_c73", ERR_PTR(ret)); 1109 break; 1110 case DW_AN_C37_SGMII: 1111 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1112 if (ret) 1113 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1114 "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); 1115 break; 1116 case DW_AN_C37_1000BASEX: 1117 ret = xpcs_get_state_c37_1000basex(xpcs, state); 1118 if (ret) 1119 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1120 "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); 1121 break; 1122 case DW_2500BASEX: 1123 ret = xpcs_get_state_2500basex(xpcs, state); 1124 if (ret) 1125 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1126 "xpcs_get_state_2500basex", ERR_PTR(ret)); 1127 break; 1128 default: 1129 return; 1130 } 1131 } 1132 1133 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, 1134 unsigned int neg_mode, 1135 phy_interface_t interface, 1136 int speed, int duplex) 1137 { 1138 int ret; 1139 1140 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1141 return; 1142 1143 if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1144 if (speed != SPEED_1000) { 1145 dev_err(&xpcs->mdiodev->dev, 1146 "%s: speed %dMbps not supported\n", 1147 __func__, speed); 1148 return; 1149 } 1150 1151 if (duplex != DUPLEX_FULL) 1152 dev_err(&xpcs->mdiodev->dev, 1153 "%s: half duplex not supported\n", 1154 __func__); 1155 } 1156 1157 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 1158 mii_bmcr_encode_fixed(speed, duplex)); 1159 if (ret) 1160 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1161 __func__, ERR_PTR(ret)); 1162 } 1163 1164 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 1165 phy_interface_t interface, int speed, int duplex) 1166 { 1167 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1168 1169 switch (interface) { 1170 case PHY_INTERFACE_MODE_USXGMII: 1171 xpcs_link_up_usxgmii(xpcs, speed); 1172 break; 1173 1174 case PHY_INTERFACE_MODE_SGMII: 1175 case PHY_INTERFACE_MODE_1000BASEX: 1176 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed, 1177 duplex); 1178 break; 1179 1180 default: 1181 break; 1182 } 1183 } 1184 1185 static void xpcs_an_restart(struct phylink_pcs *pcs) 1186 { 1187 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1188 1189 xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, 1190 BMCR_ANRESTART); 1191 } 1192 1193 static int xpcs_read_ids(struct dw_xpcs *xpcs) 1194 { 1195 int ret; 1196 u32 id; 1197 1198 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication 1199 * failed indicating that device couldn't be reached. 1200 */ 1201 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1202 if (ret < 0) 1203 return -ENODEV; 1204 1205 id = ret << 16; 1206 1207 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1208 if (ret < 0) 1209 return ret; 1210 1211 id |= ret; 1212 1213 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 1214 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 1215 * PCS in MII MMD 31. 1216 */ 1217 if (!id || id == 0xffffffff) { 1218 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1219 if (ret < 0) 1220 return ret; 1221 1222 id = ret << 16; 1223 1224 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1225 if (ret < 0) 1226 return ret; 1227 1228 id |= ret; 1229 } 1230 1231 /* Set the PCS ID if it hasn't been pre-initialized */ 1232 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) 1233 xpcs->info.pcs = id; 1234 1235 /* Find out PMA/PMD ID from MMD 1 device ID registers */ 1236 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); 1237 if (ret < 0) 1238 return ret; 1239 1240 id = ret; 1241 1242 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); 1243 if (ret < 0) 1244 return ret; 1245 1246 /* Note the inverted dword order and masked out Model/Revision numbers 1247 * with respect to what is done with the PCS ID... 1248 */ 1249 ret = (ret >> 10) & 0x3F; 1250 id |= ret << 16; 1251 1252 /* Set the PMA ID if it hasn't been pre-initialized */ 1253 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) 1254 xpcs->info.pma = id; 1255 1256 return 0; 1257 } 1258 1259 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { 1260 { 1261 .interface = PHY_INTERFACE_MODE_USXGMII, 1262 .supported = xpcs_usxgmii_features, 1263 .an_mode = DW_AN_C73, 1264 }, { 1265 .interface = PHY_INTERFACE_MODE_10GKR, 1266 .supported = xpcs_10gkr_features, 1267 .an_mode = DW_AN_C73, 1268 }, { 1269 .interface = PHY_INTERFACE_MODE_XLGMII, 1270 .supported = xpcs_xlgmii_features, 1271 .an_mode = DW_AN_C73, 1272 }, { 1273 .interface = PHY_INTERFACE_MODE_10GBASER, 1274 .supported = xpcs_10gbaser_features, 1275 .an_mode = DW_10GBASER, 1276 }, { 1277 .interface = PHY_INTERFACE_MODE_SGMII, 1278 .supported = xpcs_sgmii_features, 1279 .an_mode = DW_AN_C37_SGMII, 1280 }, { 1281 .interface = PHY_INTERFACE_MODE_1000BASEX, 1282 .supported = xpcs_1000basex_features, 1283 .an_mode = DW_AN_C37_1000BASEX, 1284 }, { 1285 .interface = PHY_INTERFACE_MODE_2500BASEX, 1286 .supported = xpcs_2500basex_features, 1287 .an_mode = DW_2500BASEX, 1288 }, { 1289 } 1290 }; 1291 1292 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { 1293 { 1294 .interface = PHY_INTERFACE_MODE_SGMII, 1295 .supported = xpcs_sgmii_features, 1296 .an_mode = DW_AN_C37_SGMII, 1297 .pma_config = nxp_sja1105_sgmii_pma_config, 1298 }, { 1299 } 1300 }; 1301 1302 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { 1303 { 1304 .interface = PHY_INTERFACE_MODE_SGMII, 1305 .supported = xpcs_sgmii_features, 1306 .an_mode = DW_AN_C37_SGMII, 1307 .pma_config = nxp_sja1110_sgmii_pma_config, 1308 }, { 1309 .interface = PHY_INTERFACE_MODE_2500BASEX, 1310 .supported = xpcs_2500basex_features, 1311 .an_mode = DW_2500BASEX, 1312 .pma_config = nxp_sja1110_2500basex_pma_config, 1313 }, { 1314 } 1315 }; 1316 1317 static const struct dw_xpcs_desc xpcs_desc_list[] = { 1318 { 1319 .id = DW_XPCS_ID, 1320 .mask = DW_XPCS_ID_MASK, 1321 .compat = synopsys_xpcs_compat, 1322 }, { 1323 .id = NXP_SJA1105_XPCS_ID, 1324 .mask = DW_XPCS_ID_MASK, 1325 .compat = nxp_sja1105_xpcs_compat, 1326 }, { 1327 .id = NXP_SJA1110_XPCS_ID, 1328 .mask = DW_XPCS_ID_MASK, 1329 .compat = nxp_sja1110_xpcs_compat, 1330 }, 1331 }; 1332 1333 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1334 .pcs_validate = xpcs_validate, 1335 .pcs_inband_caps = xpcs_inband_caps, 1336 .pcs_pre_config = xpcs_pre_config, 1337 .pcs_config = xpcs_config, 1338 .pcs_get_state = xpcs_get_state, 1339 .pcs_an_restart = xpcs_an_restart, 1340 .pcs_link_up = xpcs_link_up, 1341 }; 1342 1343 static int xpcs_identify(struct dw_xpcs *xpcs) 1344 { 1345 int i, ret; 1346 1347 ret = xpcs_read_ids(xpcs); 1348 if (ret < 0) 1349 return ret; 1350 1351 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { 1352 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; 1353 1354 if ((xpcs->info.pcs & entry->mask) == entry->id) { 1355 xpcs->desc = entry; 1356 return 0; 1357 } 1358 } 1359 1360 return -ENODEV; 1361 } 1362 1363 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) 1364 { 1365 struct dw_xpcs *xpcs; 1366 1367 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); 1368 if (!xpcs) 1369 return ERR_PTR(-ENOMEM); 1370 1371 mdio_device_get(mdiodev); 1372 xpcs->mdiodev = mdiodev; 1373 xpcs->pcs.ops = &xpcs_phylink_ops; 1374 xpcs->pcs.neg_mode = true; 1375 xpcs->pcs.poll = true; 1376 1377 return xpcs; 1378 } 1379 1380 static void xpcs_free_data(struct dw_xpcs *xpcs) 1381 { 1382 mdio_device_put(xpcs->mdiodev); 1383 kfree(xpcs); 1384 } 1385 1386 static int xpcs_init_clks(struct dw_xpcs *xpcs) 1387 { 1388 static const char *ids[DW_XPCS_NUM_CLKS] = { 1389 [DW_XPCS_CORE_CLK] = "core", 1390 [DW_XPCS_PAD_CLK] = "pad", 1391 }; 1392 struct device *dev = &xpcs->mdiodev->dev; 1393 int ret, i; 1394 1395 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) 1396 xpcs->clks[i].id = ids[i]; 1397 1398 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); 1399 if (ret) 1400 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1401 1402 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); 1403 if (ret) 1404 return dev_err_probe(dev, ret, "Failed to enable clocks\n"); 1405 1406 return 0; 1407 } 1408 1409 static void xpcs_clear_clks(struct dw_xpcs *xpcs) 1410 { 1411 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); 1412 1413 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1414 } 1415 1416 static int xpcs_init_id(struct dw_xpcs *xpcs) 1417 { 1418 const struct dw_xpcs_info *info; 1419 1420 info = dev_get_platdata(&xpcs->mdiodev->dev); 1421 if (!info) { 1422 xpcs->info.pcs = DW_XPCS_ID_NATIVE; 1423 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; 1424 } else { 1425 xpcs->info = *info; 1426 } 1427 1428 return xpcs_identify(xpcs); 1429 } 1430 1431 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) 1432 { 1433 struct dw_xpcs *xpcs; 1434 int ret; 1435 1436 xpcs = xpcs_create_data(mdiodev); 1437 if (IS_ERR(xpcs)) 1438 return xpcs; 1439 1440 ret = xpcs_init_clks(xpcs); 1441 if (ret) 1442 goto out_free_data; 1443 1444 ret = xpcs_init_id(xpcs); 1445 if (ret) 1446 goto out_clear_clks; 1447 1448 xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); 1449 1450 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 1451 xpcs->pcs.poll = false; 1452 else 1453 xpcs->need_reset = true; 1454 1455 return xpcs; 1456 1457 out_clear_clks: 1458 xpcs_clear_clks(xpcs); 1459 1460 out_free_data: 1461 xpcs_free_data(xpcs); 1462 1463 return ERR_PTR(ret); 1464 } 1465 1466 /** 1467 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr 1468 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at 1469 * @addr: device MDIO-bus ID 1470 * 1471 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1472 * the PCS device couldn't be found on the bus and other negative errno related 1473 * to the data allocation and MDIO-bus communications. 1474 */ 1475 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) 1476 { 1477 struct mdio_device *mdiodev; 1478 struct dw_xpcs *xpcs; 1479 1480 mdiodev = mdio_device_create(bus, addr); 1481 if (IS_ERR(mdiodev)) 1482 return ERR_CAST(mdiodev); 1483 1484 xpcs = xpcs_create(mdiodev); 1485 1486 /* xpcs_create() has taken a refcount on the mdiodev if it was 1487 * successful. If xpcs_create() fails, this will free the mdio 1488 * device here. In any case, we don't need to hold our reference 1489 * anymore, and putting it here will allow mdio_device_put() in 1490 * xpcs_destroy() to automatically free the mdio device. 1491 */ 1492 mdio_device_put(mdiodev); 1493 1494 return xpcs; 1495 } 1496 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1497 1498 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) 1499 { 1500 struct dw_xpcs *xpcs; 1501 1502 xpcs = xpcs_create_mdiodev(bus, addr); 1503 if (IS_ERR(xpcs)) 1504 return ERR_CAST(xpcs); 1505 1506 return &xpcs->pcs; 1507 } 1508 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); 1509 1510 /** 1511 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode 1512 * @fwnode: fwnode handle poining to the DW XPCS device 1513 * 1514 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1515 * the fwnode device is unavailable or the PCS device couldn't be found on the 1516 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, 1517 * other negative errno related to the data allocations and MDIO-bus 1518 * communications. 1519 */ 1520 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) 1521 { 1522 struct mdio_device *mdiodev; 1523 struct dw_xpcs *xpcs; 1524 1525 if (!fwnode_device_is_available(fwnode)) 1526 return ERR_PTR(-ENODEV); 1527 1528 mdiodev = fwnode_mdio_find_device(fwnode); 1529 if (!mdiodev) 1530 return ERR_PTR(-EPROBE_DEFER); 1531 1532 xpcs = xpcs_create(mdiodev); 1533 1534 /* xpcs_create() has taken a refcount on the mdiodev if it was 1535 * successful. If xpcs_create() fails, this will free the mdio 1536 * device here. In any case, we don't need to hold our reference 1537 * anymore, and putting it here will allow mdio_device_put() in 1538 * xpcs_destroy() to automatically free the mdio device. 1539 */ 1540 mdio_device_put(mdiodev); 1541 1542 return xpcs; 1543 } 1544 EXPORT_SYMBOL_GPL(xpcs_create_fwnode); 1545 1546 void xpcs_destroy(struct dw_xpcs *xpcs) 1547 { 1548 if (!xpcs) 1549 return; 1550 1551 xpcs_clear_clks(xpcs); 1552 1553 xpcs_free_data(xpcs); 1554 } 1555 EXPORT_SYMBOL_GPL(xpcs_destroy); 1556 1557 void xpcs_destroy_pcs(struct phylink_pcs *pcs) 1558 { 1559 xpcs_destroy(phylink_pcs_to_xpcs(pcs)); 1560 } 1561 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); 1562 1563 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); 1564 MODULE_LICENSE("GPL v2"); 1565