1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/pcs/pcs-xpcs.h> 12 #include <linux/mdio.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 #include <linux/property.h> 16 17 #include "pcs-xpcs.h" 18 19 #define phylink_pcs_to_xpcs(pl_pcs) \ 20 container_of((pl_pcs), struct dw_xpcs, pcs) 21 22 static const int xpcs_usxgmii_features[] = { 23 ETHTOOL_LINK_MODE_Pause_BIT, 24 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 25 ETHTOOL_LINK_MODE_Autoneg_BIT, 26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 30 __ETHTOOL_LINK_MODE_MASK_NBITS, 31 }; 32 33 static const int xpcs_10gkr_features[] = { 34 ETHTOOL_LINK_MODE_Pause_BIT, 35 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 37 __ETHTOOL_LINK_MODE_MASK_NBITS, 38 }; 39 40 static const int xpcs_xlgmii_features[] = { 41 ETHTOOL_LINK_MODE_Pause_BIT, 42 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 43 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 44 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 45 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 46 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 47 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 48 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 49 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 50 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 51 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 52 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 53 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 54 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 55 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 56 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 57 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 58 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 59 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 60 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 61 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 62 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 63 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 64 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 65 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 66 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 67 __ETHTOOL_LINK_MODE_MASK_NBITS, 68 }; 69 70 static const int xpcs_10gbaser_features[] = { 71 ETHTOOL_LINK_MODE_Pause_BIT, 72 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 73 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 74 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 75 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 76 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 77 __ETHTOOL_LINK_MODE_MASK_NBITS, 78 }; 79 80 static const int xpcs_sgmii_features[] = { 81 ETHTOOL_LINK_MODE_Pause_BIT, 82 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 83 ETHTOOL_LINK_MODE_Autoneg_BIT, 84 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 85 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 86 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 87 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 88 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 89 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 90 __ETHTOOL_LINK_MODE_MASK_NBITS, 91 }; 92 93 static const int xpcs_1000basex_features[] = { 94 ETHTOOL_LINK_MODE_Pause_BIT, 95 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 96 ETHTOOL_LINK_MODE_Autoneg_BIT, 97 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 98 __ETHTOOL_LINK_MODE_MASK_NBITS, 99 }; 100 101 static const int xpcs_2500basex_features[] = { 102 ETHTOOL_LINK_MODE_Pause_BIT, 103 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 104 ETHTOOL_LINK_MODE_Autoneg_BIT, 105 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 106 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 107 __ETHTOOL_LINK_MODE_MASK_NBITS, 108 }; 109 110 struct dw_xpcs_compat { 111 phy_interface_t interface; 112 const int *supported; 113 int an_mode; 114 int (*pma_config)(struct dw_xpcs *xpcs); 115 }; 116 117 struct dw_xpcs_desc { 118 u32 id; 119 u32 mask; 120 const struct dw_xpcs_compat *compat; 121 }; 122 123 static const struct dw_xpcs_compat * 124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) 125 { 126 const struct dw_xpcs_compat *compat; 127 128 for (compat = xpcs->desc->compat; compat->supported; compat++) 129 if (compat->interface == interface) 130 return compat; 131 132 return NULL; 133 } 134 135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) 136 { 137 return &xpcs->pcs; 138 } 139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); 140 141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 142 { 143 const struct dw_xpcs_compat *compat; 144 145 compat = xpcs_find_compat(xpcs, interface); 146 if (!compat) 147 return -ENODEV; 148 149 return compat->an_mode; 150 } 151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 152 153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, 154 enum ethtool_link_mode_bit_indices linkmode) 155 { 156 int i; 157 158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 159 if (compat->supported[i] == linkmode) 160 return true; 161 162 return false; 163 } 164 165 #define xpcs_linkmode_supported(compat, mode) \ 166 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 167 168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 169 { 170 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 171 } 172 173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 174 { 175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 176 } 177 178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 179 { 180 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 181 } 182 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 184 u16 mask, u16 set) 185 { 186 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 187 } 188 189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 190 { 191 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 192 } 193 194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 195 u16 val) 196 { 197 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 198 } 199 200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 201 u16 set) 202 { 203 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 204 } 205 206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 207 { 208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 209 } 210 211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 212 { 213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 214 } 215 216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 217 { 218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 219 } 220 221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 222 { 223 int ret, val; 224 225 ret = read_poll_timeout(xpcs_read, val, 226 val < 0 || !(val & BMCR_RESET), 227 50000, 600000, true, xpcs, dev, MII_BMCR); 228 if (val < 0) 229 ret = val; 230 231 return ret; 232 } 233 234 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 235 const struct dw_xpcs_compat *compat) 236 { 237 int ret, dev; 238 239 switch (compat->an_mode) { 240 case DW_AN_C73: 241 case DW_10GBASER: 242 dev = MDIO_MMD_PCS; 243 break; 244 case DW_AN_C37_SGMII: 245 case DW_2500BASEX: 246 case DW_AN_C37_1000BASEX: 247 dev = MDIO_MMD_VEND2; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET); 254 if (ret < 0) 255 return ret; 256 257 return xpcs_poll_reset(xpcs, dev); 258 } 259 260 #define xpcs_warn(__xpcs, __state, __args...) \ 261 ({ \ 262 if ((__state)->link) \ 263 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 264 }) 265 266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 267 struct phylink_link_state *state, 268 u16 pcs_stat1) 269 { 270 int ret; 271 272 if (pcs_stat1 & MDIO_STAT1_FAULT) { 273 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 274 return -EFAULT; 275 } 276 277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 278 if (ret < 0) 279 return ret; 280 281 if (ret & MDIO_STAT2_RXFAULT) 282 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 283 if (ret & MDIO_STAT2_TXFAULT) 284 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 285 286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 287 if (ret < 0) 288 return ret; 289 290 if (ret & DW_RXFIFO_ERR) { 291 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 292 return -EFAULT; 293 } 294 295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 296 if (ret < 0) 297 return ret; 298 299 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 300 xpcs_warn(xpcs, state, "Link is not locked!\n"); 301 302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 303 if (ret < 0) 304 return ret; 305 306 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 307 xpcs_warn(xpcs, state, "Link has errors!\n"); 308 return -EFAULT; 309 } 310 311 return 0; 312 } 313 314 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) 315 { 316 int ret, speed_sel; 317 318 switch (speed) { 319 case SPEED_10: 320 speed_sel = DW_USXGMII_10; 321 break; 322 case SPEED_100: 323 speed_sel = DW_USXGMII_100; 324 break; 325 case SPEED_1000: 326 speed_sel = DW_USXGMII_1000; 327 break; 328 case SPEED_2500: 329 speed_sel = DW_USXGMII_2500; 330 break; 331 case SPEED_5000: 332 speed_sel = DW_USXGMII_5000; 333 break; 334 case SPEED_10000: 335 speed_sel = DW_USXGMII_10000; 336 break; 337 default: 338 /* Nothing to do here */ 339 return; 340 } 341 342 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 343 if (ret < 0) 344 goto out; 345 346 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, 347 speed_sel | DW_USXGMII_FULL); 348 if (ret < 0) 349 goto out; 350 351 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 352 DW_USXGMII_RST); 353 if (ret < 0) 354 goto out; 355 356 return; 357 358 out: 359 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", 360 __func__, ERR_PTR(ret)); 361 } 362 363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 364 const struct dw_xpcs_compat *compat) 365 { 366 int ret, adv; 367 368 /* By default, in USXGMII mode XPCS operates at 10G baud and 369 * replicates data to achieve lower speeds. Hereby, in this 370 * default configuration we need to advertise all supported 371 * modes and not only the ones we want to use. 372 */ 373 374 /* SR_AN_ADV3 */ 375 adv = 0; 376 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 377 adv |= DW_C73_2500KX; 378 379 /* TODO: 5000baseKR */ 380 381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 382 if (ret < 0) 383 return ret; 384 385 /* SR_AN_ADV2 */ 386 adv = 0; 387 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 388 adv |= DW_C73_1000KX; 389 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 390 adv |= DW_C73_10000KX4; 391 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 392 adv |= DW_C73_10000KR; 393 394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 395 if (ret < 0) 396 return ret; 397 398 /* SR_AN_ADV1 */ 399 adv = DW_C73_AN_ADV_SF; 400 if (xpcs_linkmode_supported(compat, Pause)) 401 adv |= DW_C73_PAUSE; 402 if (xpcs_linkmode_supported(compat, Asym_Pause)) 403 adv |= DW_C73_ASYM_PAUSE; 404 405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 406 } 407 408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 409 const struct dw_xpcs_compat *compat) 410 { 411 int ret; 412 413 ret = _xpcs_config_aneg_c73(xpcs, compat); 414 if (ret < 0) 415 return ret; 416 417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 418 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 419 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 420 } 421 422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 423 struct phylink_link_state *state, 424 const struct dw_xpcs_compat *compat, u16 an_stat1) 425 { 426 int ret; 427 428 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 430 if (ret < 0) 431 return ret; 432 433 /* Check if Aneg outcome is valid */ 434 if (!(ret & DW_C73_AN_ADV_SF)) { 435 xpcs_config_aneg_c73(xpcs, compat); 436 return 0; 437 } 438 439 return 1; 440 } 441 442 return 0; 443 } 444 445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 446 struct phylink_link_state *state, u16 an_stat1) 447 { 448 u16 lpa[3]; 449 int i, ret; 450 451 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 452 phylink_clear(state->lp_advertising, Autoneg); 453 return 0; 454 } 455 456 phylink_set(state->lp_advertising, Autoneg); 457 458 /* Read Clause 73 link partner advertisement */ 459 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 461 if (ret < 0) 462 return ret; 463 464 lpa[i] = ret; 465 } 466 467 mii_c73_mod_linkmode(state->lp_advertising, lpa); 468 469 return 0; 470 } 471 472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 473 struct phylink_link_state *state) 474 { 475 unsigned long *adv = state->advertising; 476 int speed = SPEED_UNKNOWN; 477 int bit; 478 479 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 480 int new_speed = SPEED_UNKNOWN; 481 482 switch (bit) { 483 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 484 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 485 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 486 new_speed = SPEED_25000; 487 break; 488 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 489 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 490 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 491 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 492 new_speed = SPEED_40000; 493 break; 494 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 495 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 496 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 497 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 498 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 499 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 500 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 501 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 502 new_speed = SPEED_50000; 503 break; 504 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 505 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 506 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 507 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 508 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 509 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 510 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 511 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 512 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 513 new_speed = SPEED_100000; 514 break; 515 default: 516 continue; 517 } 518 519 if (new_speed > speed) 520 speed = new_speed; 521 } 522 523 return speed; 524 } 525 526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs, 527 struct phylink_link_state *state) 528 { 529 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 530 state->duplex = DUPLEX_FULL; 531 532 switch (state->interface) { 533 case PHY_INTERFACE_MODE_10GKR: 534 state->speed = SPEED_10000; 535 break; 536 case PHY_INTERFACE_MODE_XLGMII: 537 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 538 break; 539 default: 540 state->speed = SPEED_UNKNOWN; 541 break; 542 } 543 } 544 545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 546 const struct phylink_link_state *state) 547 { 548 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 549 const struct dw_xpcs_compat *compat; 550 struct dw_xpcs *xpcs; 551 int i; 552 553 xpcs = phylink_pcs_to_xpcs(pcs); 554 compat = xpcs_find_compat(xpcs, state->interface); 555 if (!compat) 556 return -EINVAL; 557 558 /* Populate the supported link modes for this PHY interface type. 559 * FIXME: what about the port modes and autoneg bit? This masks 560 * all those away. 561 */ 562 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 563 set_bit(compat->supported[i], xpcs_supported); 564 565 linkmode_and(supported, supported, xpcs_supported); 566 567 return 0; 568 } 569 570 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 571 { 572 const struct dw_xpcs_compat *compat; 573 574 for (compat = xpcs->desc->compat; compat->supported; compat++) 575 __set_bit(compat->interface, interfaces); 576 } 577 EXPORT_SYMBOL_GPL(xpcs_get_interfaces); 578 579 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) 580 { 581 u16 mask, val; 582 int ret; 583 584 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 585 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 586 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 587 DW_VR_MII_EEE_MULT_FACT_100NS; 588 589 if (enable) 590 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 591 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 592 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 593 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 594 mult_fact_100ns); 595 else 596 val = 0; 597 598 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 599 val); 600 if (ret < 0) 601 return ret; 602 603 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 604 DW_VR_MII_EEE_TRN_LPI, 605 enable ? DW_VR_MII_EEE_TRN_LPI : 0); 606 } 607 EXPORT_SYMBOL_GPL(xpcs_config_eee); 608 609 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) 610 { 611 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 612 const struct dw_xpcs_compat *compat; 613 int ret; 614 615 if (!xpcs->need_reset) 616 return; 617 618 compat = xpcs_find_compat(xpcs, interface); 619 if (!compat) { 620 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", 621 phy_modes(interface)); 622 return; 623 } 624 625 ret = xpcs_soft_reset(xpcs, compat); 626 if (ret) 627 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", 628 ERR_PTR(ret)); 629 630 xpcs->need_reset = false; 631 } 632 633 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, 634 unsigned int neg_mode) 635 { 636 int ret, mdio_ctrl, tx_conf; 637 u16 mask, val; 638 639 /* For AN for C37 SGMII mode, the settings are :- 640 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 641 it is already enabled) 642 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 643 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 644 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 645 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 646 * speed/duplex mode change by HW after SGMII AN complete) 647 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 648 * 649 * Note that VR_MII_MMD_CTRL is MII_BMCR. 650 * 651 * Note: Since it is MAC side SGMII, there is no need to set 652 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 653 * PHY about the link state change after C28 AN is completed 654 * between PHY and Link Partner. There is also no need to 655 * trigger AN restart for MAC-side SGMII. 656 */ 657 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 658 if (mdio_ctrl < 0) 659 return mdio_ctrl; 660 661 if (mdio_ctrl & BMCR_ANENABLE) { 662 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 663 mdio_ctrl & ~BMCR_ANENABLE); 664 if (ret < 0) 665 return ret; 666 } 667 668 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 669 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 670 DW_VR_MII_PCS_MODE_C37_SGMII); 671 672 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 673 mask |= DW_VR_MII_AN_CTRL_8BIT; 674 val |= DW_VR_MII_AN_CTRL_8BIT; 675 /* Hardware requires it to be PHY side SGMII */ 676 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 677 } else { 678 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 679 } 680 681 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 682 683 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 684 if (ret < 0) 685 return ret; 686 687 val = 0; 688 mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 689 690 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 691 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 692 693 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 694 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 695 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 696 } 697 698 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 699 if (ret < 0) 700 return ret; 701 702 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 703 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 704 mdio_ctrl | BMCR_ANENABLE); 705 706 return ret; 707 } 708 709 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, 710 unsigned int neg_mode, 711 const unsigned long *advertising) 712 { 713 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 714 int ret, mdio_ctrl, adv; 715 bool changed = 0; 716 u16 mask, val; 717 718 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 719 * be disabled first:- 720 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 721 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 722 * 723 * Note that VR_MII_MMD_CTRL is MII_BMCR. 724 */ 725 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 726 if (mdio_ctrl < 0) 727 return mdio_ctrl; 728 729 if (mdio_ctrl & BMCR_ANENABLE) { 730 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 731 mdio_ctrl & ~BMCR_ANENABLE); 732 if (ret < 0) 733 return ret; 734 } 735 736 mask = DW_VR_MII_PCS_MODE_MASK; 737 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 738 DW_VR_MII_PCS_MODE_C37_1000BASEX); 739 740 if (!xpcs->pcs.poll) { 741 mask |= DW_VR_MII_AN_INTR_EN; 742 val |= DW_VR_MII_AN_INTR_EN; 743 } 744 745 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 746 if (ret < 0) 747 return ret; 748 749 /* Check for advertising changes and update the C45 MII ADV 750 * register accordingly. 751 */ 752 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 753 advertising); 754 if (adv >= 0) { 755 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 756 MII_ADVERTISE, 0xffff, adv); 757 if (ret < 0) 758 return ret; 759 760 changed = ret; 761 } 762 763 /* Clear CL37 AN complete status */ 764 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 765 if (ret < 0) 766 return ret; 767 768 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 769 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 770 mdio_ctrl | BMCR_ANENABLE); 771 if (ret < 0) 772 return ret; 773 } 774 775 return changed; 776 } 777 778 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 779 { 780 int ret; 781 782 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 783 DW_VR_MII_DIG_CTRL1_2G5_EN | 784 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 785 DW_VR_MII_DIG_CTRL1_2G5_EN); 786 if (ret < 0) 787 return ret; 788 789 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, 790 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100, 791 BMCR_SPEED1000); 792 } 793 794 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 795 const unsigned long *advertising, 796 unsigned int neg_mode) 797 { 798 const struct dw_xpcs_compat *compat; 799 int ret; 800 801 compat = xpcs_find_compat(xpcs, interface); 802 if (!compat) 803 return -ENODEV; 804 805 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 806 ret = txgbe_xpcs_switch_mode(xpcs, interface); 807 if (ret) 808 return ret; 809 810 /* Wangxun devices need backplane CL37 AN enabled for 811 * SGMII and 1000base-X 812 */ 813 if (interface == PHY_INTERFACE_MODE_SGMII || 814 interface == PHY_INTERFACE_MODE_1000BASEX) 815 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, 816 DW_CL37_BP | DW_EN_VSMMD1); 817 } 818 819 switch (compat->an_mode) { 820 case DW_10GBASER: 821 break; 822 case DW_AN_C73: 823 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 824 ret = xpcs_config_aneg_c73(xpcs, compat); 825 if (ret) 826 return ret; 827 } 828 break; 829 case DW_AN_C37_SGMII: 830 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode); 831 if (ret) 832 return ret; 833 break; 834 case DW_AN_C37_1000BASEX: 835 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode, 836 advertising); 837 if (ret) 838 return ret; 839 break; 840 case DW_2500BASEX: 841 ret = xpcs_config_2500basex(xpcs); 842 if (ret) 843 return ret; 844 break; 845 default: 846 return -EINVAL; 847 } 848 849 if (compat->pma_config) { 850 ret = compat->pma_config(xpcs); 851 if (ret) 852 return ret; 853 } 854 855 return 0; 856 } 857 858 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 859 phy_interface_t interface, 860 const unsigned long *advertising, 861 bool permit_pause_to_mac) 862 { 863 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 864 865 return xpcs_do_config(xpcs, interface, advertising, neg_mode); 866 } 867 868 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 869 struct phylink_link_state *state, 870 const struct dw_xpcs_compat *compat) 871 { 872 bool an_enabled; 873 int pcs_stat1; 874 int an_stat1; 875 int ret; 876 877 /* The link status bit is latching-low, so it is important to 878 * avoid unnecessary re-reads of this register to avoid missing 879 * a link-down event. 880 */ 881 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 882 if (pcs_stat1 < 0) { 883 state->link = false; 884 return pcs_stat1; 885 } 886 887 /* Link needs to be read first ... */ 888 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 889 890 /* ... and then we check the faults. */ 891 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 892 if (ret) { 893 ret = xpcs_soft_reset(xpcs, compat); 894 if (ret) 895 return ret; 896 897 state->link = 0; 898 899 return xpcs_do_config(xpcs, state->interface, NULL, 900 PHYLINK_PCS_NEG_INBAND_ENABLED); 901 } 902 903 /* There is no point doing anything else if the link is down. */ 904 if (!state->link) 905 return 0; 906 907 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 908 state->advertising); 909 if (an_enabled) { 910 /* The link status bit is latching-low, so it is important to 911 * avoid unnecessary re-reads of this register to avoid missing 912 * a link-down event. 913 */ 914 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 915 if (an_stat1 < 0) { 916 state->link = false; 917 return an_stat1; 918 } 919 920 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 921 an_stat1); 922 if (!state->an_complete) { 923 state->link = false; 924 return 0; 925 } 926 927 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 928 if (ret < 0) { 929 state->link = false; 930 return ret; 931 } 932 933 phylink_resolve_c73(state); 934 } else { 935 xpcs_resolve_pma(xpcs, state); 936 } 937 938 return 0; 939 } 940 941 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 942 struct phylink_link_state *state) 943 { 944 int ret; 945 946 /* Reset link_state */ 947 state->link = false; 948 state->speed = SPEED_UNKNOWN; 949 state->duplex = DUPLEX_UNKNOWN; 950 state->pause = 0; 951 952 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 953 * status, speed and duplex. 954 */ 955 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 956 if (ret < 0) 957 return ret; 958 959 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 960 int speed_value; 961 962 state->link = true; 963 964 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 965 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 966 state->speed = SPEED_1000; 967 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 968 state->speed = SPEED_100; 969 else 970 state->speed = SPEED_10; 971 972 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 973 state->duplex = DUPLEX_FULL; 974 else 975 state->duplex = DUPLEX_HALF; 976 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 977 int speed, duplex; 978 979 state->link = true; 980 981 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 982 if (speed < 0) 983 return speed; 984 985 speed &= BMCR_SPEED100 | BMCR_SPEED1000; 986 if (speed == BMCR_SPEED1000) 987 state->speed = SPEED_1000; 988 else if (speed == BMCR_SPEED100) 989 state->speed = SPEED_100; 990 else if (speed == 0) 991 state->speed = SPEED_10; 992 993 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE); 994 if (duplex < 0) 995 return duplex; 996 997 if (duplex & ADVERTISE_1000XFULL) 998 state->duplex = DUPLEX_FULL; 999 else if (duplex & ADVERTISE_1000XHALF) 1000 state->duplex = DUPLEX_HALF; 1001 1002 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 1009 struct phylink_link_state *state) 1010 { 1011 int lpa, bmsr; 1012 1013 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1014 state->advertising)) { 1015 /* Reset link state */ 1016 state->link = false; 1017 1018 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 1019 if (lpa < 0 || lpa & LPA_RFAULT) 1020 return lpa; 1021 1022 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1023 if (bmsr < 0) 1024 return bmsr; 1025 1026 /* Clear AN complete interrupt */ 1027 if (!xpcs->pcs.poll) { 1028 int an_intr; 1029 1030 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1031 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1032 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1033 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr); 1034 } 1035 } 1036 1037 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa); 1038 } 1039 1040 return 0; 1041 } 1042 1043 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, 1044 struct phylink_link_state *state) 1045 { 1046 int ret; 1047 1048 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1049 if (ret < 0) { 1050 state->link = 0; 1051 return ret; 1052 } 1053 1054 state->link = !!(ret & BMSR_LSTATUS); 1055 if (!state->link) 1056 return 0; 1057 1058 state->speed = SPEED_2500; 1059 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 1060 state->duplex = DUPLEX_FULL; 1061 1062 return 0; 1063 } 1064 1065 static void xpcs_get_state(struct phylink_pcs *pcs, 1066 struct phylink_link_state *state) 1067 { 1068 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1069 const struct dw_xpcs_compat *compat; 1070 int ret; 1071 1072 compat = xpcs_find_compat(xpcs, state->interface); 1073 if (!compat) 1074 return; 1075 1076 switch (compat->an_mode) { 1077 case DW_10GBASER: 1078 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1079 break; 1080 case DW_AN_C73: 1081 ret = xpcs_get_state_c73(xpcs, state, compat); 1082 if (ret) 1083 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1084 "xpcs_get_state_c73", ERR_PTR(ret)); 1085 break; 1086 case DW_AN_C37_SGMII: 1087 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1088 if (ret) 1089 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1090 "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); 1091 break; 1092 case DW_AN_C37_1000BASEX: 1093 ret = xpcs_get_state_c37_1000basex(xpcs, state); 1094 if (ret) 1095 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1096 "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); 1097 break; 1098 case DW_2500BASEX: 1099 ret = xpcs_get_state_2500basex(xpcs, state); 1100 if (ret) 1101 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1102 "xpcs_get_state_2500basex", ERR_PTR(ret)); 1103 break; 1104 default: 1105 return; 1106 } 1107 } 1108 1109 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, 1110 unsigned int neg_mode, 1111 phy_interface_t interface, 1112 int speed, int duplex) 1113 { 1114 int ret; 1115 1116 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1117 return; 1118 1119 if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1120 if (speed != SPEED_1000) { 1121 dev_err(&xpcs->mdiodev->dev, 1122 "%s: speed %dMbps not supported\n", 1123 __func__, speed); 1124 return; 1125 } 1126 1127 if (duplex != DUPLEX_FULL) 1128 dev_err(&xpcs->mdiodev->dev, 1129 "%s: half duplex not supported\n", 1130 __func__); 1131 } 1132 1133 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 1134 mii_bmcr_encode_fixed(speed, duplex)); 1135 if (ret) 1136 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1137 __func__, ERR_PTR(ret)); 1138 } 1139 1140 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 1141 phy_interface_t interface, int speed, int duplex) 1142 { 1143 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1144 1145 switch (interface) { 1146 case PHY_INTERFACE_MODE_USXGMII: 1147 xpcs_link_up_usxgmii(xpcs, speed); 1148 break; 1149 1150 case PHY_INTERFACE_MODE_SGMII: 1151 case PHY_INTERFACE_MODE_1000BASEX: 1152 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed, 1153 duplex); 1154 break; 1155 1156 default: 1157 break; 1158 } 1159 } 1160 1161 static void xpcs_an_restart(struct phylink_pcs *pcs) 1162 { 1163 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1164 1165 xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, 1166 BMCR_ANRESTART); 1167 } 1168 1169 static int xpcs_read_ids(struct dw_xpcs *xpcs) 1170 { 1171 int ret; 1172 u32 id; 1173 1174 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication 1175 * failed indicating that device couldn't be reached. 1176 */ 1177 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1178 if (ret < 0) 1179 return -ENODEV; 1180 1181 id = ret << 16; 1182 1183 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1184 if (ret < 0) 1185 return ret; 1186 1187 id |= ret; 1188 1189 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 1190 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 1191 * PCS in MII MMD 31. 1192 */ 1193 if (!id || id == 0xffffffff) { 1194 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1195 if (ret < 0) 1196 return ret; 1197 1198 id = ret << 16; 1199 1200 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1201 if (ret < 0) 1202 return ret; 1203 1204 id |= ret; 1205 } 1206 1207 /* Set the PCS ID if it hasn't been pre-initialized */ 1208 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) 1209 xpcs->info.pcs = id; 1210 1211 /* Find out PMA/PMD ID from MMD 1 device ID registers */ 1212 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); 1213 if (ret < 0) 1214 return ret; 1215 1216 id = ret; 1217 1218 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); 1219 if (ret < 0) 1220 return ret; 1221 1222 /* Note the inverted dword order and masked out Model/Revision numbers 1223 * with respect to what is done with the PCS ID... 1224 */ 1225 ret = (ret >> 10) & 0x3F; 1226 id |= ret << 16; 1227 1228 /* Set the PMA ID if it hasn't been pre-initialized */ 1229 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) 1230 xpcs->info.pma = id; 1231 1232 return 0; 1233 } 1234 1235 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { 1236 { 1237 .interface = PHY_INTERFACE_MODE_USXGMII, 1238 .supported = xpcs_usxgmii_features, 1239 .an_mode = DW_AN_C73, 1240 }, { 1241 .interface = PHY_INTERFACE_MODE_10GKR, 1242 .supported = xpcs_10gkr_features, 1243 .an_mode = DW_AN_C73, 1244 }, { 1245 .interface = PHY_INTERFACE_MODE_XLGMII, 1246 .supported = xpcs_xlgmii_features, 1247 .an_mode = DW_AN_C73, 1248 }, { 1249 .interface = PHY_INTERFACE_MODE_10GBASER, 1250 .supported = xpcs_10gbaser_features, 1251 .an_mode = DW_10GBASER, 1252 }, { 1253 .interface = PHY_INTERFACE_MODE_SGMII, 1254 .supported = xpcs_sgmii_features, 1255 .an_mode = DW_AN_C37_SGMII, 1256 }, { 1257 .interface = PHY_INTERFACE_MODE_1000BASEX, 1258 .supported = xpcs_1000basex_features, 1259 .an_mode = DW_AN_C37_1000BASEX, 1260 }, { 1261 .interface = PHY_INTERFACE_MODE_2500BASEX, 1262 .supported = xpcs_2500basex_features, 1263 .an_mode = DW_2500BASEX, 1264 }, { 1265 } 1266 }; 1267 1268 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { 1269 { 1270 .interface = PHY_INTERFACE_MODE_SGMII, 1271 .supported = xpcs_sgmii_features, 1272 .an_mode = DW_AN_C37_SGMII, 1273 .pma_config = nxp_sja1105_sgmii_pma_config, 1274 }, { 1275 } 1276 }; 1277 1278 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { 1279 { 1280 .interface = PHY_INTERFACE_MODE_SGMII, 1281 .supported = xpcs_sgmii_features, 1282 .an_mode = DW_AN_C37_SGMII, 1283 .pma_config = nxp_sja1110_sgmii_pma_config, 1284 }, { 1285 .interface = PHY_INTERFACE_MODE_2500BASEX, 1286 .supported = xpcs_2500basex_features, 1287 .an_mode = DW_2500BASEX, 1288 .pma_config = nxp_sja1110_2500basex_pma_config, 1289 }, { 1290 } 1291 }; 1292 1293 static const struct dw_xpcs_desc xpcs_desc_list[] = { 1294 { 1295 .id = DW_XPCS_ID, 1296 .mask = DW_XPCS_ID_MASK, 1297 .compat = synopsys_xpcs_compat, 1298 }, { 1299 .id = NXP_SJA1105_XPCS_ID, 1300 .mask = DW_XPCS_ID_MASK, 1301 .compat = nxp_sja1105_xpcs_compat, 1302 }, { 1303 .id = NXP_SJA1110_XPCS_ID, 1304 .mask = DW_XPCS_ID_MASK, 1305 .compat = nxp_sja1110_xpcs_compat, 1306 }, 1307 }; 1308 1309 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1310 .pcs_validate = xpcs_validate, 1311 .pcs_pre_config = xpcs_pre_config, 1312 .pcs_config = xpcs_config, 1313 .pcs_get_state = xpcs_get_state, 1314 .pcs_an_restart = xpcs_an_restart, 1315 .pcs_link_up = xpcs_link_up, 1316 }; 1317 1318 static int xpcs_identify(struct dw_xpcs *xpcs) 1319 { 1320 int i, ret; 1321 1322 ret = xpcs_read_ids(xpcs); 1323 if (ret < 0) 1324 return ret; 1325 1326 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { 1327 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; 1328 1329 if ((xpcs->info.pcs & entry->mask) == entry->id) { 1330 xpcs->desc = entry; 1331 return 0; 1332 } 1333 } 1334 1335 return -ENODEV; 1336 } 1337 1338 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) 1339 { 1340 struct dw_xpcs *xpcs; 1341 1342 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); 1343 if (!xpcs) 1344 return ERR_PTR(-ENOMEM); 1345 1346 mdio_device_get(mdiodev); 1347 xpcs->mdiodev = mdiodev; 1348 xpcs->pcs.ops = &xpcs_phylink_ops; 1349 xpcs->pcs.neg_mode = true; 1350 xpcs->pcs.poll = true; 1351 1352 return xpcs; 1353 } 1354 1355 static void xpcs_free_data(struct dw_xpcs *xpcs) 1356 { 1357 mdio_device_put(xpcs->mdiodev); 1358 kfree(xpcs); 1359 } 1360 1361 static int xpcs_init_clks(struct dw_xpcs *xpcs) 1362 { 1363 static const char *ids[DW_XPCS_NUM_CLKS] = { 1364 [DW_XPCS_CORE_CLK] = "core", 1365 [DW_XPCS_PAD_CLK] = "pad", 1366 }; 1367 struct device *dev = &xpcs->mdiodev->dev; 1368 int ret, i; 1369 1370 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) 1371 xpcs->clks[i].id = ids[i]; 1372 1373 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); 1374 if (ret) 1375 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1376 1377 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); 1378 if (ret) 1379 return dev_err_probe(dev, ret, "Failed to enable clocks\n"); 1380 1381 return 0; 1382 } 1383 1384 static void xpcs_clear_clks(struct dw_xpcs *xpcs) 1385 { 1386 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); 1387 1388 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1389 } 1390 1391 static int xpcs_init_id(struct dw_xpcs *xpcs) 1392 { 1393 const struct dw_xpcs_info *info; 1394 1395 info = dev_get_platdata(&xpcs->mdiodev->dev); 1396 if (!info) { 1397 xpcs->info.pcs = DW_XPCS_ID_NATIVE; 1398 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; 1399 } else { 1400 xpcs->info = *info; 1401 } 1402 1403 return xpcs_identify(xpcs); 1404 } 1405 1406 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) 1407 { 1408 struct dw_xpcs *xpcs; 1409 int ret; 1410 1411 xpcs = xpcs_create_data(mdiodev); 1412 if (IS_ERR(xpcs)) 1413 return xpcs; 1414 1415 ret = xpcs_init_clks(xpcs); 1416 if (ret) 1417 goto out_free_data; 1418 1419 ret = xpcs_init_id(xpcs); 1420 if (ret) 1421 goto out_clear_clks; 1422 1423 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 1424 xpcs->pcs.poll = false; 1425 else 1426 xpcs->need_reset = true; 1427 1428 return xpcs; 1429 1430 out_clear_clks: 1431 xpcs_clear_clks(xpcs); 1432 1433 out_free_data: 1434 xpcs_free_data(xpcs); 1435 1436 return ERR_PTR(ret); 1437 } 1438 1439 /** 1440 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr 1441 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at 1442 * @addr: device MDIO-bus ID 1443 * 1444 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1445 * the PCS device couldn't be found on the bus and other negative errno related 1446 * to the data allocation and MDIO-bus communications. 1447 */ 1448 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) 1449 { 1450 struct mdio_device *mdiodev; 1451 struct dw_xpcs *xpcs; 1452 1453 mdiodev = mdio_device_create(bus, addr); 1454 if (IS_ERR(mdiodev)) 1455 return ERR_CAST(mdiodev); 1456 1457 xpcs = xpcs_create(mdiodev); 1458 1459 /* xpcs_create() has taken a refcount on the mdiodev if it was 1460 * successful. If xpcs_create() fails, this will free the mdio 1461 * device here. In any case, we don't need to hold our reference 1462 * anymore, and putting it here will allow mdio_device_put() in 1463 * xpcs_destroy() to automatically free the mdio device. 1464 */ 1465 mdio_device_put(mdiodev); 1466 1467 return xpcs; 1468 } 1469 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1470 1471 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) 1472 { 1473 struct dw_xpcs *xpcs; 1474 1475 xpcs = xpcs_create_mdiodev(bus, addr); 1476 if (IS_ERR(xpcs)) 1477 return ERR_CAST(xpcs); 1478 1479 return &xpcs->pcs; 1480 } 1481 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); 1482 1483 /** 1484 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode 1485 * @fwnode: fwnode handle poining to the DW XPCS device 1486 * 1487 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1488 * the fwnode device is unavailable or the PCS device couldn't be found on the 1489 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, 1490 * other negative errno related to the data allocations and MDIO-bus 1491 * communications. 1492 */ 1493 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) 1494 { 1495 struct mdio_device *mdiodev; 1496 struct dw_xpcs *xpcs; 1497 1498 if (!fwnode_device_is_available(fwnode)) 1499 return ERR_PTR(-ENODEV); 1500 1501 mdiodev = fwnode_mdio_find_device(fwnode); 1502 if (!mdiodev) 1503 return ERR_PTR(-EPROBE_DEFER); 1504 1505 xpcs = xpcs_create(mdiodev); 1506 1507 /* xpcs_create() has taken a refcount on the mdiodev if it was 1508 * successful. If xpcs_create() fails, this will free the mdio 1509 * device here. In any case, we don't need to hold our reference 1510 * anymore, and putting it here will allow mdio_device_put() in 1511 * xpcs_destroy() to automatically free the mdio device. 1512 */ 1513 mdio_device_put(mdiodev); 1514 1515 return xpcs; 1516 } 1517 EXPORT_SYMBOL_GPL(xpcs_create_fwnode); 1518 1519 void xpcs_destroy(struct dw_xpcs *xpcs) 1520 { 1521 if (!xpcs) 1522 return; 1523 1524 xpcs_clear_clks(xpcs); 1525 1526 xpcs_free_data(xpcs); 1527 } 1528 EXPORT_SYMBOL_GPL(xpcs_destroy); 1529 1530 void xpcs_destroy_pcs(struct phylink_pcs *pcs) 1531 { 1532 xpcs_destroy(phylink_pcs_to_xpcs(pcs)); 1533 } 1534 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); 1535 1536 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); 1537 MODULE_LICENSE("GPL v2"); 1538