1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/pcs/pcs-xpcs.h> 12 #include <linux/mdio.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 #include <linux/property.h> 16 17 #include "pcs-xpcs.h" 18 19 #define phylink_pcs_to_xpcs(pl_pcs) \ 20 container_of((pl_pcs), struct dw_xpcs, pcs) 21 22 static const int xpcs_usxgmii_features[] = { 23 ETHTOOL_LINK_MODE_Pause_BIT, 24 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 25 ETHTOOL_LINK_MODE_Autoneg_BIT, 26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 30 __ETHTOOL_LINK_MODE_MASK_NBITS, 31 }; 32 33 static const int xpcs_10gkr_features[] = { 34 ETHTOOL_LINK_MODE_Pause_BIT, 35 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 37 __ETHTOOL_LINK_MODE_MASK_NBITS, 38 }; 39 40 static const int xpcs_xlgmii_features[] = { 41 ETHTOOL_LINK_MODE_Pause_BIT, 42 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 43 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 44 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 45 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 46 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 47 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 48 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 49 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 50 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 51 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 52 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 53 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 54 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 55 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 56 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 57 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 58 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 59 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 60 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 61 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 62 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 63 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 64 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 65 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 66 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 67 __ETHTOOL_LINK_MODE_MASK_NBITS, 68 }; 69 70 static const int xpcs_10gbaser_features[] = { 71 ETHTOOL_LINK_MODE_Pause_BIT, 72 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 73 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 74 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 75 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 76 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 77 __ETHTOOL_LINK_MODE_MASK_NBITS, 78 }; 79 80 static const int xpcs_sgmii_features[] = { 81 ETHTOOL_LINK_MODE_Pause_BIT, 82 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 83 ETHTOOL_LINK_MODE_Autoneg_BIT, 84 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 85 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 86 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 87 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 88 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 89 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 90 __ETHTOOL_LINK_MODE_MASK_NBITS, 91 }; 92 93 static const int xpcs_1000basex_features[] = { 94 ETHTOOL_LINK_MODE_Pause_BIT, 95 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 96 ETHTOOL_LINK_MODE_Autoneg_BIT, 97 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 98 __ETHTOOL_LINK_MODE_MASK_NBITS, 99 }; 100 101 static const int xpcs_2500basex_features[] = { 102 ETHTOOL_LINK_MODE_Pause_BIT, 103 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 104 ETHTOOL_LINK_MODE_Autoneg_BIT, 105 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 106 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 107 __ETHTOOL_LINK_MODE_MASK_NBITS, 108 }; 109 110 struct dw_xpcs_compat { 111 phy_interface_t interface; 112 const int *supported; 113 int an_mode; 114 int (*pma_config)(struct dw_xpcs *xpcs); 115 }; 116 117 struct dw_xpcs_desc { 118 u32 id; 119 u32 mask; 120 const struct dw_xpcs_compat *compat; 121 }; 122 123 static const struct dw_xpcs_compat * 124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) 125 { 126 const struct dw_xpcs_compat *compat; 127 128 for (compat = xpcs->desc->compat; compat->supported; compat++) 129 if (compat->interface == interface) 130 return compat; 131 132 return NULL; 133 } 134 135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) 136 { 137 return &xpcs->pcs; 138 } 139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); 140 141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 142 { 143 const struct dw_xpcs_compat *compat; 144 145 compat = xpcs_find_compat(xpcs, interface); 146 if (!compat) 147 return -ENODEV; 148 149 return compat->an_mode; 150 } 151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 152 153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, 154 enum ethtool_link_mode_bit_indices linkmode) 155 { 156 int i; 157 158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 159 if (compat->supported[i] == linkmode) 160 return true; 161 162 return false; 163 } 164 165 #define xpcs_linkmode_supported(compat, mode) \ 166 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 167 168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 169 { 170 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 171 } 172 173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 174 { 175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 176 } 177 178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 179 { 180 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 181 } 182 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 184 u16 mask, u16 set) 185 { 186 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 187 } 188 189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 190 { 191 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 192 } 193 194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 195 u16 val) 196 { 197 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 198 } 199 200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 201 u16 set) 202 { 203 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 204 } 205 206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 207 { 208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 209 } 210 211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 212 { 213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 214 } 215 216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 217 { 218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 219 } 220 221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 222 { 223 int ret, val; 224 225 ret = read_poll_timeout(xpcs_read, val, 226 val < 0 || !(val & MDIO_CTRL1_RESET), 227 50000, 600000, true, xpcs, dev, MDIO_CTRL1); 228 if (val < 0) 229 ret = val; 230 231 return ret; 232 } 233 234 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 235 const struct dw_xpcs_compat *compat) 236 { 237 int ret, dev; 238 239 switch (compat->an_mode) { 240 case DW_AN_C73: 241 case DW_10GBASER: 242 dev = MDIO_MMD_PCS; 243 break; 244 case DW_AN_C37_SGMII: 245 case DW_2500BASEX: 246 case DW_AN_C37_1000BASEX: 247 dev = MDIO_MMD_VEND2; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET); 254 if (ret < 0) 255 return ret; 256 257 return xpcs_poll_reset(xpcs, dev); 258 } 259 260 #define xpcs_warn(__xpcs, __state, __args...) \ 261 ({ \ 262 if ((__state)->link) \ 263 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 264 }) 265 266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 267 struct phylink_link_state *state, 268 u16 pcs_stat1) 269 { 270 int ret; 271 272 if (pcs_stat1 & MDIO_STAT1_FAULT) { 273 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 274 return -EFAULT; 275 } 276 277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 278 if (ret < 0) 279 return ret; 280 281 if (ret & MDIO_STAT2_RXFAULT) 282 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 283 if (ret & MDIO_STAT2_TXFAULT) 284 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 285 286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 287 if (ret < 0) 288 return ret; 289 290 if (ret & DW_RXFIFO_ERR) { 291 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 292 return -EFAULT; 293 } 294 295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 296 if (ret < 0) 297 return ret; 298 299 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 300 xpcs_warn(xpcs, state, "Link is not locked!\n"); 301 302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 303 if (ret < 0) 304 return ret; 305 306 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 307 xpcs_warn(xpcs, state, "Link has errors!\n"); 308 return -EFAULT; 309 } 310 311 return 0; 312 } 313 314 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed) 315 { 316 int ret, speed_sel; 317 318 switch (speed) { 319 case SPEED_10: 320 speed_sel = DW_USXGMII_10; 321 break; 322 case SPEED_100: 323 speed_sel = DW_USXGMII_100; 324 break; 325 case SPEED_1000: 326 speed_sel = DW_USXGMII_1000; 327 break; 328 case SPEED_2500: 329 speed_sel = DW_USXGMII_2500; 330 break; 331 case SPEED_5000: 332 speed_sel = DW_USXGMII_5000; 333 break; 334 case SPEED_10000: 335 speed_sel = DW_USXGMII_10000; 336 break; 337 default: 338 /* Nothing to do here */ 339 return; 340 } 341 342 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 343 if (ret < 0) 344 goto out; 345 346 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, DW_USXGMII_SS_MASK, 347 speed_sel | DW_USXGMII_FULL); 348 if (ret < 0) 349 goto out; 350 351 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 352 DW_USXGMII_RST); 353 if (ret < 0) 354 goto out; 355 356 return; 357 358 out: 359 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", 360 __func__, ERR_PTR(ret)); 361 } 362 363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 364 const struct dw_xpcs_compat *compat) 365 { 366 int ret, adv; 367 368 /* By default, in USXGMII mode XPCS operates at 10G baud and 369 * replicates data to achieve lower speeds. Hereby, in this 370 * default configuration we need to advertise all supported 371 * modes and not only the ones we want to use. 372 */ 373 374 /* SR_AN_ADV3 */ 375 adv = 0; 376 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 377 adv |= DW_C73_2500KX; 378 379 /* TODO: 5000baseKR */ 380 381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 382 if (ret < 0) 383 return ret; 384 385 /* SR_AN_ADV2 */ 386 adv = 0; 387 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 388 adv |= DW_C73_1000KX; 389 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 390 adv |= DW_C73_10000KX4; 391 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 392 adv |= DW_C73_10000KR; 393 394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 395 if (ret < 0) 396 return ret; 397 398 /* SR_AN_ADV1 */ 399 adv = DW_C73_AN_ADV_SF; 400 if (xpcs_linkmode_supported(compat, Pause)) 401 adv |= DW_C73_PAUSE; 402 if (xpcs_linkmode_supported(compat, Asym_Pause)) 403 adv |= DW_C73_ASYM_PAUSE; 404 405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 406 } 407 408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 409 const struct dw_xpcs_compat *compat) 410 { 411 int ret; 412 413 ret = _xpcs_config_aneg_c73(xpcs, compat); 414 if (ret < 0) 415 return ret; 416 417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 418 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 419 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 420 } 421 422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 423 struct phylink_link_state *state, 424 const struct dw_xpcs_compat *compat, u16 an_stat1) 425 { 426 int ret; 427 428 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 430 if (ret < 0) 431 return ret; 432 433 /* Check if Aneg outcome is valid */ 434 if (!(ret & DW_C73_AN_ADV_SF)) { 435 xpcs_config_aneg_c73(xpcs, compat); 436 return 0; 437 } 438 439 return 1; 440 } 441 442 return 0; 443 } 444 445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 446 struct phylink_link_state *state, u16 an_stat1) 447 { 448 u16 lpa[3]; 449 int i, ret; 450 451 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 452 phylink_clear(state->lp_advertising, Autoneg); 453 return 0; 454 } 455 456 phylink_set(state->lp_advertising, Autoneg); 457 458 /* Read Clause 73 link partner advertisement */ 459 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 461 if (ret < 0) 462 return ret; 463 464 lpa[i] = ret; 465 } 466 467 mii_c73_mod_linkmode(state->lp_advertising, lpa); 468 469 return 0; 470 } 471 472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 473 struct phylink_link_state *state) 474 { 475 unsigned long *adv = state->advertising; 476 int speed = SPEED_UNKNOWN; 477 int bit; 478 479 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 480 int new_speed = SPEED_UNKNOWN; 481 482 switch (bit) { 483 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 484 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 485 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 486 new_speed = SPEED_25000; 487 break; 488 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 489 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 490 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 491 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 492 new_speed = SPEED_40000; 493 break; 494 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 495 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 496 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 497 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 498 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 499 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 500 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 501 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 502 new_speed = SPEED_50000; 503 break; 504 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 505 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 506 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 507 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 508 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 509 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 510 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 511 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 512 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 513 new_speed = SPEED_100000; 514 break; 515 default: 516 continue; 517 } 518 519 if (new_speed > speed) 520 speed = new_speed; 521 } 522 523 return speed; 524 } 525 526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs, 527 struct phylink_link_state *state) 528 { 529 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 530 state->duplex = DUPLEX_FULL; 531 532 switch (state->interface) { 533 case PHY_INTERFACE_MODE_10GKR: 534 state->speed = SPEED_10000; 535 break; 536 case PHY_INTERFACE_MODE_XLGMII: 537 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 538 break; 539 default: 540 state->speed = SPEED_UNKNOWN; 541 break; 542 } 543 } 544 545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 546 const struct phylink_link_state *state) 547 { 548 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 549 const struct dw_xpcs_compat *compat; 550 struct dw_xpcs *xpcs; 551 int i; 552 553 xpcs = phylink_pcs_to_xpcs(pcs); 554 compat = xpcs_find_compat(xpcs, state->interface); 555 if (!compat) 556 return -EINVAL; 557 558 /* Populate the supported link modes for this PHY interface type. 559 * FIXME: what about the port modes and autoneg bit? This masks 560 * all those away. 561 */ 562 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 563 set_bit(compat->supported[i], xpcs_supported); 564 565 linkmode_and(supported, supported, xpcs_supported); 566 567 return 0; 568 } 569 570 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 571 { 572 const struct dw_xpcs_compat *compat; 573 574 for (compat = xpcs->desc->compat; compat->supported; compat++) 575 __set_bit(compat->interface, interfaces); 576 } 577 EXPORT_SYMBOL_GPL(xpcs_get_interfaces); 578 579 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) 580 { 581 u16 mask, val; 582 int ret; 583 584 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 585 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 586 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 587 DW_VR_MII_EEE_MULT_FACT_100NS; 588 589 if (enable) 590 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 591 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 592 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 593 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 594 mult_fact_100ns); 595 else 596 val = 0; 597 598 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 599 val); 600 if (ret < 0) 601 return ret; 602 603 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 604 DW_VR_MII_EEE_TRN_LPI, 605 enable ? DW_VR_MII_EEE_TRN_LPI : 0); 606 } 607 EXPORT_SYMBOL_GPL(xpcs_config_eee); 608 609 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) 610 { 611 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 612 const struct dw_xpcs_compat *compat; 613 int ret; 614 615 if (!xpcs->need_reset) 616 return; 617 618 compat = xpcs_find_compat(xpcs, interface); 619 if (!compat) { 620 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", 621 phy_modes(interface)); 622 return; 623 } 624 625 ret = xpcs_soft_reset(xpcs, compat); 626 if (ret) 627 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", 628 ERR_PTR(ret)); 629 630 xpcs->need_reset = false; 631 } 632 633 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, 634 unsigned int neg_mode) 635 { 636 int ret, mdio_ctrl, tx_conf; 637 u16 mask, val; 638 639 /* For AN for C37 SGMII mode, the settings are :- 640 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 641 it is already enabled) 642 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 643 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 644 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 645 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 646 * speed/duplex mode change by HW after SGMII AN complete) 647 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 648 * 649 * Note: Since it is MAC side SGMII, there is no need to set 650 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 651 * PHY about the link state change after C28 AN is completed 652 * between PHY and Link Partner. There is also no need to 653 * trigger AN restart for MAC-side SGMII. 654 */ 655 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 656 if (mdio_ctrl < 0) 657 return mdio_ctrl; 658 659 if (mdio_ctrl & AN_CL37_EN) { 660 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 661 mdio_ctrl & ~AN_CL37_EN); 662 if (ret < 0) 663 return ret; 664 } 665 666 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 667 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 668 DW_VR_MII_PCS_MODE_C37_SGMII); 669 670 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 671 mask |= DW_VR_MII_AN_CTRL_8BIT; 672 val |= DW_VR_MII_AN_CTRL_8BIT; 673 /* Hardware requires it to be PHY side SGMII */ 674 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 675 } else { 676 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 677 } 678 679 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 680 681 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 682 if (ret < 0) 683 return ret; 684 685 mask = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 686 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 687 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 688 689 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 690 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 691 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 692 } 693 694 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 695 if (ret < 0) 696 return ret; 697 698 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 699 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 700 mdio_ctrl | AN_CL37_EN); 701 702 return ret; 703 } 704 705 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, 706 unsigned int neg_mode, 707 const unsigned long *advertising) 708 { 709 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 710 int ret, mdio_ctrl, adv; 711 bool changed = 0; 712 u16 mask, val; 713 714 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 715 * be disabled first:- 716 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 717 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 718 */ 719 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 720 if (mdio_ctrl < 0) 721 return mdio_ctrl; 722 723 if (mdio_ctrl & AN_CL37_EN) { 724 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 725 mdio_ctrl & ~AN_CL37_EN); 726 if (ret < 0) 727 return ret; 728 } 729 730 mask = DW_VR_MII_PCS_MODE_MASK; 731 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 732 DW_VR_MII_PCS_MODE_C37_1000BASEX); 733 734 if (!xpcs->pcs.poll) { 735 mask |= DW_VR_MII_AN_INTR_EN; 736 val |= DW_VR_MII_AN_INTR_EN; 737 } 738 739 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 740 if (ret < 0) 741 return ret; 742 743 /* Check for advertising changes and update the C45 MII ADV 744 * register accordingly. 745 */ 746 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 747 advertising); 748 if (adv >= 0) { 749 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 750 MII_ADVERTISE, 0xffff, adv); 751 if (ret < 0) 752 return ret; 753 754 changed = ret; 755 } 756 757 /* Clear CL37 AN complete status */ 758 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 759 if (ret < 0) 760 return ret; 761 762 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 763 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 764 mdio_ctrl | AN_CL37_EN); 765 if (ret < 0) 766 return ret; 767 } 768 769 return changed; 770 } 771 772 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 773 { 774 int ret; 775 776 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 777 DW_VR_MII_DIG_CTRL1_2G5_EN | 778 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 779 DW_VR_MII_DIG_CTRL1_2G5_EN); 780 if (ret < 0) 781 return ret; 782 783 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 784 AN_CL37_EN | SGMII_SPEED_SS6 | SGMII_SPEED_SS13, 785 SGMII_SPEED_SS6); 786 } 787 788 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 789 const unsigned long *advertising, 790 unsigned int neg_mode) 791 { 792 const struct dw_xpcs_compat *compat; 793 int ret; 794 795 compat = xpcs_find_compat(xpcs, interface); 796 if (!compat) 797 return -ENODEV; 798 799 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 800 ret = txgbe_xpcs_switch_mode(xpcs, interface); 801 if (ret) 802 return ret; 803 804 /* Wangxun devices need backplane CL37 AN enabled for 805 * SGMII and 1000base-X 806 */ 807 if (interface == PHY_INTERFACE_MODE_SGMII || 808 interface == PHY_INTERFACE_MODE_1000BASEX) 809 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, 810 DW_CL37_BP | DW_EN_VSMMD1); 811 } 812 813 switch (compat->an_mode) { 814 case DW_10GBASER: 815 break; 816 case DW_AN_C73: 817 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 818 ret = xpcs_config_aneg_c73(xpcs, compat); 819 if (ret) 820 return ret; 821 } 822 break; 823 case DW_AN_C37_SGMII: 824 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode); 825 if (ret) 826 return ret; 827 break; 828 case DW_AN_C37_1000BASEX: 829 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode, 830 advertising); 831 if (ret) 832 return ret; 833 break; 834 case DW_2500BASEX: 835 ret = xpcs_config_2500basex(xpcs); 836 if (ret) 837 return ret; 838 break; 839 default: 840 return -EINVAL; 841 } 842 843 if (compat->pma_config) { 844 ret = compat->pma_config(xpcs); 845 if (ret) 846 return ret; 847 } 848 849 return 0; 850 } 851 852 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 853 phy_interface_t interface, 854 const unsigned long *advertising, 855 bool permit_pause_to_mac) 856 { 857 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 858 859 return xpcs_do_config(xpcs, interface, advertising, neg_mode); 860 } 861 862 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 863 struct phylink_link_state *state, 864 const struct dw_xpcs_compat *compat) 865 { 866 bool an_enabled; 867 int pcs_stat1; 868 int an_stat1; 869 int ret; 870 871 /* The link status bit is latching-low, so it is important to 872 * avoid unnecessary re-reads of this register to avoid missing 873 * a link-down event. 874 */ 875 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 876 if (pcs_stat1 < 0) { 877 state->link = false; 878 return pcs_stat1; 879 } 880 881 /* Link needs to be read first ... */ 882 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 883 884 /* ... and then we check the faults. */ 885 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 886 if (ret) { 887 ret = xpcs_soft_reset(xpcs, compat); 888 if (ret) 889 return ret; 890 891 state->link = 0; 892 893 return xpcs_do_config(xpcs, state->interface, NULL, 894 PHYLINK_PCS_NEG_INBAND_ENABLED); 895 } 896 897 /* There is no point doing anything else if the link is down. */ 898 if (!state->link) 899 return 0; 900 901 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 902 state->advertising); 903 if (an_enabled) { 904 /* The link status bit is latching-low, so it is important to 905 * avoid unnecessary re-reads of this register to avoid missing 906 * a link-down event. 907 */ 908 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 909 if (an_stat1 < 0) { 910 state->link = false; 911 return an_stat1; 912 } 913 914 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 915 an_stat1); 916 if (!state->an_complete) { 917 state->link = false; 918 return 0; 919 } 920 921 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 922 if (ret < 0) { 923 state->link = false; 924 return ret; 925 } 926 927 phylink_resolve_c73(state); 928 } else { 929 xpcs_resolve_pma(xpcs, state); 930 } 931 932 return 0; 933 } 934 935 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 936 struct phylink_link_state *state) 937 { 938 int ret; 939 940 /* Reset link_state */ 941 state->link = false; 942 state->speed = SPEED_UNKNOWN; 943 state->duplex = DUPLEX_UNKNOWN; 944 state->pause = 0; 945 946 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 947 * status, speed and duplex. 948 */ 949 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 950 if (ret < 0) 951 return ret; 952 953 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 954 int speed_value; 955 956 state->link = true; 957 958 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 959 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 960 state->speed = SPEED_1000; 961 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 962 state->speed = SPEED_100; 963 else 964 state->speed = SPEED_10; 965 966 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 967 state->duplex = DUPLEX_FULL; 968 else 969 state->duplex = DUPLEX_HALF; 970 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 971 int speed, duplex; 972 973 state->link = true; 974 975 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 976 if (speed < 0) 977 return speed; 978 979 speed &= SGMII_SPEED_SS13 | SGMII_SPEED_SS6; 980 if (speed == SGMII_SPEED_SS6) 981 state->speed = SPEED_1000; 982 else if (speed == SGMII_SPEED_SS13) 983 state->speed = SPEED_100; 984 else if (speed == 0) 985 state->speed = SPEED_10; 986 987 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE); 988 if (duplex < 0) 989 return duplex; 990 991 if (duplex & DW_FULL_DUPLEX) 992 state->duplex = DUPLEX_FULL; 993 else if (duplex & DW_HALF_DUPLEX) 994 state->duplex = DUPLEX_HALF; 995 996 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 997 } 998 999 return 0; 1000 } 1001 1002 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 1003 struct phylink_link_state *state) 1004 { 1005 int lpa, bmsr; 1006 1007 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1008 state->advertising)) { 1009 /* Reset link state */ 1010 state->link = false; 1011 1012 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 1013 if (lpa < 0 || lpa & LPA_RFAULT) 1014 return lpa; 1015 1016 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1017 if (bmsr < 0) 1018 return bmsr; 1019 1020 /* Clear AN complete interrupt */ 1021 if (!xpcs->pcs.poll) { 1022 int an_intr; 1023 1024 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1025 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1026 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1027 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr); 1028 } 1029 } 1030 1031 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa); 1032 } 1033 1034 return 0; 1035 } 1036 1037 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, 1038 struct phylink_link_state *state) 1039 { 1040 int ret; 1041 1042 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_STS); 1043 if (ret < 0) { 1044 state->link = 0; 1045 return ret; 1046 } 1047 1048 state->link = !!(ret & DW_VR_MII_MMD_STS_LINK_STS); 1049 if (!state->link) 1050 return 0; 1051 1052 state->speed = SPEED_2500; 1053 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 1054 state->duplex = DUPLEX_FULL; 1055 1056 return 0; 1057 } 1058 1059 static void xpcs_get_state(struct phylink_pcs *pcs, 1060 struct phylink_link_state *state) 1061 { 1062 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1063 const struct dw_xpcs_compat *compat; 1064 int ret; 1065 1066 compat = xpcs_find_compat(xpcs, state->interface); 1067 if (!compat) 1068 return; 1069 1070 switch (compat->an_mode) { 1071 case DW_10GBASER: 1072 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1073 break; 1074 case DW_AN_C73: 1075 ret = xpcs_get_state_c73(xpcs, state, compat); 1076 if (ret) 1077 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1078 "xpcs_get_state_c73", ERR_PTR(ret)); 1079 break; 1080 case DW_AN_C37_SGMII: 1081 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1082 if (ret) 1083 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1084 "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); 1085 break; 1086 case DW_AN_C37_1000BASEX: 1087 ret = xpcs_get_state_c37_1000basex(xpcs, state); 1088 if (ret) 1089 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1090 "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); 1091 break; 1092 case DW_2500BASEX: 1093 ret = xpcs_get_state_2500basex(xpcs, state); 1094 if (ret) 1095 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1096 "xpcs_get_state_2500basex", ERR_PTR(ret)); 1097 break; 1098 default: 1099 return; 1100 } 1101 } 1102 1103 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode, 1104 int speed, int duplex) 1105 { 1106 int val, ret; 1107 1108 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1109 return; 1110 1111 val = mii_bmcr_encode_fixed(speed, duplex); 1112 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); 1113 if (ret) 1114 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1115 __func__, ERR_PTR(ret)); 1116 } 1117 1118 static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode, 1119 int speed, int duplex) 1120 { 1121 int val, ret; 1122 1123 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1124 return; 1125 1126 switch (speed) { 1127 case SPEED_1000: 1128 val = BMCR_SPEED1000; 1129 break; 1130 case SPEED_100: 1131 case SPEED_10: 1132 default: 1133 dev_err(&xpcs->mdiodev->dev, "%s: speed = %d\n", 1134 __func__, speed); 1135 return; 1136 } 1137 1138 if (duplex == DUPLEX_FULL) 1139 val |= BMCR_FULLDPLX; 1140 else 1141 dev_err(&xpcs->mdiodev->dev, "%s: half duplex not supported\n", 1142 __func__); 1143 1144 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); 1145 if (ret) 1146 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1147 __func__, ERR_PTR(ret)); 1148 } 1149 1150 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 1151 phy_interface_t interface, int speed, int duplex) 1152 { 1153 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1154 1155 if (interface == PHY_INTERFACE_MODE_USXGMII) 1156 return xpcs_config_usxgmii(xpcs, speed); 1157 if (interface == PHY_INTERFACE_MODE_SGMII) 1158 return xpcs_link_up_sgmii(xpcs, neg_mode, speed, duplex); 1159 if (interface == PHY_INTERFACE_MODE_1000BASEX) 1160 return xpcs_link_up_1000basex(xpcs, neg_mode, speed, duplex); 1161 } 1162 1163 static void xpcs_an_restart(struct phylink_pcs *pcs) 1164 { 1165 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1166 1167 xpcs_modify(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, BMCR_ANRESTART, 1168 BMCR_ANRESTART); 1169 } 1170 1171 static int xpcs_read_ids(struct dw_xpcs *xpcs) 1172 { 1173 int ret; 1174 u32 id; 1175 1176 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication 1177 * failed indicating that device couldn't be reached. 1178 */ 1179 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1180 if (ret < 0) 1181 return -ENODEV; 1182 1183 id = ret << 16; 1184 1185 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1186 if (ret < 0) 1187 return ret; 1188 1189 id |= ret; 1190 1191 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 1192 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 1193 * PCS in MII MMD 31. 1194 */ 1195 if (!id || id == 0xffffffff) { 1196 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1197 if (ret < 0) 1198 return ret; 1199 1200 id = ret << 16; 1201 1202 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1203 if (ret < 0) 1204 return ret; 1205 1206 id |= ret; 1207 } 1208 1209 /* Set the PCS ID if it hasn't been pre-initialized */ 1210 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) 1211 xpcs->info.pcs = id; 1212 1213 /* Find out PMA/PMD ID from MMD 1 device ID registers */ 1214 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); 1215 if (ret < 0) 1216 return ret; 1217 1218 id = ret; 1219 1220 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); 1221 if (ret < 0) 1222 return ret; 1223 1224 /* Note the inverted dword order and masked out Model/Revision numbers 1225 * with respect to what is done with the PCS ID... 1226 */ 1227 ret = (ret >> 10) & 0x3F; 1228 id |= ret << 16; 1229 1230 /* Set the PMA ID if it hasn't been pre-initialized */ 1231 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) 1232 xpcs->info.pma = id; 1233 1234 return 0; 1235 } 1236 1237 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { 1238 { 1239 .interface = PHY_INTERFACE_MODE_USXGMII, 1240 .supported = xpcs_usxgmii_features, 1241 .an_mode = DW_AN_C73, 1242 }, { 1243 .interface = PHY_INTERFACE_MODE_10GKR, 1244 .supported = xpcs_10gkr_features, 1245 .an_mode = DW_AN_C73, 1246 }, { 1247 .interface = PHY_INTERFACE_MODE_XLGMII, 1248 .supported = xpcs_xlgmii_features, 1249 .an_mode = DW_AN_C73, 1250 }, { 1251 .interface = PHY_INTERFACE_MODE_10GBASER, 1252 .supported = xpcs_10gbaser_features, 1253 .an_mode = DW_10GBASER, 1254 }, { 1255 .interface = PHY_INTERFACE_MODE_SGMII, 1256 .supported = xpcs_sgmii_features, 1257 .an_mode = DW_AN_C37_SGMII, 1258 }, { 1259 .interface = PHY_INTERFACE_MODE_1000BASEX, 1260 .supported = xpcs_1000basex_features, 1261 .an_mode = DW_AN_C37_1000BASEX, 1262 }, { 1263 .interface = PHY_INTERFACE_MODE_2500BASEX, 1264 .supported = xpcs_2500basex_features, 1265 .an_mode = DW_2500BASEX, 1266 }, { 1267 } 1268 }; 1269 1270 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { 1271 { 1272 .interface = PHY_INTERFACE_MODE_SGMII, 1273 .supported = xpcs_sgmii_features, 1274 .an_mode = DW_AN_C37_SGMII, 1275 .pma_config = nxp_sja1105_sgmii_pma_config, 1276 }, { 1277 } 1278 }; 1279 1280 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { 1281 { 1282 .interface = PHY_INTERFACE_MODE_SGMII, 1283 .supported = xpcs_sgmii_features, 1284 .an_mode = DW_AN_C37_SGMII, 1285 .pma_config = nxp_sja1110_sgmii_pma_config, 1286 }, { 1287 .interface = PHY_INTERFACE_MODE_2500BASEX, 1288 .supported = xpcs_2500basex_features, 1289 .an_mode = DW_2500BASEX, 1290 .pma_config = nxp_sja1110_2500basex_pma_config, 1291 }, { 1292 } 1293 }; 1294 1295 static const struct dw_xpcs_desc xpcs_desc_list[] = { 1296 { 1297 .id = DW_XPCS_ID, 1298 .mask = DW_XPCS_ID_MASK, 1299 .compat = synopsys_xpcs_compat, 1300 }, { 1301 .id = NXP_SJA1105_XPCS_ID, 1302 .mask = DW_XPCS_ID_MASK, 1303 .compat = nxp_sja1105_xpcs_compat, 1304 }, { 1305 .id = NXP_SJA1110_XPCS_ID, 1306 .mask = DW_XPCS_ID_MASK, 1307 .compat = nxp_sja1110_xpcs_compat, 1308 }, 1309 }; 1310 1311 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1312 .pcs_validate = xpcs_validate, 1313 .pcs_pre_config = xpcs_pre_config, 1314 .pcs_config = xpcs_config, 1315 .pcs_get_state = xpcs_get_state, 1316 .pcs_an_restart = xpcs_an_restart, 1317 .pcs_link_up = xpcs_link_up, 1318 }; 1319 1320 static int xpcs_identify(struct dw_xpcs *xpcs) 1321 { 1322 int i, ret; 1323 1324 ret = xpcs_read_ids(xpcs); 1325 if (ret < 0) 1326 return ret; 1327 1328 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { 1329 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; 1330 1331 if ((xpcs->info.pcs & entry->mask) == entry->id) { 1332 xpcs->desc = entry; 1333 return 0; 1334 } 1335 } 1336 1337 return -ENODEV; 1338 } 1339 1340 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) 1341 { 1342 struct dw_xpcs *xpcs; 1343 1344 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); 1345 if (!xpcs) 1346 return ERR_PTR(-ENOMEM); 1347 1348 mdio_device_get(mdiodev); 1349 xpcs->mdiodev = mdiodev; 1350 xpcs->pcs.ops = &xpcs_phylink_ops; 1351 xpcs->pcs.neg_mode = true; 1352 xpcs->pcs.poll = true; 1353 1354 return xpcs; 1355 } 1356 1357 static void xpcs_free_data(struct dw_xpcs *xpcs) 1358 { 1359 mdio_device_put(xpcs->mdiodev); 1360 kfree(xpcs); 1361 } 1362 1363 static int xpcs_init_clks(struct dw_xpcs *xpcs) 1364 { 1365 static const char *ids[DW_XPCS_NUM_CLKS] = { 1366 [DW_XPCS_CORE_CLK] = "core", 1367 [DW_XPCS_PAD_CLK] = "pad", 1368 }; 1369 struct device *dev = &xpcs->mdiodev->dev; 1370 int ret, i; 1371 1372 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) 1373 xpcs->clks[i].id = ids[i]; 1374 1375 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); 1376 if (ret) 1377 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1378 1379 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); 1380 if (ret) 1381 return dev_err_probe(dev, ret, "Failed to enable clocks\n"); 1382 1383 return 0; 1384 } 1385 1386 static void xpcs_clear_clks(struct dw_xpcs *xpcs) 1387 { 1388 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); 1389 1390 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1391 } 1392 1393 static int xpcs_init_id(struct dw_xpcs *xpcs) 1394 { 1395 const struct dw_xpcs_info *info; 1396 1397 info = dev_get_platdata(&xpcs->mdiodev->dev); 1398 if (!info) { 1399 xpcs->info.pcs = DW_XPCS_ID_NATIVE; 1400 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; 1401 } else { 1402 xpcs->info = *info; 1403 } 1404 1405 return xpcs_identify(xpcs); 1406 } 1407 1408 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) 1409 { 1410 struct dw_xpcs *xpcs; 1411 int ret; 1412 1413 xpcs = xpcs_create_data(mdiodev); 1414 if (IS_ERR(xpcs)) 1415 return xpcs; 1416 1417 ret = xpcs_init_clks(xpcs); 1418 if (ret) 1419 goto out_free_data; 1420 1421 ret = xpcs_init_id(xpcs); 1422 if (ret) 1423 goto out_clear_clks; 1424 1425 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 1426 xpcs->pcs.poll = false; 1427 else 1428 xpcs->need_reset = true; 1429 1430 return xpcs; 1431 1432 out_clear_clks: 1433 xpcs_clear_clks(xpcs); 1434 1435 out_free_data: 1436 xpcs_free_data(xpcs); 1437 1438 return ERR_PTR(ret); 1439 } 1440 1441 /** 1442 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr 1443 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at 1444 * @addr: device MDIO-bus ID 1445 * 1446 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1447 * the PCS device couldn't be found on the bus and other negative errno related 1448 * to the data allocation and MDIO-bus communications. 1449 */ 1450 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) 1451 { 1452 struct mdio_device *mdiodev; 1453 struct dw_xpcs *xpcs; 1454 1455 mdiodev = mdio_device_create(bus, addr); 1456 if (IS_ERR(mdiodev)) 1457 return ERR_CAST(mdiodev); 1458 1459 xpcs = xpcs_create(mdiodev); 1460 1461 /* xpcs_create() has taken a refcount on the mdiodev if it was 1462 * successful. If xpcs_create() fails, this will free the mdio 1463 * device here. In any case, we don't need to hold our reference 1464 * anymore, and putting it here will allow mdio_device_put() in 1465 * xpcs_destroy() to automatically free the mdio device. 1466 */ 1467 mdio_device_put(mdiodev); 1468 1469 return xpcs; 1470 } 1471 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1472 1473 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) 1474 { 1475 struct dw_xpcs *xpcs; 1476 1477 xpcs = xpcs_create_mdiodev(bus, addr); 1478 if (IS_ERR(xpcs)) 1479 return ERR_CAST(xpcs); 1480 1481 return &xpcs->pcs; 1482 } 1483 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); 1484 1485 /** 1486 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode 1487 * @fwnode: fwnode handle poining to the DW XPCS device 1488 * 1489 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1490 * the fwnode device is unavailable or the PCS device couldn't be found on the 1491 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, 1492 * other negative errno related to the data allocations and MDIO-bus 1493 * communications. 1494 */ 1495 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) 1496 { 1497 struct mdio_device *mdiodev; 1498 struct dw_xpcs *xpcs; 1499 1500 if (!fwnode_device_is_available(fwnode)) 1501 return ERR_PTR(-ENODEV); 1502 1503 mdiodev = fwnode_mdio_find_device(fwnode); 1504 if (!mdiodev) 1505 return ERR_PTR(-EPROBE_DEFER); 1506 1507 xpcs = xpcs_create(mdiodev); 1508 1509 /* xpcs_create() has taken a refcount on the mdiodev if it was 1510 * successful. If xpcs_create() fails, this will free the mdio 1511 * device here. In any case, we don't need to hold our reference 1512 * anymore, and putting it here will allow mdio_device_put() in 1513 * xpcs_destroy() to automatically free the mdio device. 1514 */ 1515 mdio_device_put(mdiodev); 1516 1517 return xpcs; 1518 } 1519 EXPORT_SYMBOL_GPL(xpcs_create_fwnode); 1520 1521 void xpcs_destroy(struct dw_xpcs *xpcs) 1522 { 1523 if (!xpcs) 1524 return; 1525 1526 xpcs_clear_clks(xpcs); 1527 1528 xpcs_free_data(xpcs); 1529 } 1530 EXPORT_SYMBOL_GPL(xpcs_destroy); 1531 1532 void xpcs_destroy_pcs(struct phylink_pcs *pcs) 1533 { 1534 xpcs_destroy(phylink_pcs_to_xpcs(pcs)); 1535 } 1536 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); 1537 1538 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); 1539 MODULE_LICENSE("GPL v2"); 1540