1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare XPCS helpers 5 * 6 * Author: Jose Abreu <Jose.Abreu@synopsys.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/pcs/pcs-xpcs.h> 12 #include <linux/mdio.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 #include <linux/property.h> 16 17 #include "pcs-xpcs.h" 18 19 #define phylink_pcs_to_xpcs(pl_pcs) \ 20 container_of((pl_pcs), struct dw_xpcs, pcs) 21 22 static const int xpcs_usxgmii_features[] = { 23 ETHTOOL_LINK_MODE_Pause_BIT, 24 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 25 ETHTOOL_LINK_MODE_Autoneg_BIT, 26 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 27 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 28 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 30 __ETHTOOL_LINK_MODE_MASK_NBITS, 31 }; 32 33 static const int xpcs_10gkr_features[] = { 34 ETHTOOL_LINK_MODE_Pause_BIT, 35 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 36 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 37 __ETHTOOL_LINK_MODE_MASK_NBITS, 38 }; 39 40 static const int xpcs_xlgmii_features[] = { 41 ETHTOOL_LINK_MODE_Pause_BIT, 42 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 43 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 44 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 45 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 46 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 47 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 48 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 49 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 50 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 51 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 52 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 53 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 54 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 55 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 56 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 57 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, 58 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 59 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 60 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 61 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 62 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 63 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 64 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 65 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 66 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, 67 __ETHTOOL_LINK_MODE_MASK_NBITS, 68 }; 69 70 static const int xpcs_10gbaser_features[] = { 71 ETHTOOL_LINK_MODE_Pause_BIT, 72 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 73 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 74 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 75 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 76 ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 77 __ETHTOOL_LINK_MODE_MASK_NBITS, 78 }; 79 80 static const int xpcs_sgmii_features[] = { 81 ETHTOOL_LINK_MODE_Pause_BIT, 82 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 83 ETHTOOL_LINK_MODE_Autoneg_BIT, 84 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 85 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 86 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 87 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 88 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 89 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 90 __ETHTOOL_LINK_MODE_MASK_NBITS, 91 }; 92 93 static const int xpcs_1000basex_features[] = { 94 ETHTOOL_LINK_MODE_Pause_BIT, 95 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 96 ETHTOOL_LINK_MODE_Autoneg_BIT, 97 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 98 __ETHTOOL_LINK_MODE_MASK_NBITS, 99 }; 100 101 static const int xpcs_2500basex_features[] = { 102 ETHTOOL_LINK_MODE_Pause_BIT, 103 ETHTOOL_LINK_MODE_Asym_Pause_BIT, 104 ETHTOOL_LINK_MODE_Autoneg_BIT, 105 ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 106 ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 107 __ETHTOOL_LINK_MODE_MASK_NBITS, 108 }; 109 110 struct dw_xpcs_compat { 111 phy_interface_t interface; 112 const int *supported; 113 int an_mode; 114 int (*pma_config)(struct dw_xpcs *xpcs); 115 }; 116 117 struct dw_xpcs_desc { 118 u32 id; 119 u32 mask; 120 const struct dw_xpcs_compat *compat; 121 }; 122 123 static const struct dw_xpcs_compat * 124 xpcs_find_compat(struct dw_xpcs *xpcs, phy_interface_t interface) 125 { 126 const struct dw_xpcs_compat *compat; 127 128 for (compat = xpcs->desc->compat; compat->supported; compat++) 129 if (compat->interface == interface) 130 return compat; 131 132 return NULL; 133 } 134 135 struct phylink_pcs *xpcs_to_phylink_pcs(struct dw_xpcs *xpcs) 136 { 137 return &xpcs->pcs; 138 } 139 EXPORT_SYMBOL_GPL(xpcs_to_phylink_pcs); 140 141 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 142 { 143 const struct dw_xpcs_compat *compat; 144 145 compat = xpcs_find_compat(xpcs, interface); 146 if (!compat) 147 return -ENODEV; 148 149 return compat->an_mode; 150 } 151 EXPORT_SYMBOL_GPL(xpcs_get_an_mode); 152 153 static bool __xpcs_linkmode_supported(const struct dw_xpcs_compat *compat, 154 enum ethtool_link_mode_bit_indices linkmode) 155 { 156 int i; 157 158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 159 if (compat->supported[i] == linkmode) 160 return true; 161 162 return false; 163 } 164 165 #define xpcs_linkmode_supported(compat, mode) \ 166 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) 167 168 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) 169 { 170 return mdiodev_c45_read(xpcs->mdiodev, dev, reg); 171 } 172 173 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) 174 { 175 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val); 176 } 177 178 int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) 179 { 180 return mdiodev_c45_modify(xpcs->mdiodev, dev, reg, mask, set); 181 } 182 183 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, 184 u16 mask, u16 set) 185 { 186 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); 187 } 188 189 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) 190 { 191 return xpcs_read(xpcs, dev, DW_VENDOR | reg); 192 } 193 194 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, 195 u16 val) 196 { 197 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); 198 } 199 200 static int xpcs_modify_vendor(struct dw_xpcs *xpcs, int dev, int reg, u16 mask, 201 u16 set) 202 { 203 return xpcs_modify(xpcs, dev, DW_VENDOR | reg, mask, set); 204 } 205 206 int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) 207 { 208 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 209 } 210 211 int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) 212 { 213 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 214 } 215 216 static int xpcs_modify_vpcs(struct dw_xpcs *xpcs, int reg, u16 mask, u16 val) 217 { 218 return xpcs_modify_vendor(xpcs, MDIO_MMD_PCS, reg, mask, val); 219 } 220 221 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) 222 { 223 int ret, val; 224 225 ret = read_poll_timeout(xpcs_read, val, 226 val < 0 || !(val & BMCR_RESET), 227 50000, 600000, true, xpcs, dev, MII_BMCR); 228 if (val < 0) 229 ret = val; 230 231 return ret; 232 } 233 234 static int xpcs_soft_reset(struct dw_xpcs *xpcs, 235 const struct dw_xpcs_compat *compat) 236 { 237 int ret, dev; 238 239 switch (compat->an_mode) { 240 case DW_AN_C73: 241 case DW_10GBASER: 242 dev = MDIO_MMD_PCS; 243 break; 244 case DW_AN_C37_SGMII: 245 case DW_2500BASEX: 246 case DW_AN_C37_1000BASEX: 247 dev = MDIO_MMD_VEND2; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 ret = xpcs_write(xpcs, dev, MII_BMCR, BMCR_RESET); 254 if (ret < 0) 255 return ret; 256 257 return xpcs_poll_reset(xpcs, dev); 258 } 259 260 #define xpcs_warn(__xpcs, __state, __args...) \ 261 ({ \ 262 if ((__state)->link) \ 263 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ 264 }) 265 266 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, 267 struct phylink_link_state *state, 268 u16 pcs_stat1) 269 { 270 int ret; 271 272 if (pcs_stat1 & MDIO_STAT1_FAULT) { 273 xpcs_warn(xpcs, state, "Link fault condition detected!\n"); 274 return -EFAULT; 275 } 276 277 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 278 if (ret < 0) 279 return ret; 280 281 if (ret & MDIO_STAT2_RXFAULT) 282 xpcs_warn(xpcs, state, "Receiver fault detected!\n"); 283 if (ret & MDIO_STAT2_TXFAULT) 284 xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); 285 286 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 287 if (ret < 0) 288 return ret; 289 290 if (ret & DW_RXFIFO_ERR) { 291 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); 292 return -EFAULT; 293 } 294 295 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 296 if (ret < 0) 297 return ret; 298 299 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) 300 xpcs_warn(xpcs, state, "Link is not locked!\n"); 301 302 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 303 if (ret < 0) 304 return ret; 305 306 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { 307 xpcs_warn(xpcs, state, "Link has errors!\n"); 308 return -EFAULT; 309 } 310 311 return 0; 312 } 313 314 static void xpcs_link_up_usxgmii(struct dw_xpcs *xpcs, int speed) 315 { 316 int ret, speed_sel; 317 318 switch (speed) { 319 case SPEED_10: 320 speed_sel = DW_USXGMII_10; 321 break; 322 case SPEED_100: 323 speed_sel = DW_USXGMII_100; 324 break; 325 case SPEED_1000: 326 speed_sel = DW_USXGMII_1000; 327 break; 328 case SPEED_2500: 329 speed_sel = DW_USXGMII_2500; 330 break; 331 case SPEED_5000: 332 speed_sel = DW_USXGMII_5000; 333 break; 334 case SPEED_10000: 335 speed_sel = DW_USXGMII_10000; 336 break; 337 default: 338 /* Nothing to do here */ 339 return; 340 } 341 342 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_EN, DW_USXGMII_EN); 343 if (ret < 0) 344 goto out; 345 346 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, DW_USXGMII_SS_MASK, 347 speed_sel | DW_USXGMII_FULL); 348 if (ret < 0) 349 goto out; 350 351 ret = xpcs_modify_vpcs(xpcs, MDIO_CTRL1, DW_USXGMII_RST, 352 DW_USXGMII_RST); 353 if (ret < 0) 354 goto out; 355 356 return; 357 358 out: 359 dev_err(&xpcs->mdiodev->dev, "%s: XPCS access returned %pe\n", 360 __func__, ERR_PTR(ret)); 361 } 362 363 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 364 const struct dw_xpcs_compat *compat) 365 { 366 int ret, adv; 367 368 /* By default, in USXGMII mode XPCS operates at 10G baud and 369 * replicates data to achieve lower speeds. Hereby, in this 370 * default configuration we need to advertise all supported 371 * modes and not only the ones we want to use. 372 */ 373 374 /* SR_AN_ADV3 */ 375 adv = 0; 376 if (xpcs_linkmode_supported(compat, 2500baseX_Full)) 377 adv |= DW_C73_2500KX; 378 379 /* TODO: 5000baseKR */ 380 381 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); 382 if (ret < 0) 383 return ret; 384 385 /* SR_AN_ADV2 */ 386 adv = 0; 387 if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) 388 adv |= DW_C73_1000KX; 389 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) 390 adv |= DW_C73_10000KX4; 391 if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) 392 adv |= DW_C73_10000KR; 393 394 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); 395 if (ret < 0) 396 return ret; 397 398 /* SR_AN_ADV1 */ 399 adv = DW_C73_AN_ADV_SF; 400 if (xpcs_linkmode_supported(compat, Pause)) 401 adv |= DW_C73_PAUSE; 402 if (xpcs_linkmode_supported(compat, Asym_Pause)) 403 adv |= DW_C73_ASYM_PAUSE; 404 405 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); 406 } 407 408 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, 409 const struct dw_xpcs_compat *compat) 410 { 411 int ret; 412 413 ret = _xpcs_config_aneg_c73(xpcs, compat); 414 if (ret < 0) 415 return ret; 416 417 return xpcs_modify(xpcs, MDIO_MMD_AN, MDIO_CTRL1, 418 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART, 419 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 420 } 421 422 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, 423 struct phylink_link_state *state, 424 const struct dw_xpcs_compat *compat, u16 an_stat1) 425 { 426 int ret; 427 428 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) { 429 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); 430 if (ret < 0) 431 return ret; 432 433 /* Check if Aneg outcome is valid */ 434 if (!(ret & DW_C73_AN_ADV_SF)) { 435 xpcs_config_aneg_c73(xpcs, compat); 436 return 0; 437 } 438 439 return 1; 440 } 441 442 return 0; 443 } 444 445 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, 446 struct phylink_link_state *state, u16 an_stat1) 447 { 448 u16 lpa[3]; 449 int i, ret; 450 451 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) { 452 phylink_clear(state->lp_advertising, Autoneg); 453 return 0; 454 } 455 456 phylink_set(state->lp_advertising, Autoneg); 457 458 /* Read Clause 73 link partner advertisement */ 459 for (i = ARRAY_SIZE(lpa); --i >= 0; ) { 460 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); 461 if (ret < 0) 462 return ret; 463 464 lpa[i] = ret; 465 } 466 467 mii_c73_mod_linkmode(state->lp_advertising, lpa); 468 469 return 0; 470 } 471 472 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, 473 struct phylink_link_state *state) 474 { 475 unsigned long *adv = state->advertising; 476 int speed = SPEED_UNKNOWN; 477 int bit; 478 479 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { 480 int new_speed = SPEED_UNKNOWN; 481 482 switch (bit) { 483 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 484 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 485 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 486 new_speed = SPEED_25000; 487 break; 488 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 489 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 490 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 491 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 492 new_speed = SPEED_40000; 493 break; 494 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: 495 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: 496 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: 497 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 498 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 499 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 500 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 501 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: 502 new_speed = SPEED_50000; 503 break; 504 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 505 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 506 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 507 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 508 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: 509 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: 510 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: 511 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: 512 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: 513 new_speed = SPEED_100000; 514 break; 515 default: 516 continue; 517 } 518 519 if (new_speed > speed) 520 speed = new_speed; 521 } 522 523 return speed; 524 } 525 526 static void xpcs_resolve_pma(struct dw_xpcs *xpcs, 527 struct phylink_link_state *state) 528 { 529 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; 530 state->duplex = DUPLEX_FULL; 531 532 switch (state->interface) { 533 case PHY_INTERFACE_MODE_10GKR: 534 state->speed = SPEED_10000; 535 break; 536 case PHY_INTERFACE_MODE_XLGMII: 537 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); 538 break; 539 default: 540 state->speed = SPEED_UNKNOWN; 541 break; 542 } 543 } 544 545 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported, 546 const struct phylink_link_state *state) 547 { 548 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, }; 549 const struct dw_xpcs_compat *compat; 550 struct dw_xpcs *xpcs; 551 int i; 552 553 xpcs = phylink_pcs_to_xpcs(pcs); 554 compat = xpcs_find_compat(xpcs, state->interface); 555 if (!compat) 556 return -EINVAL; 557 558 /* Populate the supported link modes for this PHY interface type. 559 * FIXME: what about the port modes and autoneg bit? This masks 560 * all those away. 561 */ 562 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) 563 set_bit(compat->supported[i], xpcs_supported); 564 565 linkmode_and(supported, supported, xpcs_supported); 566 567 return 0; 568 } 569 570 static unsigned int xpcs_inband_caps(struct phylink_pcs *pcs, 571 phy_interface_t interface) 572 { 573 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 574 const struct dw_xpcs_compat *compat; 575 576 compat = xpcs_find_compat(xpcs, interface); 577 if (!compat) 578 return 0; 579 580 switch (compat->an_mode) { 581 case DW_AN_C73: 582 return LINK_INBAND_ENABLE; 583 584 case DW_AN_C37_SGMII: 585 case DW_AN_C37_1000BASEX: 586 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 587 588 case DW_10GBASER: 589 case DW_2500BASEX: 590 return LINK_INBAND_DISABLE; 591 592 default: 593 return 0; 594 } 595 } 596 597 static void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces) 598 { 599 const struct dw_xpcs_compat *compat; 600 601 for (compat = xpcs->desc->compat; compat->supported; compat++) 602 __set_bit(compat->interface, interfaces); 603 } 604 605 static void xpcs_pre_config(struct phylink_pcs *pcs, phy_interface_t interface) 606 { 607 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 608 const struct dw_xpcs_compat *compat; 609 int ret; 610 611 if (!xpcs->need_reset) 612 return; 613 614 compat = xpcs_find_compat(xpcs, interface); 615 if (!compat) { 616 dev_err(&xpcs->mdiodev->dev, "unsupported interface %s\n", 617 phy_modes(interface)); 618 return; 619 } 620 621 ret = xpcs_soft_reset(xpcs, compat); 622 if (ret) 623 dev_err(&xpcs->mdiodev->dev, "soft reset failed: %pe\n", 624 ERR_PTR(ret)); 625 626 xpcs->need_reset = false; 627 } 628 629 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, 630 unsigned int neg_mode) 631 { 632 int ret, mdio_ctrl, tx_conf; 633 u16 mask, val; 634 635 /* For AN for C37 SGMII mode, the settings are :- 636 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case 637 it is already enabled) 638 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) 639 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) 640 * DW xPCS used with DW EQoS MAC is always MAC side SGMII. 641 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic 642 * speed/duplex mode change by HW after SGMII AN complete) 643 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) 644 * 645 * Note that VR_MII_MMD_CTRL is MII_BMCR. 646 * 647 * Note: Since it is MAC side SGMII, there is no need to set 648 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from 649 * PHY about the link state change after C28 AN is completed 650 * between PHY and Link Partner. There is also no need to 651 * trigger AN restart for MAC-side SGMII. 652 */ 653 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 654 if (mdio_ctrl < 0) 655 return mdio_ctrl; 656 657 if (mdio_ctrl & BMCR_ANENABLE) { 658 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 659 mdio_ctrl & ~BMCR_ANENABLE); 660 if (ret < 0) 661 return ret; 662 } 663 664 mask = DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK; 665 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 666 DW_VR_MII_PCS_MODE_C37_SGMII); 667 668 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 669 mask |= DW_VR_MII_AN_CTRL_8BIT; 670 val |= DW_VR_MII_AN_CTRL_8BIT; 671 /* Hardware requires it to be PHY side SGMII */ 672 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; 673 } else { 674 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII; 675 } 676 677 val |= FIELD_PREP(DW_VR_MII_TX_CONFIG_MASK, tx_conf); 678 679 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 680 if (ret < 0) 681 return ret; 682 683 val = 0; 684 mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 685 686 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 687 val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; 688 689 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 690 mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 691 val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL; 692 } 693 694 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, mask, val); 695 if (ret < 0) 696 return ret; 697 698 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 699 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 700 mdio_ctrl | BMCR_ANENABLE); 701 702 return ret; 703 } 704 705 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, 706 unsigned int neg_mode, 707 const unsigned long *advertising) 708 { 709 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX; 710 int ret, mdio_ctrl, adv; 711 bool changed = 0; 712 u16 mask, val; 713 714 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must 715 * be disabled first:- 716 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b 717 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37) 718 * 719 * Note that VR_MII_MMD_CTRL is MII_BMCR. 720 */ 721 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 722 if (mdio_ctrl < 0) 723 return mdio_ctrl; 724 725 if (mdio_ctrl & BMCR_ANENABLE) { 726 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 727 mdio_ctrl & ~BMCR_ANENABLE); 728 if (ret < 0) 729 return ret; 730 } 731 732 mask = DW_VR_MII_PCS_MODE_MASK; 733 val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, 734 DW_VR_MII_PCS_MODE_C37_1000BASEX); 735 736 if (!xpcs->pcs.poll) { 737 mask |= DW_VR_MII_AN_INTR_EN; 738 val |= DW_VR_MII_AN_INTR_EN; 739 } 740 741 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, mask, val); 742 if (ret < 0) 743 return ret; 744 745 /* Check for advertising changes and update the C45 MII ADV 746 * register accordingly. 747 */ 748 adv = phylink_mii_c22_pcs_encode_advertisement(interface, 749 advertising); 750 if (adv >= 0) { 751 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, 752 MII_ADVERTISE, 0xffff, adv); 753 if (ret < 0) 754 return ret; 755 756 changed = ret; 757 } 758 759 /* Clear CL37 AN complete status */ 760 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 761 if (ret < 0) 762 return ret; 763 764 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 765 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 766 mdio_ctrl | BMCR_ANENABLE); 767 if (ret < 0) 768 return ret; 769 } 770 771 return changed; 772 } 773 774 static int xpcs_config_2500basex(struct dw_xpcs *xpcs) 775 { 776 int ret; 777 778 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 779 DW_VR_MII_DIG_CTRL1_2G5_EN | 780 DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW, 781 DW_VR_MII_DIG_CTRL1_2G5_EN); 782 if (ret < 0) 783 return ret; 784 785 return xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, 786 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_SPEED100, 787 BMCR_SPEED1000); 788 } 789 790 static int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, 791 const unsigned long *advertising, 792 unsigned int neg_mode) 793 { 794 const struct dw_xpcs_compat *compat; 795 int ret; 796 797 compat = xpcs_find_compat(xpcs, interface); 798 if (!compat) 799 return -ENODEV; 800 801 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { 802 ret = txgbe_xpcs_switch_mode(xpcs, interface); 803 if (ret) 804 return ret; 805 806 /* Wangxun devices need backplane CL37 AN enabled for 807 * SGMII and 1000base-X 808 */ 809 if (interface == PHY_INTERFACE_MODE_SGMII || 810 interface == PHY_INTERFACE_MODE_1000BASEX) 811 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, 812 DW_CL37_BP | DW_EN_VSMMD1); 813 } 814 815 switch (compat->an_mode) { 816 case DW_10GBASER: 817 break; 818 case DW_AN_C73: 819 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 820 ret = xpcs_config_aneg_c73(xpcs, compat); 821 if (ret) 822 return ret; 823 } 824 break; 825 case DW_AN_C37_SGMII: 826 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode); 827 if (ret) 828 return ret; 829 break; 830 case DW_AN_C37_1000BASEX: 831 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode, 832 advertising); 833 if (ret) 834 return ret; 835 break; 836 case DW_2500BASEX: 837 ret = xpcs_config_2500basex(xpcs); 838 if (ret) 839 return ret; 840 break; 841 default: 842 return -EINVAL; 843 } 844 845 if (compat->pma_config) { 846 ret = compat->pma_config(xpcs); 847 if (ret) 848 return ret; 849 } 850 851 return 0; 852 } 853 854 static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 855 phy_interface_t interface, 856 const unsigned long *advertising, 857 bool permit_pause_to_mac) 858 { 859 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 860 861 return xpcs_do_config(xpcs, interface, advertising, neg_mode); 862 } 863 864 static int xpcs_get_state_c73(struct dw_xpcs *xpcs, 865 struct phylink_link_state *state, 866 const struct dw_xpcs_compat *compat) 867 { 868 bool an_enabled; 869 int pcs_stat1; 870 int an_stat1; 871 int ret; 872 873 /* The link status bit is latching-low, so it is important to 874 * avoid unnecessary re-reads of this register to avoid missing 875 * a link-down event. 876 */ 877 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 878 if (pcs_stat1 < 0) { 879 state->link = false; 880 return pcs_stat1; 881 } 882 883 /* Link needs to be read first ... */ 884 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS); 885 886 /* ... and then we check the faults. */ 887 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1); 888 if (ret) { 889 ret = xpcs_soft_reset(xpcs, compat); 890 if (ret) 891 return ret; 892 893 state->link = 0; 894 895 return xpcs_do_config(xpcs, state->interface, NULL, 896 PHYLINK_PCS_NEG_INBAND_ENABLED); 897 } 898 899 /* There is no point doing anything else if the link is down. */ 900 if (!state->link) 901 return 0; 902 903 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 904 state->advertising); 905 if (an_enabled) { 906 /* The link status bit is latching-low, so it is important to 907 * avoid unnecessary re-reads of this register to avoid missing 908 * a link-down event. 909 */ 910 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); 911 if (an_stat1 < 0) { 912 state->link = false; 913 return an_stat1; 914 } 915 916 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat, 917 an_stat1); 918 if (!state->an_complete) { 919 state->link = false; 920 return 0; 921 } 922 923 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1); 924 if (ret < 0) { 925 state->link = false; 926 return ret; 927 } 928 929 phylink_resolve_c73(state); 930 } else { 931 xpcs_resolve_pma(xpcs, state); 932 } 933 934 return 0; 935 } 936 937 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, 938 struct phylink_link_state *state) 939 { 940 int ret; 941 942 /* Reset link_state */ 943 state->link = false; 944 state->speed = SPEED_UNKNOWN; 945 state->duplex = DUPLEX_UNKNOWN; 946 state->pause = 0; 947 948 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link 949 * status, speed and duplex. 950 */ 951 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 952 if (ret < 0) 953 return ret; 954 955 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { 956 int speed_value; 957 958 state->link = true; 959 960 speed_value = FIELD_GET(DW_VR_MII_AN_STS_C37_ANSGM_SP, ret); 961 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) 962 state->speed = SPEED_1000; 963 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) 964 state->speed = SPEED_100; 965 else 966 state->speed = SPEED_10; 967 968 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) 969 state->duplex = DUPLEX_FULL; 970 else 971 state->duplex = DUPLEX_HALF; 972 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 973 int speed, duplex; 974 975 state->link = true; 976 977 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR); 978 if (speed < 0) 979 return speed; 980 981 speed &= BMCR_SPEED100 | BMCR_SPEED1000; 982 if (speed == BMCR_SPEED1000) 983 state->speed = SPEED_1000; 984 else if (speed == BMCR_SPEED100) 985 state->speed = SPEED_100; 986 else if (speed == 0) 987 state->speed = SPEED_10; 988 989 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE); 990 if (duplex < 0) 991 return duplex; 992 993 if (duplex & ADVERTISE_1000XFULL) 994 state->duplex = DUPLEX_FULL; 995 else if (duplex & ADVERTISE_1000XHALF) 996 state->duplex = DUPLEX_HALF; 997 998 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0); 999 } 1000 1001 return 0; 1002 } 1003 1004 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs, 1005 unsigned int neg_mode, 1006 struct phylink_link_state *state) 1007 { 1008 int lpa, bmsr; 1009 1010 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 1011 state->advertising)) { 1012 /* Reset link state */ 1013 state->link = false; 1014 1015 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); 1016 if (lpa < 0 || lpa & LPA_RFAULT) 1017 return lpa; 1018 1019 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1020 if (bmsr < 0) 1021 return bmsr; 1022 1023 /* Clear AN complete interrupt */ 1024 if (!xpcs->pcs.poll) { 1025 int an_intr; 1026 1027 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); 1028 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) { 1029 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR; 1030 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr); 1031 } 1032 } 1033 1034 phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr, lpa); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs, 1041 struct phylink_link_state *state) 1042 { 1043 int ret; 1044 1045 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); 1046 if (ret < 0) { 1047 state->link = 0; 1048 return ret; 1049 } 1050 1051 state->link = !!(ret & BMSR_LSTATUS); 1052 if (!state->link) 1053 return 0; 1054 1055 state->speed = SPEED_2500; 1056 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX; 1057 state->duplex = DUPLEX_FULL; 1058 1059 return 0; 1060 } 1061 1062 static void xpcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 1063 struct phylink_link_state *state) 1064 { 1065 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1066 const struct dw_xpcs_compat *compat; 1067 int ret; 1068 1069 compat = xpcs_find_compat(xpcs, state->interface); 1070 if (!compat) 1071 return; 1072 1073 switch (compat->an_mode) { 1074 case DW_10GBASER: 1075 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state); 1076 break; 1077 case DW_AN_C73: 1078 ret = xpcs_get_state_c73(xpcs, state, compat); 1079 if (ret) 1080 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1081 "xpcs_get_state_c73", ERR_PTR(ret)); 1082 break; 1083 case DW_AN_C37_SGMII: 1084 ret = xpcs_get_state_c37_sgmii(xpcs, state); 1085 if (ret) 1086 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1087 "xpcs_get_state_c37_sgmii", ERR_PTR(ret)); 1088 break; 1089 case DW_AN_C37_1000BASEX: 1090 ret = xpcs_get_state_c37_1000basex(xpcs, neg_mode, state); 1091 if (ret) 1092 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1093 "xpcs_get_state_c37_1000basex", ERR_PTR(ret)); 1094 break; 1095 case DW_2500BASEX: 1096 ret = xpcs_get_state_2500basex(xpcs, state); 1097 if (ret) 1098 dev_err(&xpcs->mdiodev->dev, "%s returned %pe\n", 1099 "xpcs_get_state_2500basex", ERR_PTR(ret)); 1100 break; 1101 default: 1102 return; 1103 } 1104 } 1105 1106 static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs, 1107 unsigned int neg_mode, 1108 phy_interface_t interface, 1109 int speed, int duplex) 1110 { 1111 int ret; 1112 1113 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) 1114 return; 1115 1116 if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1117 if (speed != SPEED_1000) { 1118 dev_err(&xpcs->mdiodev->dev, 1119 "%s: speed %dMbps not supported\n", 1120 __func__, speed); 1121 return; 1122 } 1123 1124 if (duplex != DUPLEX_FULL) 1125 dev_err(&xpcs->mdiodev->dev, 1126 "%s: half duplex not supported\n", 1127 __func__); 1128 } 1129 1130 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR, 1131 mii_bmcr_encode_fixed(speed, duplex)); 1132 if (ret) 1133 dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n", 1134 __func__, ERR_PTR(ret)); 1135 } 1136 1137 static void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 1138 phy_interface_t interface, int speed, int duplex) 1139 { 1140 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1141 1142 switch (interface) { 1143 case PHY_INTERFACE_MODE_USXGMII: 1144 xpcs_link_up_usxgmii(xpcs, speed); 1145 break; 1146 1147 case PHY_INTERFACE_MODE_SGMII: 1148 case PHY_INTERFACE_MODE_1000BASEX: 1149 xpcs_link_up_sgmii_1000basex(xpcs, neg_mode, interface, speed, 1150 duplex); 1151 break; 1152 1153 default: 1154 break; 1155 } 1156 } 1157 1158 static void xpcs_an_restart(struct phylink_pcs *pcs) 1159 { 1160 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1161 1162 xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR, BMCR_ANRESTART, 1163 BMCR_ANRESTART); 1164 } 1165 1166 static int xpcs_config_eee(struct dw_xpcs *xpcs, bool enable) 1167 { 1168 u16 mask, val; 1169 int ret; 1170 1171 mask = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 1172 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 1173 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 1174 DW_VR_MII_EEE_MULT_FACT_100NS; 1175 1176 if (enable) 1177 val = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | 1178 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | 1179 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | 1180 FIELD_PREP(DW_VR_MII_EEE_MULT_FACT_100NS, 1181 xpcs->eee_mult_fact); 1182 else 1183 val = 0; 1184 1185 ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, mask, 1186 val); 1187 if (ret < 0) 1188 return ret; 1189 1190 return xpcs_modify(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, 1191 DW_VR_MII_EEE_TRN_LPI, 1192 enable ? DW_VR_MII_EEE_TRN_LPI : 0); 1193 } 1194 1195 static void xpcs_disable_eee(struct phylink_pcs *pcs) 1196 { 1197 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1198 1199 xpcs_config_eee(xpcs, false); 1200 } 1201 1202 static void xpcs_enable_eee(struct phylink_pcs *pcs) 1203 { 1204 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); 1205 1206 xpcs_config_eee(xpcs, true); 1207 } 1208 1209 /** 1210 * xpcs_config_eee_mult_fact() - set the EEE clock multiplying factor 1211 * @xpcs: pointer to a &struct dw_xpcs instance 1212 * @mult_fact: the multiplying factor 1213 * 1214 * Configure the EEE clock multiplying factor. This value should be such that 1215 * clk_eee_time_period * (mult_fact + 1) is within the range 80 to 120ns. 1216 */ 1217 void xpcs_config_eee_mult_fact(struct dw_xpcs *xpcs, u8 mult_fact) 1218 { 1219 xpcs->eee_mult_fact = mult_fact; 1220 } 1221 EXPORT_SYMBOL_GPL(xpcs_config_eee_mult_fact); 1222 1223 static int xpcs_read_ids(struct dw_xpcs *xpcs) 1224 { 1225 int ret; 1226 u32 id; 1227 1228 /* First, search C73 PCS using PCS MMD 3. Return ENODEV if communication 1229 * failed indicating that device couldn't be reached. 1230 */ 1231 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1232 if (ret < 0) 1233 return -ENODEV; 1234 1235 id = ret << 16; 1236 1237 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); 1238 if (ret < 0) 1239 return ret; 1240 1241 id |= ret; 1242 1243 /* If Device IDs are not all zeros or ones, then 10GBase-X/R or C73 1244 * KR/KX4 PCS found. Otherwise fallback to detecting 1000Base-X or C37 1245 * PCS in MII MMD 31. 1246 */ 1247 if (!id || id == 0xffffffff) { 1248 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); 1249 if (ret < 0) 1250 return ret; 1251 1252 id = ret << 16; 1253 1254 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); 1255 if (ret < 0) 1256 return ret; 1257 1258 id |= ret; 1259 } 1260 1261 /* Set the PCS ID if it hasn't been pre-initialized */ 1262 if (xpcs->info.pcs == DW_XPCS_ID_NATIVE) 1263 xpcs->info.pcs = id; 1264 1265 /* Find out PMA/PMD ID from MMD 1 device ID registers */ 1266 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1); 1267 if (ret < 0) 1268 return ret; 1269 1270 id = ret; 1271 1272 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2); 1273 if (ret < 0) 1274 return ret; 1275 1276 /* Note the inverted dword order and masked out Model/Revision numbers 1277 * with respect to what is done with the PCS ID... 1278 */ 1279 ret = (ret >> 10) & 0x3F; 1280 id |= ret << 16; 1281 1282 /* Set the PMA ID if it hasn't been pre-initialized */ 1283 if (xpcs->info.pma == DW_XPCS_PMA_ID_NATIVE) 1284 xpcs->info.pma = id; 1285 1286 return 0; 1287 } 1288 1289 static const struct dw_xpcs_compat synopsys_xpcs_compat[] = { 1290 { 1291 .interface = PHY_INTERFACE_MODE_USXGMII, 1292 .supported = xpcs_usxgmii_features, 1293 .an_mode = DW_AN_C73, 1294 }, { 1295 .interface = PHY_INTERFACE_MODE_10GKR, 1296 .supported = xpcs_10gkr_features, 1297 .an_mode = DW_AN_C73, 1298 }, { 1299 .interface = PHY_INTERFACE_MODE_XLGMII, 1300 .supported = xpcs_xlgmii_features, 1301 .an_mode = DW_AN_C73, 1302 }, { 1303 .interface = PHY_INTERFACE_MODE_10GBASER, 1304 .supported = xpcs_10gbaser_features, 1305 .an_mode = DW_10GBASER, 1306 }, { 1307 .interface = PHY_INTERFACE_MODE_SGMII, 1308 .supported = xpcs_sgmii_features, 1309 .an_mode = DW_AN_C37_SGMII, 1310 }, { 1311 .interface = PHY_INTERFACE_MODE_1000BASEX, 1312 .supported = xpcs_1000basex_features, 1313 .an_mode = DW_AN_C37_1000BASEX, 1314 }, { 1315 .interface = PHY_INTERFACE_MODE_2500BASEX, 1316 .supported = xpcs_2500basex_features, 1317 .an_mode = DW_2500BASEX, 1318 }, { 1319 } 1320 }; 1321 1322 static const struct dw_xpcs_compat nxp_sja1105_xpcs_compat[] = { 1323 { 1324 .interface = PHY_INTERFACE_MODE_SGMII, 1325 .supported = xpcs_sgmii_features, 1326 .an_mode = DW_AN_C37_SGMII, 1327 .pma_config = nxp_sja1105_sgmii_pma_config, 1328 }, { 1329 } 1330 }; 1331 1332 static const struct dw_xpcs_compat nxp_sja1110_xpcs_compat[] = { 1333 { 1334 .interface = PHY_INTERFACE_MODE_SGMII, 1335 .supported = xpcs_sgmii_features, 1336 .an_mode = DW_AN_C37_SGMII, 1337 .pma_config = nxp_sja1110_sgmii_pma_config, 1338 }, { 1339 .interface = PHY_INTERFACE_MODE_2500BASEX, 1340 .supported = xpcs_2500basex_features, 1341 .an_mode = DW_2500BASEX, 1342 .pma_config = nxp_sja1110_2500basex_pma_config, 1343 }, { 1344 } 1345 }; 1346 1347 static const struct dw_xpcs_desc xpcs_desc_list[] = { 1348 { 1349 .id = DW_XPCS_ID, 1350 .mask = DW_XPCS_ID_MASK, 1351 .compat = synopsys_xpcs_compat, 1352 }, { 1353 .id = NXP_SJA1105_XPCS_ID, 1354 .mask = DW_XPCS_ID_MASK, 1355 .compat = nxp_sja1105_xpcs_compat, 1356 }, { 1357 .id = NXP_SJA1110_XPCS_ID, 1358 .mask = DW_XPCS_ID_MASK, 1359 .compat = nxp_sja1110_xpcs_compat, 1360 }, 1361 }; 1362 1363 static const struct phylink_pcs_ops xpcs_phylink_ops = { 1364 .pcs_validate = xpcs_validate, 1365 .pcs_inband_caps = xpcs_inband_caps, 1366 .pcs_pre_config = xpcs_pre_config, 1367 .pcs_config = xpcs_config, 1368 .pcs_get_state = xpcs_get_state, 1369 .pcs_an_restart = xpcs_an_restart, 1370 .pcs_link_up = xpcs_link_up, 1371 .pcs_disable_eee = xpcs_disable_eee, 1372 .pcs_enable_eee = xpcs_enable_eee, 1373 }; 1374 1375 static int xpcs_identify(struct dw_xpcs *xpcs) 1376 { 1377 int i, ret; 1378 1379 ret = xpcs_read_ids(xpcs); 1380 if (ret < 0) 1381 return ret; 1382 1383 for (i = 0; i < ARRAY_SIZE(xpcs_desc_list); i++) { 1384 const struct dw_xpcs_desc *entry = &xpcs_desc_list[i]; 1385 1386 if ((xpcs->info.pcs & entry->mask) == entry->id) { 1387 xpcs->desc = entry; 1388 return 0; 1389 } 1390 } 1391 1392 return -ENODEV; 1393 } 1394 1395 static struct dw_xpcs *xpcs_create_data(struct mdio_device *mdiodev) 1396 { 1397 struct dw_xpcs *xpcs; 1398 1399 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); 1400 if (!xpcs) 1401 return ERR_PTR(-ENOMEM); 1402 1403 mdio_device_get(mdiodev); 1404 xpcs->mdiodev = mdiodev; 1405 xpcs->pcs.ops = &xpcs_phylink_ops; 1406 xpcs->pcs.poll = true; 1407 1408 return xpcs; 1409 } 1410 1411 static void xpcs_free_data(struct dw_xpcs *xpcs) 1412 { 1413 mdio_device_put(xpcs->mdiodev); 1414 kfree(xpcs); 1415 } 1416 1417 static int xpcs_init_clks(struct dw_xpcs *xpcs) 1418 { 1419 static const char *ids[DW_XPCS_NUM_CLKS] = { 1420 [DW_XPCS_CORE_CLK] = "core", 1421 [DW_XPCS_PAD_CLK] = "pad", 1422 }; 1423 struct device *dev = &xpcs->mdiodev->dev; 1424 int ret, i; 1425 1426 for (i = 0; i < DW_XPCS_NUM_CLKS; ++i) 1427 xpcs->clks[i].id = ids[i]; 1428 1429 ret = clk_bulk_get_optional(dev, DW_XPCS_NUM_CLKS, xpcs->clks); 1430 if (ret) 1431 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1432 1433 ret = clk_bulk_prepare_enable(DW_XPCS_NUM_CLKS, xpcs->clks); 1434 if (ret) 1435 return dev_err_probe(dev, ret, "Failed to enable clocks\n"); 1436 1437 return 0; 1438 } 1439 1440 static void xpcs_clear_clks(struct dw_xpcs *xpcs) 1441 { 1442 clk_bulk_disable_unprepare(DW_XPCS_NUM_CLKS, xpcs->clks); 1443 1444 clk_bulk_put(DW_XPCS_NUM_CLKS, xpcs->clks); 1445 } 1446 1447 static int xpcs_init_id(struct dw_xpcs *xpcs) 1448 { 1449 const struct dw_xpcs_info *info; 1450 1451 info = dev_get_platdata(&xpcs->mdiodev->dev); 1452 if (!info) { 1453 xpcs->info.pcs = DW_XPCS_ID_NATIVE; 1454 xpcs->info.pma = DW_XPCS_PMA_ID_NATIVE; 1455 } else { 1456 xpcs->info = *info; 1457 } 1458 1459 return xpcs_identify(xpcs); 1460 } 1461 1462 static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) 1463 { 1464 struct dw_xpcs *xpcs; 1465 int ret; 1466 1467 xpcs = xpcs_create_data(mdiodev); 1468 if (IS_ERR(xpcs)) 1469 return xpcs; 1470 1471 ret = xpcs_init_clks(xpcs); 1472 if (ret) 1473 goto out_free_data; 1474 1475 ret = xpcs_init_id(xpcs); 1476 if (ret) 1477 goto out_clear_clks; 1478 1479 xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); 1480 1481 if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) 1482 xpcs->pcs.poll = false; 1483 else 1484 xpcs->need_reset = true; 1485 1486 return xpcs; 1487 1488 out_clear_clks: 1489 xpcs_clear_clks(xpcs); 1490 1491 out_free_data: 1492 xpcs_free_data(xpcs); 1493 1494 return ERR_PTR(ret); 1495 } 1496 1497 /** 1498 * xpcs_create_mdiodev() - create a DW xPCS instance with the MDIO @addr 1499 * @bus: pointer to the MDIO-bus descriptor for the device to be looked at 1500 * @addr: device MDIO-bus ID 1501 * 1502 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1503 * the PCS device couldn't be found on the bus and other negative errno related 1504 * to the data allocation and MDIO-bus communications. 1505 */ 1506 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr) 1507 { 1508 struct mdio_device *mdiodev; 1509 struct dw_xpcs *xpcs; 1510 1511 mdiodev = mdio_device_create(bus, addr); 1512 if (IS_ERR(mdiodev)) 1513 return ERR_CAST(mdiodev); 1514 1515 xpcs = xpcs_create(mdiodev); 1516 1517 /* xpcs_create() has taken a refcount on the mdiodev if it was 1518 * successful. If xpcs_create() fails, this will free the mdio 1519 * device here. In any case, we don't need to hold our reference 1520 * anymore, and putting it here will allow mdio_device_put() in 1521 * xpcs_destroy() to automatically free the mdio device. 1522 */ 1523 mdio_device_put(mdiodev); 1524 1525 return xpcs; 1526 } 1527 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev); 1528 1529 struct phylink_pcs *xpcs_create_pcs_mdiodev(struct mii_bus *bus, int addr) 1530 { 1531 struct dw_xpcs *xpcs; 1532 1533 xpcs = xpcs_create_mdiodev(bus, addr); 1534 if (IS_ERR(xpcs)) 1535 return ERR_CAST(xpcs); 1536 1537 return &xpcs->pcs; 1538 } 1539 EXPORT_SYMBOL_GPL(xpcs_create_pcs_mdiodev); 1540 1541 /** 1542 * xpcs_create_fwnode() - Create a DW xPCS instance from @fwnode 1543 * @fwnode: fwnode handle poining to the DW XPCS device 1544 * 1545 * Return: a pointer to the DW XPCS handle if successful, otherwise -ENODEV if 1546 * the fwnode device is unavailable or the PCS device couldn't be found on the 1547 * bus, -EPROBE_DEFER if the respective MDIO-device instance couldn't be found, 1548 * other negative errno related to the data allocations and MDIO-bus 1549 * communications. 1550 */ 1551 struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode) 1552 { 1553 struct mdio_device *mdiodev; 1554 struct dw_xpcs *xpcs; 1555 1556 if (!fwnode_device_is_available(fwnode)) 1557 return ERR_PTR(-ENODEV); 1558 1559 mdiodev = fwnode_mdio_find_device(fwnode); 1560 if (!mdiodev) 1561 return ERR_PTR(-EPROBE_DEFER); 1562 1563 xpcs = xpcs_create(mdiodev); 1564 1565 /* xpcs_create() has taken a refcount on the mdiodev if it was 1566 * successful. If xpcs_create() fails, this will free the mdio 1567 * device here. In any case, we don't need to hold our reference 1568 * anymore, and putting it here will allow mdio_device_put() in 1569 * xpcs_destroy() to automatically free the mdio device. 1570 */ 1571 mdio_device_put(mdiodev); 1572 1573 return xpcs; 1574 } 1575 EXPORT_SYMBOL_GPL(xpcs_create_fwnode); 1576 1577 void xpcs_destroy(struct dw_xpcs *xpcs) 1578 { 1579 if (!xpcs) 1580 return; 1581 1582 xpcs_clear_clks(xpcs); 1583 1584 xpcs_free_data(xpcs); 1585 } 1586 EXPORT_SYMBOL_GPL(xpcs_destroy); 1587 1588 void xpcs_destroy_pcs(struct phylink_pcs *pcs) 1589 { 1590 xpcs_destroy(phylink_pcs_to_xpcs(pcs)); 1591 } 1592 EXPORT_SYMBOL_GPL(xpcs_destroy_pcs); 1593 1594 MODULE_DESCRIPTION("Synopsys DesignWare XPCS library"); 1595 MODULE_LICENSE("GPL v2"); 1596