1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bits.h> 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/device/devres.h> 14 #include <linux/mdio.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/pcs-rzn1-miic.h> 18 #include <linux/phylink.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <dt-bindings/net/pcs-rzn1-miic.h> 24 25 #define MIIC_PRCMD 0x0 26 #define MIIC_ESID_CODE 0x4 27 28 #define MIIC_MODCTRL 0x8 29 30 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 31 32 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 33 #define CONV_MODE_10MBPS 0 34 #define CONV_MODE_100MBPS 1 35 #define CONV_MODE_1000MBPS 2 36 37 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 38 #define CONV_MODE_MII 0 39 #define CONV_MODE_RMII 1 40 #define CONV_MODE_RGMII 2 41 42 #define MIIC_CONVCTRL_FULLD BIT(8) 43 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 44 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 45 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 46 47 #define MIIC_CONVRST 0x114 48 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 49 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 50 51 #define MIIC_SWCTRL 0x304 52 #define MIIC_SWDUPC 0x308 53 54 #define MIIC_MODCTRL_CONF_CONV_MAX 6 55 #define MIIC_MODCTRL_CONF_NONE -1 56 57 #define MIIC_MAX_NUM_RSTS 2 58 59 /** 60 * struct modctrl_match - Matching table entry for convctrl configuration 61 * See section 8.2.1 of manual. 62 * @mode_cfg: Configuration value for convctrl 63 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 64 * then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case 65 * of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then 66 * index 0 - 3 are CONV0 - CONV3. 67 */ 68 struct modctrl_match { 69 u32 mode_cfg; 70 u8 conv[MIIC_MODCTRL_CONF_CONV_MAX]; 71 }; 72 73 static struct modctrl_match modctrl_match_table[] = { 74 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 75 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 76 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 77 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 78 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 79 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 80 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 81 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 82 83 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 84 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 85 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 86 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 87 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 88 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 89 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 90 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 91 92 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 93 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 94 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 95 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 96 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 97 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 98 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 99 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 100 }; 101 102 static const char * const conf_to_string[] = { 103 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 104 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 105 [MIIC_RTOS_PORT] = "RTOS_PORT", 106 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 107 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 108 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 109 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 110 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 111 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 112 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 113 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 114 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 115 [MIIC_HSR_PORTA] = "HSR_PORTA", 116 [MIIC_HSR_PORTB] = "HSR_PORTB", 117 }; 118 119 static const char * const index_to_string[] = { 120 "SWITCH_PORTIN", 121 "CONV1", 122 "CONV2", 123 "CONV3", 124 "CONV4", 125 "CONV5", 126 }; 127 128 /** 129 * struct miic - MII converter structure 130 * @base: base address of the MII converter 131 * @dev: Device associated to the MII converter 132 * @lock: Lock used for read-modify-write access 133 * @rsts: Reset controls for the MII converter 134 * @of_data: Pointer to OF data 135 */ 136 struct miic { 137 void __iomem *base; 138 struct device *dev; 139 spinlock_t lock; 140 struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; 141 const struct miic_of_data *of_data; 142 }; 143 144 /** 145 * struct miic_of_data - OF data for MII converter 146 * @match_table: Matching table for convctrl configuration 147 * @match_table_count: Number of entries in the matching table 148 * @conf_conv_count: Number of entries in the conf_conv array 149 * @conf_to_string: String representations of the configuration values 150 * @conf_to_string_count: Number of entries in the conf_to_string array 151 * @index_to_string: String representations of the index values 152 * @index_to_string_count: Number of entries in the index_to_string array 153 * @miic_port_start: MIIC port start number 154 * @miic_port_max: Maximum MIIC supported 155 * @sw_mode_mask: Switch mode mask 156 * @reset_ids: Reset names array 157 * @reset_count: Number of entries in the reset_ids array 158 */ 159 struct miic_of_data { 160 struct modctrl_match *match_table; 161 u8 match_table_count; 162 u8 conf_conv_count; 163 const char * const *conf_to_string; 164 u8 conf_to_string_count; 165 const char * const *index_to_string; 166 u8 index_to_string_count; 167 u8 miic_port_start; 168 u8 miic_port_max; 169 u8 sw_mode_mask; 170 const char * const *reset_ids; 171 u8 reset_count; 172 }; 173 174 /** 175 * struct miic_port - Per port MII converter struct 176 * @miic: backiling to MII converter structure 177 * @pcs: PCS structure associated to the port 178 * @port: port number 179 * @interface: interface mode of the port 180 */ 181 struct miic_port { 182 struct miic *miic; 183 struct phylink_pcs pcs; 184 int port; 185 phy_interface_t interface; 186 }; 187 188 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 189 { 190 return container_of(pcs, struct miic_port, pcs); 191 } 192 193 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 194 { 195 writel(value, miic->base + offset); 196 } 197 198 static u32 miic_reg_readl(struct miic *miic, int offset) 199 { 200 return readl(miic->base + offset); 201 } 202 203 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 204 { 205 u32 reg; 206 207 spin_lock(&miic->lock); 208 209 reg = miic_reg_readl(miic, offset); 210 reg &= ~mask; 211 reg |= val; 212 miic_reg_writel(miic, offset, reg); 213 214 spin_unlock(&miic->lock); 215 } 216 217 static void miic_converter_enable(struct miic *miic, int port, int enable) 218 { 219 u32 val = 0; 220 221 if (enable) 222 val = MIIC_CONVRST_PHYIF_RST(port); 223 224 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 225 } 226 227 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, 228 phy_interface_t interface, 229 const unsigned long *advertising, bool permit) 230 { 231 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 232 struct miic *miic = miic_port->miic; 233 u32 speed, conv_mode, val, mask; 234 int port = miic_port->port; 235 236 switch (interface) { 237 case PHY_INTERFACE_MODE_RMII: 238 conv_mode = CONV_MODE_RMII; 239 speed = CONV_MODE_100MBPS; 240 break; 241 case PHY_INTERFACE_MODE_RGMII: 242 case PHY_INTERFACE_MODE_RGMII_ID: 243 case PHY_INTERFACE_MODE_RGMII_TXID: 244 case PHY_INTERFACE_MODE_RGMII_RXID: 245 conv_mode = CONV_MODE_RGMII; 246 speed = CONV_MODE_1000MBPS; 247 break; 248 case PHY_INTERFACE_MODE_MII: 249 conv_mode = CONV_MODE_MII; 250 /* When in MII mode, speed should be set to 0 (which is actually 251 * CONV_MODE_10MBPS) 252 */ 253 speed = CONV_MODE_10MBPS; 254 break; 255 default: 256 return -EOPNOTSUPP; 257 } 258 259 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 260 mask = MIIC_CONVCTRL_CONV_MODE; 261 262 /* Update speed only if we are going to change the interface because 263 * the link might already be up and it would break it if the speed is 264 * changed. 265 */ 266 if (interface != miic_port->interface) { 267 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 268 mask |= MIIC_CONVCTRL_CONV_SPEED; 269 miic_port->interface = interface; 270 } 271 272 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 273 miic_converter_enable(miic, miic_port->port, 1); 274 275 return 0; 276 } 277 278 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 279 phy_interface_t interface, int speed, int duplex) 280 { 281 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 282 struct miic *miic = miic_port->miic; 283 u32 conv_speed = 0, val = 0; 284 int port = miic_port->port; 285 286 if (duplex == DUPLEX_FULL) 287 val |= MIIC_CONVCTRL_FULLD; 288 289 /* No speed in MII through-mode */ 290 if (interface != PHY_INTERFACE_MODE_MII) { 291 switch (speed) { 292 case SPEED_1000: 293 conv_speed = CONV_MODE_1000MBPS; 294 break; 295 case SPEED_100: 296 conv_speed = CONV_MODE_100MBPS; 297 break; 298 case SPEED_10: 299 conv_speed = CONV_MODE_10MBPS; 300 break; 301 default: 302 return; 303 } 304 } 305 306 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 307 308 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 309 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 310 } 311 312 static int miic_pre_init(struct phylink_pcs *pcs) 313 { 314 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 315 struct miic *miic = miic_port->miic; 316 u32 val, mask; 317 318 /* Start RX clock if required */ 319 if (pcs->rxc_always_on) { 320 /* In MII through mode, the clock signals will be driven by the 321 * external PHY, which might not be initialized yet. Set RMII 322 * as default mode to ensure that a reference clock signal is 323 * generated. 324 */ 325 miic_port->interface = PHY_INTERFACE_MODE_RMII; 326 327 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | 328 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); 329 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; 330 331 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); 332 333 miic_converter_enable(miic, miic_port->port, 1); 334 } 335 336 return 0; 337 } 338 339 static const struct phylink_pcs_ops miic_phylink_ops = { 340 .pcs_config = miic_config, 341 .pcs_link_up = miic_link_up, 342 .pcs_pre_init = miic_pre_init, 343 }; 344 345 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 346 { 347 const struct miic_of_data *of_data; 348 struct platform_device *pdev; 349 struct miic_port *miic_port; 350 struct device_node *pcs_np; 351 struct miic *miic; 352 u32 port; 353 354 if (!of_device_is_available(np)) 355 return ERR_PTR(-ENODEV); 356 357 if (of_property_read_u32(np, "reg", &port)) 358 return ERR_PTR(-EINVAL); 359 360 /* The PCS pdev is attached to the parent node */ 361 pcs_np = of_get_parent(np); 362 if (!pcs_np) 363 return ERR_PTR(-ENODEV); 364 365 if (!of_device_is_available(pcs_np)) { 366 of_node_put(pcs_np); 367 return ERR_PTR(-ENODEV); 368 } 369 370 pdev = of_find_device_by_node(pcs_np); 371 of_node_put(pcs_np); 372 if (!pdev || !platform_get_drvdata(pdev)) { 373 if (pdev) 374 put_device(&pdev->dev); 375 return ERR_PTR(-EPROBE_DEFER); 376 } 377 378 miic = platform_get_drvdata(pdev); 379 of_data = miic->of_data; 380 if (port > of_data->miic_port_max || port < of_data->miic_port_start) { 381 put_device(&pdev->dev); 382 return ERR_PTR(-EINVAL); 383 } 384 385 miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL); 386 if (!miic_port) { 387 put_device(&pdev->dev); 388 return ERR_PTR(-ENOMEM); 389 } 390 391 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 392 put_device(&pdev->dev); 393 394 miic_port->miic = miic; 395 miic_port->port = port - of_data->miic_port_start; 396 miic_port->pcs.ops = &miic_phylink_ops; 397 398 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); 399 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces); 400 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces); 401 402 return &miic_port->pcs; 403 } 404 EXPORT_SYMBOL(miic_create); 405 406 void miic_destroy(struct phylink_pcs *pcs) 407 { 408 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 409 410 miic_converter_enable(miic_port->miic, miic_port->port, 0); 411 kfree(miic_port); 412 } 413 EXPORT_SYMBOL(miic_destroy); 414 415 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 416 { 417 u8 sw_mode_mask = miic->of_data->sw_mode_mask; 418 int port; 419 420 /* Unlock write access to accessory registers (cf datasheet). If this 421 * is going to be used in conjunction with the Cortex-M3, this sequence 422 * will have to be moved in register write 423 */ 424 miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); 425 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 426 miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); 427 miic_reg_writel(miic, MIIC_PRCMD, 0x0001); 428 429 /* TODO: Replace with FIELD_PREP() when compile-time constant 430 * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask. 431 */ 432 miic_reg_writel(miic, MIIC_MODCTRL, 433 ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); 434 435 for (port = 0; port < miic->of_data->miic_port_max; port++) { 436 miic_converter_enable(miic, port, 0); 437 /* Disable speed/duplex control from these registers, datasheet 438 * says switch registers should be used to setup switch port 439 * speed and duplex. 440 */ 441 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 442 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 443 } 444 445 return 0; 446 } 447 448 static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count) 449 { 450 int i; 451 452 for (i = 0; i < count; i++) { 453 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 454 continue; 455 456 if (dt_val[i] != table_val[i]) 457 return false; 458 } 459 460 return true; 461 } 462 463 static void miic_dump_conf(struct miic *miic, s8 *conf) 464 { 465 const struct miic_of_data *of_data = miic->of_data; 466 const char *conf_name; 467 int i; 468 469 for (i = 0; i < of_data->conf_conv_count; i++) { 470 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 471 conf_name = of_data->conf_to_string[conf[i]]; 472 else 473 conf_name = "NONE"; 474 475 dev_err(miic->dev, "%s: %s\n", 476 of_data->index_to_string[i], conf_name); 477 } 478 } 479 480 static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg) 481 { 482 const struct miic_of_data *of_data = miic->of_data; 483 struct modctrl_match *table_entry; 484 int i; 485 486 for (i = 0; i < of_data->match_table_count; i++) { 487 table_entry = &of_data->match_table[i]; 488 489 if (miic_modctrl_match(table_entry->conv, dt_val, 490 miic->of_data->conf_conv_count)) { 491 *mode_cfg = table_entry->mode_cfg; 492 return 0; 493 } 494 } 495 496 dev_err(miic->dev, "Failed to apply requested configuration\n"); 497 miic_dump_conf(miic, dt_val); 498 499 return -EINVAL; 500 } 501 502 static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) 503 { 504 struct device_node *np = miic->dev->of_node; 505 struct device_node *conv; 506 int port, ret; 507 s8 *dt_val; 508 u32 conf; 509 510 dt_val = kmalloc_array(miic->of_data->conf_conv_count, 511 sizeof(*dt_val), GFP_KERNEL); 512 if (!dt_val) 513 return -ENOMEM; 514 515 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val)); 516 517 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 518 dt_val[0] = conf; 519 520 for_each_available_child_of_node(np, conv) { 521 if (of_property_read_u32(conv, "reg", &port)) 522 continue; 523 524 /* Adjust for 0 based index */ 525 port += !miic->of_data->miic_port_start; 526 if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0) 527 dt_val[port] = conf; 528 } 529 530 ret = miic_match_dt_conf(miic, dt_val, mode_cfg); 531 kfree(dt_val); 532 533 return ret; 534 } 535 536 static void miic_reset_control_bulk_assert(void *data) 537 { 538 struct miic *miic = data; 539 int ret; 540 541 ret = reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts); 542 if (ret) 543 dev_err(miic->dev, "failed to assert reset lines\n"); 544 } 545 546 static int miic_reset_control_init(struct miic *miic) 547 { 548 const struct miic_of_data *of_data = miic->of_data; 549 struct device *dev = miic->dev; 550 int ret; 551 u8 i; 552 553 if (!of_data->reset_count) 554 return 0; 555 556 for (i = 0; i < of_data->reset_count; i++) 557 miic->rsts[i].id = of_data->reset_ids[i]; 558 559 ret = devm_reset_control_bulk_get_exclusive(dev, of_data->reset_count, 560 miic->rsts); 561 if (ret) 562 return dev_err_probe(dev, ret, 563 "failed to get bulk reset lines\n"); 564 565 ret = reset_control_bulk_deassert(of_data->reset_count, miic->rsts); 566 if (ret) 567 return dev_err_probe(dev, ret, 568 "failed to deassert reset lines\n"); 569 570 ret = devm_add_action_or_reset(dev, miic_reset_control_bulk_assert, 571 miic); 572 if (ret) 573 return dev_err_probe(dev, ret, "failed to add reset action\n"); 574 575 return 0; 576 } 577 578 static int miic_probe(struct platform_device *pdev) 579 { 580 struct device *dev = &pdev->dev; 581 struct miic *miic; 582 u32 mode_cfg; 583 int ret; 584 585 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 586 if (!miic) 587 return -ENOMEM; 588 589 miic->of_data = of_device_get_match_data(dev); 590 miic->dev = dev; 591 592 ret = miic_parse_dt(miic, &mode_cfg); 593 if (ret < 0) 594 return ret; 595 596 spin_lock_init(&miic->lock); 597 miic->base = devm_platform_ioremap_resource(pdev, 0); 598 if (IS_ERR(miic->base)) 599 return PTR_ERR(miic->base); 600 601 ret = miic_reset_control_init(miic); 602 if (ret) 603 return ret; 604 605 ret = devm_pm_runtime_enable(dev); 606 if (ret < 0) 607 return ret; 608 609 ret = pm_runtime_resume_and_get(dev); 610 if (ret < 0) 611 return ret; 612 613 ret = miic_init_hw(miic, mode_cfg); 614 if (ret) 615 goto disable_runtime_pm; 616 617 /* miic_create() relies on that fact that data are attached to the 618 * platform device to determine if the driver is ready so this needs to 619 * be the last thing to be done after everything is initialized 620 * properly. 621 */ 622 platform_set_drvdata(pdev, miic); 623 624 return 0; 625 626 disable_runtime_pm: 627 pm_runtime_put(dev); 628 629 return ret; 630 } 631 632 static void miic_remove(struct platform_device *pdev) 633 { 634 pm_runtime_put(&pdev->dev); 635 } 636 637 static struct miic_of_data rzn1_miic_of_data = { 638 .match_table = modctrl_match_table, 639 .match_table_count = ARRAY_SIZE(modctrl_match_table), 640 .conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX, 641 .conf_to_string = conf_to_string, 642 .conf_to_string_count = ARRAY_SIZE(conf_to_string), 643 .index_to_string = index_to_string, 644 .index_to_string_count = ARRAY_SIZE(index_to_string), 645 .miic_port_start = 1, 646 .miic_port_max = 5, 647 .sw_mode_mask = GENMASK(4, 0), 648 }; 649 650 static const struct of_device_id miic_of_mtable[] = { 651 { .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data }, 652 { /* sentinel */ } 653 }; 654 MODULE_DEVICE_TABLE(of, miic_of_mtable); 655 656 static struct platform_driver miic_driver = { 657 .driver = { 658 .name = "rzn1_miic", 659 .suppress_bind_attrs = true, 660 .of_match_table = miic_of_mtable, 661 }, 662 .probe = miic_probe, 663 .remove = miic_remove, 664 }; 665 module_platform_driver(miic_driver); 666 667 MODULE_LICENSE("GPL"); 668 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 669 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 670