1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018-2019 MediaTek Inc. 3 /* A library for MediaTek SGMII circuit 4 * 5 * Author: Sean Wang <sean.wang@mediatek.com> 6 * Author: Alexander Couzens <lynxis@fe80.eu> 7 * Author: Daniel Golle <daniel@makrotopia.org> 8 * 9 */ 10 11 #include <linux/mdio.h> 12 #include <linux/of.h> 13 #include <linux/pcs/pcs-mtk-lynxi.h> 14 #include <linux/phy/phy-common-props.h> 15 #include <linux/phylink.h> 16 #include <linux/regmap.h> 17 18 /* SGMII subsystem config registers */ 19 /* BMCR (low 16) BMSR (high 16) */ 20 #define SGMSYS_PCS_CONTROL_1 0x0 21 #define SGMII_BMCR GENMASK(15, 0) 22 #define SGMII_BMSR GENMASK(31, 16) 23 24 #define SGMSYS_PCS_DEVICE_ID 0x4 25 #define SGMII_LYNXI_DEV_ID 0x4d544950 26 27 #define SGMSYS_PCS_ADVERTISE 0x8 28 #define SGMII_ADVERTISE GENMASK(15, 0) 29 #define SGMII_LPA GENMASK(31, 16) 30 31 #define SGMSYS_PCS_SCRATCH 0x14 32 #define SGMII_DEV_VERSION GENMASK(31, 16) 33 34 /* Register to programmable link timer, the unit in 2 * 8ns */ 35 #define SGMSYS_PCS_LINK_TIMER 0x18 36 #define SGMII_LINK_TIMER_MASK GENMASK(19, 0) 37 #define SGMII_LINK_TIMER_VAL(ns) FIELD_PREP(SGMII_LINK_TIMER_MASK, \ 38 ((ns) / 2 / 8)) 39 40 /* Register to control remote fault */ 41 #define SGMSYS_SGMII_MODE 0x20 42 #define SGMII_IF_MODE_SGMII BIT(0) 43 #define SGMII_SPEED_DUPLEX_AN BIT(1) 44 #define SGMII_SPEED_MASK GENMASK(3, 2) 45 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) 46 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) 47 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) 48 #define SGMII_DUPLEX_HALF BIT(4) 49 #define SGMII_REMOTE_FAULT_DIS BIT(8) 50 51 /* Register to reset SGMII design */ 52 #define SGMSYS_RESERVED_0 0x34 53 #define SGMII_SW_RESET BIT(0) 54 55 /* Register to set SGMII speed, ANA RG_ Control Signals III */ 56 #define SGMII_PHY_SPEED_MASK GENMASK(3, 2) 57 #define SGMII_PHY_SPEED_1_25G FIELD_PREP(SGMII_PHY_SPEED_MASK, 0) 58 #define SGMII_PHY_SPEED_3_125G FIELD_PREP(SGMII_PHY_SPEED_MASK, 1) 59 60 /* Register to power up QPHY */ 61 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 62 #define SGMII_PHYA_PWD BIT(4) 63 64 /* Register to QPHY wrapper control */ 65 #define SGMSYS_QPHY_WRAP_CTRL 0xec 66 #define SGMII_PN_SWAP_RX BIT(1) 67 #define SGMII_PN_SWAP_TX BIT(0) 68 69 70 /* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated 71 * data 72 * @regmap: The register map pointing at the range used to setup 73 * SGMII modes 74 * @dev: Pointer to device owning the PCS 75 * @ana_rgc3: The offset of register ANA_RGC3 relative to regmap 76 * @interface: Currently configured interface mode 77 * @pcs: Phylink PCS structure 78 * @flags: Flags indicating hardware properties 79 */ 80 struct mtk_pcs_lynxi { 81 struct regmap *regmap; 82 u32 ana_rgc3; 83 phy_interface_t interface; 84 struct phylink_pcs pcs; 85 u32 flags; 86 struct fwnode_handle *fwnode; 87 }; 88 89 static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs) 90 { 91 return container_of(pcs, struct mtk_pcs_lynxi, pcs); 92 } 93 94 static unsigned int mtk_pcs_lynxi_inband_caps(struct phylink_pcs *pcs, 95 phy_interface_t interface) 96 { 97 switch (interface) { 98 case PHY_INTERFACE_MODE_1000BASEX: 99 case PHY_INTERFACE_MODE_2500BASEX: 100 case PHY_INTERFACE_MODE_SGMII: 101 return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE; 102 103 default: 104 return 0; 105 } 106 } 107 108 static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, 109 unsigned int neg_mode, 110 struct phylink_link_state *state) 111 { 112 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); 113 unsigned int bm, adv; 114 115 /* Read the BMSR and LPA */ 116 if (regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm) || 117 regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv)) { 118 state->link = false; 119 return; 120 } 121 122 phylink_mii_c22_pcs_decode_state(state, neg_mode, 123 FIELD_GET(SGMII_BMSR, bm), 124 FIELD_GET(SGMII_LPA, adv)); 125 } 126 127 static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs, 128 phy_interface_t interface) 129 { 130 struct fwnode_handle *fwnode = mpcs->fwnode, *pcs_fwnode; 131 unsigned int pol, default_pol = PHY_POL_NORMAL; 132 unsigned int val = 0; 133 int ret; 134 135 if (!fwnode) 136 return 0; 137 138 if (fwnode_property_read_bool(fwnode, "mediatek,pnswap")) 139 default_pol = PHY_POL_INVERT; 140 141 pcs_fwnode = fwnode_get_named_child_node(fwnode, "pcs"); 142 143 ret = phy_get_rx_polarity(pcs_fwnode, phy_modes(interface), 144 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), 145 default_pol, &pol); 146 if (ret) { 147 fwnode_handle_put(pcs_fwnode); 148 return ret; 149 } 150 if (pol == PHY_POL_INVERT) 151 val |= SGMII_PN_SWAP_RX; 152 153 ret = phy_get_tx_polarity(pcs_fwnode, phy_modes(interface), 154 BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), 155 default_pol, &pol); 156 fwnode_handle_put(pcs_fwnode); 157 if (ret) 158 return ret; 159 if (pol == PHY_POL_INVERT) 160 val |= SGMII_PN_SWAP_TX; 161 162 return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, 163 SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val); 164 } 165 166 static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode, 167 phy_interface_t interface, 168 const unsigned long *advertising, 169 bool permit_pause_to_mac) 170 { 171 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); 172 bool mode_changed = false, changed; 173 unsigned int rgc3, sgm_mode, bmcr; 174 int advertise, link_timer; 175 int ret; 176 177 advertise = phylink_mii_c22_pcs_encode_advertisement(interface, 178 advertising); 179 if (advertise < 0) 180 return advertise; 181 182 /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and 183 * we assume that fixes it's speed at bitrate = line rate (in 184 * other words, 1000Mbps or 2500Mbps). 185 */ 186 if (interface == PHY_INTERFACE_MODE_SGMII) 187 sgm_mode = SGMII_IF_MODE_SGMII; 188 else 189 sgm_mode = 0; 190 191 if (neg_mode & PHYLINK_PCS_NEG_INBAND) 192 sgm_mode |= SGMII_REMOTE_FAULT_DIS; 193 194 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 195 if (interface == PHY_INTERFACE_MODE_SGMII) 196 sgm_mode |= SGMII_SPEED_DUPLEX_AN; 197 bmcr = BMCR_ANENABLE; 198 } else { 199 bmcr = 0; 200 } 201 202 if (mpcs->interface != interface) { 203 link_timer = phylink_get_link_timer_ns(interface); 204 if (link_timer < 0) 205 return link_timer; 206 207 /* PHYA power down */ 208 regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 209 SGMII_PHYA_PWD); 210 211 /* Reset SGMII PCS state */ 212 regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0, 213 SGMII_SW_RESET); 214 215 ret = mtk_pcs_config_polarity(mpcs, interface); 216 if (ret) 217 return ret; 218 219 if (interface == PHY_INTERFACE_MODE_2500BASEX) 220 rgc3 = SGMII_PHY_SPEED_3_125G; 221 else 222 rgc3 = SGMII_PHY_SPEED_1_25G; 223 224 /* Configure the underlying interface speed */ 225 regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3, 226 SGMII_PHY_SPEED_MASK, rgc3); 227 228 /* Setup the link timer */ 229 regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, 230 SGMII_LINK_TIMER_VAL(link_timer)); 231 232 mpcs->interface = interface; 233 mode_changed = true; 234 } 235 236 /* Update the advertisement, noting whether it has changed */ 237 regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE, 238 SGMII_ADVERTISE, advertise, &changed); 239 240 /* Update the sgmsys mode register */ 241 regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, 242 SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN | 243 SGMII_IF_MODE_SGMII, sgm_mode); 244 245 /* Update the BMCR */ 246 regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, 247 BMCR_ANENABLE, bmcr); 248 249 /* Release PHYA power down state 250 * Only removing bit SGMII_PHYA_PWD isn't enough. 251 * There are cases when the SGMII_PHYA_PWD register contains 0x9 which 252 * prevents SGMII from working. The SGMII still shows link but no traffic 253 * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was 254 * taken from a good working state of the SGMII interface. 255 * Unknown how much the QPHY needs but it is racy without a sleep. 256 * Tested on mt7622 & mt7986. 257 */ 258 usleep_range(50, 100); 259 regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); 260 261 return changed || mode_changed; 262 } 263 264 static void mtk_pcs_lynxi_restart_an(struct phylink_pcs *pcs) 265 { 266 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); 267 268 regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART); 269 } 270 271 static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs, 272 unsigned int neg_mode, 273 phy_interface_t interface, int speed, 274 int duplex) 275 { 276 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); 277 unsigned int sgm_mode; 278 279 if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { 280 /* Force the speed and duplex setting */ 281 if (speed == SPEED_10) 282 sgm_mode = SGMII_SPEED_10; 283 else if (speed == SPEED_100) 284 sgm_mode = SGMII_SPEED_100; 285 else 286 sgm_mode = SGMII_SPEED_1000; 287 288 if (duplex != DUPLEX_FULL) 289 sgm_mode |= SGMII_DUPLEX_HALF; 290 291 regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE, 292 SGMII_DUPLEX_HALF | SGMII_SPEED_MASK, 293 sgm_mode); 294 } 295 } 296 297 static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs) 298 { 299 struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); 300 301 mpcs->interface = PHY_INTERFACE_MODE_NA; 302 } 303 304 static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = { 305 .pcs_inband_caps = mtk_pcs_lynxi_inband_caps, 306 .pcs_get_state = mtk_pcs_lynxi_get_state, 307 .pcs_config = mtk_pcs_lynxi_config, 308 .pcs_an_restart = mtk_pcs_lynxi_restart_an, 309 .pcs_link_up = mtk_pcs_lynxi_link_up, 310 .pcs_disable = mtk_pcs_lynxi_disable, 311 }; 312 313 struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, 314 struct fwnode_handle *fwnode, 315 struct regmap *regmap, u32 ana_rgc3) 316 { 317 struct mtk_pcs_lynxi *mpcs; 318 u32 id, ver; 319 int ret; 320 321 ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id); 322 if (ret < 0) 323 return NULL; 324 325 if (id != SGMII_LYNXI_DEV_ID) { 326 dev_err(dev, "unknown PCS device id %08x\n", id); 327 return NULL; 328 } 329 330 ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver); 331 if (ret < 0) 332 return NULL; 333 334 ver = FIELD_GET(SGMII_DEV_VERSION, ver); 335 if (ver != 0x1) { 336 dev_err(dev, "unknown PCS device version %04x\n", ver); 337 return NULL; 338 } 339 340 dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id, 341 ver); 342 343 mpcs = kzalloc_obj(*mpcs); 344 if (!mpcs) 345 return NULL; 346 347 mpcs->ana_rgc3 = ana_rgc3; 348 mpcs->regmap = regmap; 349 mpcs->pcs.ops = &mtk_pcs_lynxi_ops; 350 mpcs->pcs.poll = true; 351 mpcs->interface = PHY_INTERFACE_MODE_NA; 352 mpcs->fwnode = fwnode_handle_get(fwnode); 353 354 __set_bit(PHY_INTERFACE_MODE_SGMII, mpcs->pcs.supported_interfaces); 355 __set_bit(PHY_INTERFACE_MODE_1000BASEX, mpcs->pcs.supported_interfaces); 356 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mpcs->pcs.supported_interfaces); 357 358 return &mpcs->pcs; 359 } 360 EXPORT_SYMBOL(mtk_pcs_lynxi_create); 361 362 void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs) 363 { 364 struct mtk_pcs_lynxi *mpcs; 365 366 if (!pcs) 367 return; 368 369 mpcs = pcs_to_mtk_pcs_lynxi(pcs); 370 fwnode_handle_put(mpcs->fwnode); 371 kfree(mpcs); 372 } 373 EXPORT_SYMBOL(mtk_pcs_lynxi_destroy); 374 375 MODULE_DESCRIPTION("MediaTek SGMII library for LynxI"); 376 MODULE_LICENSE("GPL"); 377