1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Broadcom UniMAC MDIO bus controller driver 4 * 5 * Copyright (C) 2014-2017 Broadcom 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_platform.h> 16 #include <linux/phy.h> 17 #include <linux/platform_data/mdio-bcm-unimac.h> 18 #include <linux/platform_device.h> 19 #include <linux/sched.h> 20 21 #define MDIO_CMD 0x00 22 #define MDIO_START_BUSY (1 << 29) 23 #define MDIO_READ_FAIL (1 << 28) 24 #define MDIO_RD (2 << 26) 25 #define MDIO_WR (1 << 26) 26 #define MDIO_PMD_SHIFT 21 27 #define MDIO_PMD_MASK 0x1F 28 #define MDIO_REG_SHIFT 16 29 #define MDIO_REG_MASK 0x1F 30 31 #define MDIO_CFG 0x04 32 #define MDIO_C22 (1 << 0) 33 #define MDIO_C45 0 34 #define MDIO_CLK_DIV_SHIFT 4 35 #define MDIO_CLK_DIV_MASK 0x3F 36 #define MDIO_SUPP_PREAMBLE (1 << 12) 37 38 struct unimac_mdio_priv { 39 struct mii_bus *mii_bus; 40 void __iomem *base; 41 int (*wait_func) (void *wait_func_data); 42 void *wait_func_data; 43 struct clk *clk; 44 u32 clk_freq; 45 }; 46 47 static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset) 48 { 49 /* MIPS chips strapped for BE will automagically configure the 50 * peripheral registers for CPU-native byte order. 51 */ 52 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 53 return __raw_readl(priv->base + offset); 54 else 55 return readl_relaxed(priv->base + offset); 56 } 57 58 static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val, 59 u32 offset) 60 { 61 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 62 __raw_writel(val, priv->base + offset); 63 else 64 writel_relaxed(val, priv->base + offset); 65 } 66 67 static inline void unimac_mdio_start(struct unimac_mdio_priv *priv) 68 { 69 u32 reg; 70 71 reg = unimac_mdio_readl(priv, MDIO_CMD); 72 reg |= MDIO_START_BUSY; 73 unimac_mdio_writel(priv, reg, MDIO_CMD); 74 } 75 76 static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv) 77 { 78 return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY; 79 } 80 81 static int unimac_mdio_poll(void *wait_func_data) 82 { 83 struct unimac_mdio_priv *priv = wait_func_data; 84 unsigned int timeout = 100; 85 86 /* 87 * C22 transactions should take ~25 usec, will need to adjust 88 * if C45 support is added. 89 */ 90 udelay(30); 91 92 do { 93 if (!unimac_mdio_busy(priv)) 94 return 0; 95 96 usleep_range(1000, 2000); 97 } while (--timeout); 98 99 return -ETIMEDOUT; 100 } 101 102 static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg) 103 { 104 struct unimac_mdio_priv *priv = bus->priv; 105 int ret; 106 u32 cmd; 107 108 /* Prepare the read operation */ 109 cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); 110 unimac_mdio_writel(priv, cmd, MDIO_CMD); 111 112 /* Start MDIO transaction */ 113 unimac_mdio_start(priv); 114 115 ret = priv->wait_func(priv->wait_func_data); 116 if (ret) 117 return ret; 118 119 cmd = unimac_mdio_readl(priv, MDIO_CMD); 120 121 /* Some broken devices are known not to release the line during 122 * turn-around, e.g: Broadcom BCM53125 external switches, so check for 123 * that condition here and ignore the MDIO controller read failure 124 * indication. 125 */ 126 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL)) 127 return -EIO; 128 129 return cmd & 0xffff; 130 } 131 132 static int unimac_mdio_write(struct mii_bus *bus, int phy_id, 133 int reg, u16 val) 134 { 135 struct unimac_mdio_priv *priv = bus->priv; 136 u32 cmd; 137 138 /* Prepare the write operation */ 139 cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 140 (reg << MDIO_REG_SHIFT) | (0xffff & val); 141 unimac_mdio_writel(priv, cmd, MDIO_CMD); 142 143 unimac_mdio_start(priv); 144 145 return priv->wait_func(priv->wait_func_data); 146 } 147 148 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with 149 * their internal MDIO management controller making them fail to successfully 150 * be read from or written to for the first transaction. We insert a dummy 151 * BMSR read here to make sure that phy_get_device() and get_phy_id() can 152 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a 153 * PHY device for this peripheral. 154 * 155 * Once the PHY driver is registered, we can workaround subsequent reads from 156 * there (e.g: during system-wide power management). 157 * 158 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is 159 * therefore the right location to stick that workaround. Since we do not want 160 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual 161 * Device Tree scan to limit the search area. 162 */ 163 static int unimac_mdio_reset(struct mii_bus *bus) 164 { 165 struct device_node *np = bus->dev.of_node; 166 struct device_node *child; 167 u32 read_mask = 0; 168 int addr; 169 170 if (!np) { 171 read_mask = ~bus->phy_mask; 172 } else { 173 for_each_available_child_of_node(np, child) { 174 addr = of_mdio_parse_addr(&bus->dev, child); 175 if (addr < 0) 176 continue; 177 178 read_mask |= 1 << addr; 179 } 180 } 181 182 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 183 if (read_mask & 1 << addr) { 184 dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr); 185 mdiobus_read(bus, addr, MII_BMSR); 186 } 187 } 188 189 return 0; 190 } 191 192 static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv) 193 { 194 unsigned long rate; 195 u32 reg, div; 196 197 /* Keep the hardware default values */ 198 if (!priv->clk_freq) 199 return; 200 201 if (!priv->clk) 202 rate = 250000000; 203 else 204 rate = clk_get_rate(priv->clk); 205 206 div = (rate / (2 * priv->clk_freq)) - 1; 207 if (div & ~MDIO_CLK_DIV_MASK) { 208 pr_warn("Incorrect MDIO clock frequency, ignoring\n"); 209 return; 210 } 211 212 /* The MDIO clock is the reference clock (typically 250Mhz) divided by 213 * 2 x (MDIO_CLK_DIV + 1) 214 */ 215 reg = unimac_mdio_readl(priv, MDIO_CFG); 216 reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT); 217 reg |= div << MDIO_CLK_DIV_SHIFT; 218 unimac_mdio_writel(priv, reg, MDIO_CFG); 219 } 220 221 static int unimac_mdio_probe(struct platform_device *pdev) 222 { 223 struct unimac_mdio_pdata *pdata = pdev->dev.platform_data; 224 struct unimac_mdio_priv *priv; 225 struct device_node *np; 226 struct mii_bus *bus; 227 struct resource *r; 228 int ret; 229 230 np = pdev->dev.of_node; 231 232 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 233 if (!priv) 234 return -ENOMEM; 235 236 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 237 if (!r) 238 return -EINVAL; 239 240 /* Just ioremap, as this MDIO block is usually integrated into an 241 * Ethernet MAC controller register range 242 */ 243 priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 244 if (!priv->base) { 245 dev_err(&pdev->dev, "failed to remap register\n"); 246 return -ENOMEM; 247 } 248 249 priv->clk = devm_clk_get_optional(&pdev->dev, NULL); 250 if (IS_ERR(priv->clk)) 251 return PTR_ERR(priv->clk); 252 253 ret = clk_prepare_enable(priv->clk); 254 if (ret) 255 return ret; 256 257 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) 258 priv->clk_freq = 0; 259 260 unimac_mdio_clk_set(priv); 261 262 priv->mii_bus = mdiobus_alloc(); 263 if (!priv->mii_bus) { 264 ret = -ENOMEM; 265 goto out_clk_disable; 266 } 267 268 bus = priv->mii_bus; 269 bus->priv = priv; 270 if (pdata) { 271 bus->name = pdata->bus_name; 272 priv->wait_func = pdata->wait_func; 273 priv->wait_func_data = pdata->wait_func_data; 274 bus->phy_mask = ~pdata->phy_mask; 275 } else { 276 bus->name = "unimac MII bus"; 277 priv->wait_func_data = priv; 278 priv->wait_func = unimac_mdio_poll; 279 } 280 bus->parent = &pdev->dev; 281 bus->read = unimac_mdio_read; 282 bus->write = unimac_mdio_write; 283 bus->reset = unimac_mdio_reset; 284 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id); 285 286 ret = of_mdiobus_register(bus, np); 287 if (ret) { 288 dev_err(&pdev->dev, "MDIO bus registration failed\n"); 289 goto out_mdio_free; 290 } 291 292 platform_set_drvdata(pdev, priv); 293 294 dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n"); 295 296 return 0; 297 298 out_mdio_free: 299 mdiobus_free(bus); 300 out_clk_disable: 301 clk_disable_unprepare(priv->clk); 302 return ret; 303 } 304 305 static void unimac_mdio_remove(struct platform_device *pdev) 306 { 307 struct unimac_mdio_priv *priv = platform_get_drvdata(pdev); 308 309 mdiobus_unregister(priv->mii_bus); 310 mdiobus_free(priv->mii_bus); 311 clk_disable_unprepare(priv->clk); 312 } 313 314 static int __maybe_unused unimac_mdio_suspend(struct device *d) 315 { 316 struct unimac_mdio_priv *priv = dev_get_drvdata(d); 317 318 clk_disable_unprepare(priv->clk); 319 320 return 0; 321 } 322 323 static int __maybe_unused unimac_mdio_resume(struct device *d) 324 { 325 struct unimac_mdio_priv *priv = dev_get_drvdata(d); 326 int ret; 327 328 ret = clk_prepare_enable(priv->clk); 329 if (ret) 330 return ret; 331 332 unimac_mdio_clk_set(priv); 333 334 return 0; 335 } 336 337 static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops, 338 unimac_mdio_suspend, unimac_mdio_resume); 339 340 static const struct of_device_id unimac_mdio_ids[] = { 341 { .compatible = "brcm,asp-v2.1-mdio", }, 342 { .compatible = "brcm,asp-v2.0-mdio", }, 343 { .compatible = "brcm,genet-mdio-v5", }, 344 { .compatible = "brcm,genet-mdio-v4", }, 345 { .compatible = "brcm,genet-mdio-v3", }, 346 { .compatible = "brcm,genet-mdio-v2", }, 347 { .compatible = "brcm,genet-mdio-v1", }, 348 { .compatible = "brcm,unimac-mdio", }, 349 { /* sentinel */ }, 350 }; 351 MODULE_DEVICE_TABLE(of, unimac_mdio_ids); 352 353 static struct platform_driver unimac_mdio_driver = { 354 .driver = { 355 .name = UNIMAC_MDIO_DRV_NAME, 356 .of_match_table = unimac_mdio_ids, 357 .pm = &unimac_mdio_pm_ops, 358 }, 359 .probe = unimac_mdio_probe, 360 .remove_new = unimac_mdio_remove, 361 }; 362 module_platform_driver(unimac_mdio_driver); 363 364 MODULE_AUTHOR("Broadcom Corporation"); 365 MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller"); 366 MODULE_LICENSE("GPL"); 367 MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME); 368