1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 /* Bit 4 reserved */ 18 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 19 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 30 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17), 31 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 32 [GENQMB_AOOOWR] = BIT(20), 33 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 34 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22), 35 /* Bits 25-29 reserved */ 36 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 37 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 38 }; 39 40 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 41 42 static const u32 reg_clkon_cfg_fmask[] = { 43 [CLKON_RX] = BIT(0), 44 [CLKON_PROC] = BIT(1), 45 [TX_WRAPPER] = BIT(2), 46 [CLKON_MISC] = BIT(3), 47 [RAM_ARB] = BIT(4), 48 [FTCH_HPS] = BIT(5), 49 [FTCH_DPS] = BIT(6), 50 [CLKON_HPS] = BIT(7), 51 [CLKON_DPS] = BIT(8), 52 [RX_HPS_CMDQS] = BIT(9), 53 [HPS_DPS_CMDQS] = BIT(10), 54 [DPS_TX_CMDQS] = BIT(11), 55 [RSRC_MNGR] = BIT(12), 56 [CTX_HANDLER] = BIT(13), 57 [ACK_MNGR] = BIT(14), 58 [D_DCPH] = BIT(15), 59 [H_DCPH] = BIT(16), 60 [CLKON_DCMP] = BIT(17), 61 [NTF_TX_CMDQS] = BIT(18), 62 [CLKON_TX_0] = BIT(19), 63 [CLKON_TX_1] = BIT(20), 64 [CLKON_FNR] = BIT(21), 65 [QSB2AXI_CMDQ_L] = BIT(22), 66 [AGGR_WRAPPER] = BIT(23), 67 [RAM_SLAVEWAY] = BIT(24), 68 [CLKON_QMB] = BIT(25), 69 [WEIGHT_ARB] = BIT(26), 70 [GSI_IF] = BIT(27), 71 [CLKON_GLOBAL] = BIT(28), 72 [GLOBAL_2X_CLK] = BIT(29), 73 [DPL_FIFO] = BIT(30), 74 [DRBIP] = BIT(31), 75 }; 76 77 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 78 79 static const u32 reg_route_fmask[] = { 80 [ROUTE_DIS] = BIT(0), 81 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 82 [ROUTE_DEF_HDR_TABLE] = BIT(6), 83 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 84 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 85 /* Bits 22-23 reserved */ 86 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 87 /* Bits 25-31 reserved */ 88 }; 89 90 REG_FIELDS(ROUTE, route, 0x00000048); 91 92 static const u32 reg_shared_mem_size_fmask[] = { 93 [MEM_SIZE] = GENMASK(15, 0), 94 [MEM_BADDR] = GENMASK(31, 16), 95 }; 96 97 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 98 99 static const u32 reg_qsb_max_writes_fmask[] = { 100 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 101 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 102 /* Bits 8-31 reserved */ 103 }; 104 105 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 106 107 static const u32 reg_qsb_max_reads_fmask[] = { 108 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 109 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 110 /* Bits 8-15 reserved */ 111 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 112 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 113 }; 114 115 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 116 117 static const u32 reg_filt_rout_hash_flush_fmask[] = { 118 [IPV6_ROUTER_HASH] = BIT(0), 119 /* Bits 1-3 reserved */ 120 [IPV6_FILTER_HASH] = BIT(4), 121 /* Bits 5-7 reserved */ 122 [IPV4_ROUTER_HASH] = BIT(8), 123 /* Bits 9-11 reserved */ 124 [IPV4_FILTER_HASH] = BIT(12), 125 /* Bits 13-31 reserved */ 126 }; 127 128 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 129 130 /* Valid bits defined by ipa->available */ 131 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 132 133 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 134 [IPA_BASE_ADDR] = GENMASK(17, 0), 135 /* Bits 18-31 reserved */ 136 }; 137 138 /* Offset must be a multiple of 8 */ 139 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 140 141 /* Valid bits defined by ipa->available */ 142 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 143 144 static const u32 reg_ipa_tx_cfg_fmask[] = { 145 /* Bits 0-1 reserved */ 146 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 147 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 148 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 149 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 150 [PA_MASK_EN] = BIT(12), 151 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 152 [DUAL_TX_ENABLE] = BIT(17), 153 [SSPND_PA_NO_START_STATE] = BIT(18), 154 /* Bits 19-31 reserved */ 155 }; 156 157 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 158 159 static const u32 reg_flavor_0_fmask[] = { 160 [MAX_PIPES] = GENMASK(3, 0), 161 /* Bits 4-7 reserved */ 162 [MAX_CONS_PIPES] = GENMASK(12, 8), 163 /* Bits 13-15 reserved */ 164 [MAX_PROD_PIPES] = GENMASK(20, 16), 165 /* Bits 21-23 reserved */ 166 [PROD_LOWEST] = GENMASK(27, 24), 167 /* Bits 28-31 reserved */ 168 }; 169 170 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 171 172 static const u32 reg_idle_indication_cfg_fmask[] = { 173 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 174 [CONST_NON_IDLE_ENABLE] = BIT(16), 175 /* Bits 17-31 reserved */ 176 }; 177 178 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 179 180 static const u32 reg_qtime_timestamp_cfg_fmask[] = { 181 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 182 /* Bits 5-6 reserved */ 183 [DPL_TIMESTAMP_SEL] = BIT(7), 184 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 185 /* Bits 13-15 reserved */ 186 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 187 /* Bits 21-31 reserved */ 188 }; 189 190 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 191 192 static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 193 [DIV_VALUE] = GENMASK(8, 0), 194 /* Bits 9-30 reserved */ 195 [DIV_ENABLE] = BIT(31), 196 }; 197 198 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 199 200 static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 201 [PULSE_GRAN_0] = GENMASK(2, 0), 202 [PULSE_GRAN_1] = GENMASK(5, 3), 203 [PULSE_GRAN_2] = GENMASK(8, 6), 204 }; 205 206 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 207 208 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 209 [X_MIN_LIM] = GENMASK(5, 0), 210 /* Bits 6-7 reserved */ 211 [X_MAX_LIM] = GENMASK(13, 8), 212 /* Bits 14-15 reserved */ 213 [Y_MIN_LIM] = GENMASK(21, 16), 214 /* Bits 22-23 reserved */ 215 [Y_MAX_LIM] = GENMASK(29, 24), 216 /* Bits 30-31 reserved */ 217 }; 218 219 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 220 0x00000400, 0x0020); 221 222 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 223 [X_MIN_LIM] = GENMASK(5, 0), 224 /* Bits 6-7 reserved */ 225 [X_MAX_LIM] = GENMASK(13, 8), 226 /* Bits 14-15 reserved */ 227 [Y_MIN_LIM] = GENMASK(21, 16), 228 /* Bits 22-23 reserved */ 229 [Y_MAX_LIM] = GENMASK(29, 24), 230 /* Bits 30-31 reserved */ 231 }; 232 233 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 234 0x00000404, 0x0020); 235 236 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 237 [X_MIN_LIM] = GENMASK(5, 0), 238 /* Bits 6-7 reserved */ 239 [X_MAX_LIM] = GENMASK(13, 8), 240 /* Bits 14-15 reserved */ 241 [Y_MIN_LIM] = GENMASK(21, 16), 242 /* Bits 22-23 reserved */ 243 [Y_MAX_LIM] = GENMASK(29, 24), 244 /* Bits 30-31 reserved */ 245 }; 246 247 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 248 0x00000500, 0x0020); 249 250 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 251 [X_MIN_LIM] = GENMASK(5, 0), 252 /* Bits 6-7 reserved */ 253 [X_MAX_LIM] = GENMASK(13, 8), 254 /* Bits 14-15 reserved */ 255 [Y_MIN_LIM] = GENMASK(21, 16), 256 /* Bits 22-23 reserved */ 257 [Y_MAX_LIM] = GENMASK(29, 24), 258 /* Bits 30-31 reserved */ 259 }; 260 261 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 262 0x00000504, 0x0020); 263 264 static const u32 reg_endp_init_cfg_fmask[] = { 265 [FRAG_OFFLOAD_EN] = BIT(0), 266 [CS_OFFLOAD_EN] = GENMASK(2, 1), 267 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 268 /* Bit 7 reserved */ 269 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 270 /* Bits 9-31 reserved */ 271 }; 272 273 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 274 275 static const u32 reg_endp_init_nat_fmask[] = { 276 [NAT_EN] = GENMASK(1, 0), 277 /* Bits 2-31 reserved */ 278 }; 279 280 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 281 282 static const u32 reg_endp_init_hdr_fmask[] = { 283 [HDR_LEN] = GENMASK(5, 0), 284 [HDR_OFST_METADATA_VALID] = BIT(6), 285 [HDR_OFST_METADATA] = GENMASK(12, 7), 286 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 287 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 288 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 289 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 290 [HDR_LEN_MSB] = GENMASK(29, 28), 291 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 292 }; 293 294 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 295 296 static const u32 reg_endp_init_hdr_ext_fmask[] = { 297 [HDR_ENDIANNESS] = BIT(0), 298 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 299 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 300 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 301 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 302 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 303 /* Bits 14-15 reserved */ 304 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 305 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 306 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 307 /* Bits 22-31 reserved */ 308 }; 309 310 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 311 312 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 313 0x00000818, 0x0070); 314 315 static const u32 reg_endp_init_mode_fmask[] = { 316 [ENDP_MODE] = GENMASK(2, 0), 317 [DCPH_ENABLE] = BIT(3), 318 [DEST_PIPE_INDEX] = GENMASK(8, 4), 319 /* Bits 9-11 reserved */ 320 [BYTE_THRESHOLD] = GENMASK(27, 12), 321 [PIPE_REPLICATION_EN] = BIT(28), 322 [PAD_EN] = BIT(29), 323 [DRBIP_ACL_ENABLE] = BIT(30), 324 /* Bit 31 reserved */ 325 }; 326 327 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 328 329 static const u32 reg_endp_init_aggr_fmask[] = { 330 [AGGR_EN] = GENMASK(1, 0), 331 [AGGR_TYPE] = GENMASK(4, 2), 332 [BYTE_LIMIT] = GENMASK(10, 5), 333 /* Bit 11 reserved */ 334 [TIME_LIMIT] = GENMASK(16, 12), 335 [PKT_LIMIT] = GENMASK(22, 17), 336 [SW_EOF_ACTIVE] = BIT(23), 337 [FORCE_CLOSE] = BIT(24), 338 /* Bit 25 reserved */ 339 [HARD_BYTE_LIMIT_EN] = BIT(26), 340 [AGGR_GRAN_SEL] = BIT(27), 341 /* Bits 28-31 reserved */ 342 }; 343 344 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 345 346 static const u32 reg_endp_init_hol_block_en_fmask[] = { 347 [HOL_BLOCK_EN] = BIT(0), 348 /* Bits 1-31 reserved */ 349 }; 350 351 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 352 0x0000082c, 0x0070); 353 354 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 355 [TIMER_LIMIT] = GENMASK(4, 0), 356 /* Bits 5-7 reserved */ 357 [TIMER_GRAN_SEL] = BIT(8), 358 /* Bits 9-31 reserved */ 359 }; 360 361 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 362 0x00000830, 0x0070); 363 364 static const u32 reg_endp_init_deaggr_fmask[] = { 365 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 366 [SYSPIPE_ERR_DETECTION] = BIT(6), 367 [PACKET_OFFSET_VALID] = BIT(7), 368 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 369 [IGNORE_MIN_PKT_ERR] = BIT(14), 370 /* Bit 15 reserved */ 371 [MAX_PACKET_LEN] = GENMASK(31, 16), 372 }; 373 374 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 375 376 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 377 [ENDP_RSRC_GRP] = GENMASK(1, 0), 378 /* Bits 2-31 reserved */ 379 }; 380 381 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 382 383 static const u32 reg_endp_init_seq_fmask[] = { 384 [SEQ_TYPE] = GENMASK(7, 0), 385 /* Bits 8-31 reserved */ 386 }; 387 388 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 389 390 static const u32 reg_endp_status_fmask[] = { 391 [STATUS_EN] = BIT(0), 392 [STATUS_ENDP] = GENMASK(5, 1), 393 /* Bits 6-8 reserved */ 394 [STATUS_PKT_SUPPRESS] = BIT(9), 395 /* Bits 10-31 reserved */ 396 }; 397 398 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 399 400 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 401 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 402 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 403 [FILTER_HASH_MSK_DST_IP] = BIT(2), 404 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 405 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 406 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 407 [FILTER_HASH_MSK_METADATA] = BIT(6), 408 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 409 /* Bits 7-15 reserved */ 410 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 411 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 412 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 413 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 414 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 415 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 416 [ROUTER_HASH_MSK_METADATA] = BIT(22), 417 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 418 /* Bits 23-31 reserved */ 419 }; 420 421 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 422 0x0000085c, 0x0070); 423 424 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 425 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); 426 427 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 428 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); 429 430 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 431 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); 432 433 static const u32 reg_ipa_irq_uc_fmask[] = { 434 [UC_INTR] = BIT(0), 435 /* Bits 1-31 reserved */ 436 }; 437 438 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); 439 440 /* Valid bits defined by ipa->available */ 441 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 442 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004); 443 444 /* Valid bits defined by ipa->available */ 445 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 446 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004); 447 448 /* Valid bits defined by ipa->available */ 449 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 450 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004); 451 452 static const struct reg *reg_array[] = { 453 [COMP_CFG] = ®_comp_cfg, 454 [CLKON_CFG] = ®_clkon_cfg, 455 [ROUTE] = ®_route, 456 [SHARED_MEM_SIZE] = ®_shared_mem_size, 457 [QSB_MAX_WRITES] = ®_qsb_max_writes, 458 [QSB_MAX_READS] = ®_qsb_max_reads, 459 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 460 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 461 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 462 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 463 [IPA_TX_CFG] = ®_ipa_tx_cfg, 464 [FLAVOR_0] = ®_flavor_0, 465 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 466 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 467 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 468 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 469 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 470 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 471 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 472 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 473 [ENDP_INIT_CFG] = ®_endp_init_cfg, 474 [ENDP_INIT_NAT] = ®_endp_init_nat, 475 [ENDP_INIT_HDR] = ®_endp_init_hdr, 476 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 477 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 478 [ENDP_INIT_MODE] = ®_endp_init_mode, 479 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 480 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 481 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 482 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 483 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 484 [ENDP_INIT_SEQ] = ®_endp_init_seq, 485 [ENDP_STATUS] = ®_endp_status, 486 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 487 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 488 [IPA_IRQ_EN] = ®_ipa_irq_en, 489 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 490 [IPA_IRQ_UC] = ®_ipa_irq_uc, 491 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 492 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 493 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 494 }; 495 496 const struct regs ipa_regs_v4_9 = { 497 .reg_count = ARRAY_SIZE(reg_array), 498 .reg = reg_array, 499 }; 500